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[/] [robust_axi2ahb/] [trunk/] [src/] [base/] [axi2ahb.v] - Blame information for rev 10

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1 10 eyalhoc
<##//////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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//////////////////////////////////////////////////////////////////##>
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INCLUDE def_axi2ahb.txt
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OUTFILE PREFIX.v
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CHECK CONST(#FFD)
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CHECK CONST(PREFIX)
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CHECK CONST(ADDR_BITS)
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CHECK CONST(DATA_BITS)
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CHECK CONST(ID_BITS)
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CHECK CONST(CMD_DEPTH)
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module  PREFIX (PORTS);
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   input              clk;
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   input              reset;
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   port               GROUP_AXI;
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   revport            GROUP_AHB;
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   //outputs of cmd
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   wire                   cmd_empty;
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   wire                   cmd_read;
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   wire [ID_BITS-1:0]     cmd_id;
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   wire [ADDR_BITS-1:0]   cmd_addr;
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   wire [3:0]             cmd_len;
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   wire [1:0]             cmd_size;
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   wire                   cmd_err;
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   //outputs of ctrl
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   wire                   ahb_finish;
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   wire                   data_last;
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   //outputs of wr fifo
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   wire                   wdata_phase;
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   wire                   wdata_ready;
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   //outputs of rd fifo
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   wire                   rdata_phase;
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   wire                   rdata_ready;
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   CREATE axi2ahb_cmd.v
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     PREFIX_cmd PREFIX_cmd(
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                                           .clk(clk),
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                                           .reset(reset),
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                                           .AWGROUP_AXI_A(AWGROUP_AXI_A),
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                                           .ARGROUP_AXI_A(ARGROUP_AXI_A),
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                                           .GROUP_AHB(GROUP_AHB),
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                                           .ahb_finish(ahb_finish),
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                                           .cmd_empty(cmd_empty),
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                                           .cmd_read(cmd_read),
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                                           .cmd_id(cmd_id),
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                                           .cmd_addr(cmd_addr),
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                                           .cmd_len(cmd_len),
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                                           .cmd_size(cmd_size),
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                                           .cmd_err(cmd_err)
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                                           );
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   CREATE axi2ahb_ctrl.v
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     PREFIX_ctrl PREFIX_ctrl(
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                                             .clk(clk),
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                                             .reset(reset),
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                                             .GROUP_AHB(GROUP_AHB),
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                                             .ahb_finish(ahb_finish),
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                                             .rdata_phase(rdata_phase),
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                                             .wdata_phase(wdata_phase),
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                                             .data_last(data_last),
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                                             .rdata_ready(rdata_ready),
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                                             .wdata_ready(wdata_ready),
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                                             .cmd_empty(cmd_empty),
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                                             .cmd_read(cmd_read),
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                                             .cmd_addr(cmd_addr),
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                                             .cmd_len(cmd_len),
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                                             .cmd_size(cmd_size)
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                                             );
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   CREATE axi2ahb_wr_fifo.v
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     PREFIX_wr_fifo
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       PREFIX_wr_fifo(
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                              .clk(clk),
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                              .reset(reset),
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                              .WGROUP_AXI_W(WGROUP_AXI_W),
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                              .BGROUP_AXI_B(BGROUP_AXI_B),
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                              .HWDATA(HWDATA),
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                              .HREADY(HREADY),
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                              .HTRANS(HTRANS),
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                              .HRESP(HRESP),
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                              .cmd_err(cmd_err),
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                              .wdata_phase(wdata_phase),
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                              .wdata_ready(wdata_ready),
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                              .data_last(data_last)
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                              );
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   CREATE axi2ahb_rd_fifo.v
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     PREFIX_rd_fifo
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       PREFIX_rd_fifo(
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                              .clk(clk),
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                              .reset(reset),
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                              .RGROUP_AXI_R(RGROUP_AXI_R),
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                              .HRDATA(HRDATA),
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                              .HREADY(HREADY),
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                              .HTRANS(HTRANS),
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                              .HRESP(HRESP),
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                              .cmd_id(cmd_id),
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                              .cmd_err(cmd_err),
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                              .rdata_phase(rdata_phase),
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                              .rdata_ready(rdata_ready),
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                              .data_last(data_last)
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                              );
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endmodule
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