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[/] [robust_axi2apb/] [trunk/] [src/] [base/] [axi2apb_mux.v] - Blame information for rev 2

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INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb_mux.v
 
ITER SX
module  PREFIX_axi2apb_mux (PORTS);
 
 
   input                      clk;
   input                      reset;
 
   input [ADDR_BITS-1:0]      cmd_addr;
 
   input                      psel;
   output [31:0]              prdata;
   output                     pready;
   output                     pslverr;
 
   output                     pselSX;
 
   input                      preadySX;
 
   input                      pslverrSX;
 
   input [31:0]               prdataSX;
 
 
 
   parameter                  ADDR_MSB = EXPR(ADDR_BITS-1);
   parameter                  ADDR_LSB = EXPR(ADDR_BITS-DEC_BITS);
 
   reg                        pready;
   reg                        pslverr_pre;
   reg                        pslverr;
   reg [31:0]                 prdata_pre;
   reg [31:0]                 prdata;
 
   reg [SLV_BITS-1:0]         slave_num;
 
   always @(*)
     begin
        casex (cmd_addr[ADDR_MSB:ADDR_LSB])
          DEC_ADDRSX : slave_num = SLV_BITS'dSX;
 
          default : slave_num = SLV_BITS'dSLAVE_NUM; //decode error
        endcase
     end
 
   assign                     pselSX = psel & (slave_num == SLV_BITS'dSX);
 
   always @(*)
     begin
           case (slave_num)
             SLV_BITS'dSX: pready = preadySX;
                 default : pready = 1'b1; //decode error
           endcase
         end
 
   always @(*)
     begin
           case (slave_num)
             SLV_BITS'dSX: pslverr_pre = pslverrSX;
                 default : pslverr_pre = 1'b1; //decode error
           endcase
         end
 
   always @(*)
     begin
           case (slave_num)
             SLV_BITS'dSX: prdata_pre = prdataSX;
                 default : prdata_pre = {32{1'b0}};
           endcase
         end
 
 
   always @(posedge clk or posedge reset)
     if (reset)
           begin
         prdata  <= #FFD {32{1'b0}};
         pslverr <= #FFD 1'b0;
           end
         else if (psel & pready)
           begin
         prdata  <= #FFD prdata_pre;
         pslverr <= #FFD pslverr_pre;
           end
         else if (~psel)
           begin
         prdata  <= #FFD {32{1'b0}};
         pslverr <= #FFD 1'b0;
           end
 
endmodule
 
 

Line No.	Rev	Author	Line
1	2	eyalhoc	`INCLUDE def_axi2apb.txt`
2			`OUTFILE PREFIX_axi2apb_mux.v`
3
4			`ITER SX`
5			`module PREFIX_axi2apb_mux (PORTS);`
6
7
8			`input clk;`
9			`input reset;`
10
11			`input [ADDR_BITS-1:0] cmd_addr;`
12
13			`input psel;`
14			`output [31:0] prdata;`
15			`output pready;`
16			`output pslverr;`
17
18			`output pselSX;`
19
20			`input preadySX;`
21
22			`input pslverrSX;`
23
24			`input [31:0] prdataSX;`
25
26
27
28			`parameter ADDR_MSB = EXPR(ADDR_BITS-1);`
29			`parameter ADDR_LSB = EXPR(ADDR_BITS-DEC_BITS);`
30
31			`reg pready;`
32			`reg pslverr_pre;`
33			`reg pslverr;`
34			`reg [31:0] prdata_pre;`
35			`reg [31:0] prdata;`
36
37			`reg [SLV_BITS-1:0] slave_num;`
38
39			`always @(*)`
40			`begin`
41			`casex (cmd_addr[ADDR_MSB:ADDR_LSB])`
42			`DEC_ADDRSX : slave_num = SLV_BITS'dSX;`
43
44			`default : slave_num = SLV_BITS'dSLAVE_NUM; //decode error`
45			`endcase`
46			`end`
47
48			`assign pselSX = psel & (slave_num == SLV_BITS'dSX);`
49
50			`always @(*)`
51			`begin`
52			`case (slave_num)`
53			`SLV_BITS'dSX: pready = preadySX;`
54			`default : pready = 1'b1; //decode error`
55			`endcase`
56			`end`
57
58			`always @(*)`
59			`begin`
60			`case (slave_num)`
61			`SLV_BITS'dSX: pslverr_pre = pslverrSX;`
62			`default : pslverr_pre = 1'b1; //decode error`
63			`endcase`
64			`end`
65
66			`always @(*)`
67			`begin`
68			`case (slave_num)`
69			`SLV_BITS'dSX: prdata_pre = prdataSX;`
70			`default : prdata_pre = {32{1'b0}};`
71			`endcase`
72			`end`
73
74
75			`always @(posedge clk or posedge reset)`
76			`if (reset)`
77			`begin`
78			`prdata <= #FFD {32{1'b0}};`
79			`pslverr <= #FFD 1'b0;`
80			`end`
81			`else if (psel & pready)`
82			`begin`
83			`prdata <= #FFD prdata_pre;`
84			`pslverr <= #FFD pslverr_pre;`
85			`end`
86			`else if (~psel)`
87			`begin`
88			`prdata <= #FFD {32{1'b0}};`
89			`pslverr <= #FFD 1'b0;`
90			`end`
91
92			`endmodule`
93
94

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[/] [robust_axi2apb/] [trunk/] [src/] [base/] [axi2apb_mux.v] - Blame information for rev 2