OpenCores
URL https://opencores.org/ocsvn/robust_axi_fabric/robust_axi_fabric/trunk

Subversion Repositories robust_axi_fabric

[/] [robust_axi_fabric/] [trunk/] [README.txt] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 eyalhoc
 
2
------------------------------ Remark ----------------------------------------
3
This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.
4
It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.
5
------------------------------------------------------------------------------
6
 
7
RobustVerilog generic AXI interconnect fabric
8
 
9
In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
10
 
11
The RobustVerilog top source file is ic.v, it calls the top definition file named def_ic.txt.
12
 
13
The default definition file def_ic.txt generates 2 fabrics, the first with 3 masters and 8 slaves,
14
 
15
the second with 1 master, 3 slaves and an internal decode error slave.
16
 
17
Changing the interconnect parameters should be made only in def_ic.txt in the src/base directory (changing master num, slave num etc.).
18
 
19
For any questions / remarks / suggestions / bugs please contact info@provartec.com.
20
 
21
 
22
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.