In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
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The RobustVerilog top source file is ic.v, it calls the top definition file named def_ic.txt.
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The default definition file def_ic.txt generates 2 fabrics, the first with 3 masters and 8 slaves,
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the second with 1 master, 3 slaves and an internal decode error slave.
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Changing the interconnect parameters should be made only in def_ic.txt in the src/base directory (changing master num, slave num etc.).
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For any questions / remarks / suggestions / bugs please contact info@provartec.com.