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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [def_ic_static.txt] - Blame information for rev 18

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<##//////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
//////////////////////////////////////////////////////////////////##>
 
SWAP.GLOBAL MODEL_NAME AXI interconnect fabric
 
SWAP MSTRS MASTER_NUM
SWAP SLVS EXPR(SLAVE_NUM+DVAL(DEF_DECERR_SLV))
 
LOOP MX MSTRS
LOOP SX SLVS
 
SWAP MSTR_BITS LOG2(MSTRS)
SWAP SLV_BITS  LOG2(SLVS)
 
SWAP SERR EXPR(SLVS-1)
 
GROUP IC_AXI_A is {
    ID       ID_BITS                input
    ADDR     ADDR_BITS              input
    LEN      4                      input
    SIZE     2                      input
    BURST    2                      input
    CACHE    4                      input
    PROT     3                      input
    LOCK     2                      input
    USER     USER_BITS              input
    VALID    1                      input
    READY    1                      output
}
 
GROUP IC_AXI_W is {
    ID        ID_BITS                input
    DATA      DATA_BITS              input
    STRB      DATA_BITS/8            input
    LAST      1                      input
    USER      USER_BITS              input
    VALID     1                      input
    READY     1                      output
}
 
GROUP IC_AXI_B is {
    ID        ID_BITS                output
    RESP      2                      output
    USER      USER_BITS              output
    VALID     1                      output
    READY     1                      input
}
 
GROUP IC_AXI_R is {
    ID        ID_BITS                output
    DATA      DATA_BITS              output
    RESP      2                      output
    LAST      1                      output
    USER      USER_BITS              output
    VALID     1                      output
    READY     1                      input
}
 
GROUP IC_AXI joins {
    GROUP IC_AXI_A prefix_AW
    GROUP IC_AXI_W prefix_W
    GROUP IC_AXI_B prefix_B
    GROUP IC_AXI_A prefix_AR
    GROUP IC_AXI_R prefix_R
}
 
GROUP IC_AXI_CMD is {
    SLV       SLV_BITS               input
    ID        ID_BITS                input
    VALID     1                      input
    READY     1                      input
}

Line No.	Rev	Author	Line
1	7	eyalhoc	`<##//////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Author: Eyal Hochberg ////`
4			`//// eyal@provartec.com ////`
5			`//// ////`
6			`//// Downloaded from: http://www.opencores.org ////`
7			`/////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// Copyright (C) 2010 Provartec LTD ////`
10			`//// www.provartec.com ////`
11			`//// info@provartec.com ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer.////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation.////`
21			`//// ////`
22			`//// This source is distributed in the hope that it will be ////`
23			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
24			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
25			`//// PURPOSE. See the GNU Lesser General Public License for more////`
26			`//// details. http://www.gnu.org/licenses/lgpl.html ////`
27			`//// ////`
28			`//////////////////////////////////////////////////////////////////##>`
29	18	eyalhoc
30	17	eyalhoc	`SWAP.GLOBAL MODEL_NAME AXI interconnect fabric`
31	15	eyalhoc
32	2	eyalhoc	`SWAP MSTRS MASTER_NUM`
33	9	eyalhoc	`SWAP SLVS EXPR(SLAVE_NUM+DVAL(DEF_DECERR_SLV))`
34	2	eyalhoc
35			`LOOP MX MSTRS`
36			`LOOP SX SLVS`
37
38			`SWAP MSTR_BITS LOG2(MSTRS)`
39			`SWAP SLV_BITS LOG2(SLVS)`
40
41	9	eyalhoc	`SWAP SERR EXPR(SLVS-1)`
42	2	eyalhoc
43			`GROUP IC_AXI_A is {`
44			`ID ID_BITS input`
45			`ADDR ADDR_BITS input`
46			`LEN 4 input`
47			`SIZE 2 input`
48			`BURST 2 input`
49			`CACHE 4 input`
50			`PROT 3 input`
51			`LOCK 2 input`
52			`USER USER_BITS input`
53			`VALID 1 input`
54			`READY 1 output`
55			`}`
56
57			`GROUP IC_AXI_W is {`
58			`ID ID_BITS input`
59			`DATA DATA_BITS input`
60			`STRB DATA_BITS/8 input`
61			`LAST 1 input`
62			`USER USER_BITS input`
63			`VALID 1 input`
64			`READY 1 output`
65			`}`
66
67			`GROUP IC_AXI_B is {`
68			`ID ID_BITS output`
69			`RESP 2 output`
70			`USER USER_BITS output`
71			`VALID 1 output`
72			`READY 1 input`
73			`}`
74
75			`GROUP IC_AXI_R is {`
76			`ID ID_BITS output`
77			`DATA DATA_BITS output`
78			`RESP 2 output`
79			`LAST 1 output`
80			`USER USER_BITS output`
81			`VALID 1 output`
82			`READY 1 input`
83			`}`
84
85			`GROUP IC_AXI joins {`
86			`GROUP IC_AXI_A prefix_AW`
87			`GROUP IC_AXI_W prefix_W`
88			`GROUP IC_AXI_B prefix_B`
89			`GROUP IC_AXI_A prefix_AR`
90			`GROUP IC_AXI_R prefix_R`
91			`}`
92
93			`GROUP IC_AXI_CMD is {`
94			`SLV SLV_BITS input`
95			`ID ID_BITS input`
96			`VALID 1 input`
97			`READY 1 input`
98			`}`

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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [def_ic_static.txt] - Blame information for rev 18