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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [ic_addr.v] - Blame information for rev 23

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1 23 eyalhoc
<##//////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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//////////////////////////////////////////////////////////////////##>
29 7 eyalhoc
 
30 2 eyalhoc
OUTFILE PREFIX_ic_addr.v
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ITER MX
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ITER SX
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module PREFIX_ic_addr (PORTS);
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   input                                      clk;
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   input                                      reset;
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   output [EXPR(SLV_BITS-1):0]                 MMX_ASLV;
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   port                                       MMX_AGROUP_IC_AXI_A;
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   output [EXPR(MSTR_BITS-1):0]        SSX_AMSTR;
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   output                                     SSX_AIDOK;
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   revport                                    SSX_AGROUP_IC_AXI_A;
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   parameter                                  MASTER_NONE = 0;
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   parameter                                  MASTERMX    = 1 << MX;
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   parameter                                  ABUS_WIDTH = GONCAT(GROUP_IC_AXI_A.IN.WIDTH +);
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   wire [ABUS_WIDTH-1:0]                       SSX_ABUS;
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   wire [ABUS_WIDTH-1:0]                       MMX_ABUS;
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   wire                                       SSX_MMX;
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   wire [EXPR(SLV_BITS-1):0]                   MMX_ASLV;
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   wire                                       MMX_AIDOK;
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   wire [EXPR(MSTRS-1):0]                      SSX_master;
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   reg [EXPR(MSTR_BITS-1):0]                   SSX_AMSTR;
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   wire                                       SSX_AIDOK;
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   wire [EXPR(ADDR_BITS-1):0]                 MMX_AADDR_valid;
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   wire [EXPR(ID_BITS-1):0]                   MMX_AID_valid;
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   assign                                     MMX_AADDR_valid = MMX_AADDR & {ADDR_BITS{MMX_AVALID}};
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   assign                                     MMX_AID_valid   = MMX_AID & {ID_BITS{MMX_AVALID}};
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   CREATE ic_dec.v def_ic.txt
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   PREFIX_ic_dec
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   PREFIX_ic_dec (
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                  .MMX_AADDR(MMX_AADDR_valid),
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                  .MMX_AID(MMX_AID_valid),
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                  .MMX_ASLV(MMX_ASLV),
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                  .MMX_AIDOK(MMX_AIDOK),
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                  STOMP ,
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                  );
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   CREATE ic_arbiter.v def_ic.txt DEFCMD(SWAP MSTR_SLV mstr) DEFCMD(SWAP MSTRNUM MSTRS) DEFCMD(SWAP SLVNUM SLVS) DEFCMD(DEFINE DEF_PRIO)
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   PREFIX_ic_mstr_arbiter
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   PREFIX_ic_mstr_arbiter(
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                          .clk(clk),
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                          .reset(reset),
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                          .MMX_slave(MMX_ASLV),
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                          .SSX_master(SSX_master),
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                          .M_last({MSTRS{1'b1}}),
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                          .M_req({CONCAT(MMX_AVALID ,)}),
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                          .M_grant({CONCAT(MMX_AREADY ,)})
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                          );
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   LOOP SX
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     always @(/*AUTOSENSE*/SSX_master)
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       begin
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          case (SSX_master)
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            MASTERMX : SSX_AMSTR = MX;
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            default : SSX_AMSTR = MASTER_NONE;
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          endcase
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       end
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   ENDLOOP SX
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     assign                  SSX_MMX    = SSX_master[MX];
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   assign                    MMX_ABUS   = {GONCAT(MMX_AGROUP_IC_AXI_A.IN ,)};
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   assign                    {GONCAT(SSX_AGROUP_IC_AXI_A.IN ,)} = SSX_ABUS;
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   LOOP SX
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   assign                    SSX_ABUS  = CONCAT((MMX_ABUS & {ABUS_WIDTH{SSX_MMX}}) |);
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   assign                    SSX_AIDOK = CONCAT((SSX_MMX & MMX_AIDOK) |);
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   ENDLOOP SX
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   LOOP MX
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       assign            MMX_AREADY =
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                                          SSX_MMX ? SSX_AREADY :
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                                          ~MMX_AVALID;
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   ENDLOOP MX
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     endmodule
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