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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [ic_dec.v] - Blame information for rev 23

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1 23 eyalhoc
<##//////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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//////////////////////////////////////////////////////////////////##>
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OUTFILE PREFIX_ic_dec.v
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ITER MX
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ITER SX
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module PREFIX_ic_dec (PORTS);
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   input [ADDR_BITS-1:0]                       MMX_AADDR;
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   input [ID_BITS-1:0]                         MMX_AID;
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   output [SLV_BITS-1:0]                       MMX_ASLV;
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   output                                     MMX_AIDOK;
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   parameter                                  DEC_MSB =  ADDR_BITS - 1;
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   parameter                                  DEC_LSB =  ADDR_BITS - SLV_BITS;
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   reg [SLV_BITS-1:0]                          MMX_ASLV;
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   reg                                        MMX_AIDOK;
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   wire [DEC_MSB:DEC_LSB]                     MMX_AADDR_DEC;
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   assign                                     MMX_AADDR_DEC = MMX_AADDR[DEC_MSB:DEC_LSB];
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LOOP MX
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     always @(MMX_AADDR or MMX_AIDOK)
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       begin
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IFDEF TRUE(SLAVE_NUM==1)
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          case (MMX_AIDOK)
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            1'b1 : MMX_ASLV = SLV_BITS'd0;
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ELSE TRUE(SLAVE_NUM==1)
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          case ({MMX_AIDOK, MMX_AADDR_DEC})
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            {1'b1, BIN(SX SLV_BITS)} : MMX_ASLV = SLV_BITS'dSX;
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ENDIF TRUE(SLAVE_NUM==1)
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            default : MMX_ASLV = SLV_BITS'dSERR;
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          endcase
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       end
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   always @(MMX_AID)
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     begin
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        case (MMX_AID[MSTR_ID_BITS-1:0])
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          MSTR_ID_BITS'bGROUP_MMX_ID : MMX_AIDOK = 1'b1;
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          default : MMX_AIDOK = 1'b0;
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        endcase
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     end
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ENDLOOP MX
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endmodule
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