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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [ic_registry_resp.v] - Blame information for rev 2

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OUTFILE PREFIX_ic_registry_resp.v
 
ITER MX
ITER SX
 
LOOP MX
ITER MMX_IDX
ENDLOOP MX
 
module PREFIX_ic_registry_resp(PORTS);
 
   input                            clk;
   input                            reset;
 
   port                             MMX_AGROUP_IC_AXI_CMD;
 
   input [ID_BITS-1:0]   SSX_ID;
   input                            SSX_VALID;
   input                            SSX_READY;
   input                            SSX_LAST;
   output [MSTR_BITS-1:0] SSX_MSTR;
   output                           SSX_OK;
 
 
 
   wire                             Amatch_MMX_IDMMX_IDX;
   wire                             match_MMX_IDMMX_IDX;
   wire                             no_Amatch_MMX;
 
   wire                             cmd_push_MMX;
   wire                             cmd_push_MMX_IDMMX_IDX;
 
   wire                             cmd_pop_SSX;
LOOP MX
   wire                             cmd_pop_MMX_IDMMX_IDX;
ENDLOOP MX
 
   wire [SLV_BITS-1:0]   slave_in_MMX_IDMMX_IDX;
   wire [SLV_BITS-1:0]   slave_out_MMX_IDMMX_IDX;
   wire                             slave_empty_MMX_IDMMX_IDX;
   wire                             slave_full_MMX_IDMMX_IDX;
 
   reg [MSTR_BITS-1:0]   ERR_MSTR_reg;
   wire [MSTR_BITS-1:0] ERR_MSTR;
 
   reg [MSTR_BITS-1:0]   SSX_MSTR;
   reg                              SSX_OK;
 
 
 
 
   assign                           Amatch_MMX_IDMMX_IDX = MMX_AID == ID_MMX_IDMMX_IDX;
 
   assign                           match_MMX_IDMMX_IDX  = SSX_ID == ID_MMX_IDMMX_IDX;
 
 
   assign                           cmd_push_MMX           = MMX_AVALID & MMX_AREADY;
   assign                           cmd_push_MMX_IDMMX_IDX = cmd_push_MMX & Amatch_MMX_IDMMX_IDX;
   assign                           cmd_pop_SSX            = SSX_VALID & SSX_READY & SSX_LAST;
 
   LOOP MX
     assign                         cmd_pop_MMX_IDMMX_IDX = CONCAT((cmd_pop_SSX & (SSX_ID == ID_MMX_IDMMX_IDX)) |);
   ENDLOOP MX
 
 
   assign                           slave_in_MMX_IDMMX_IDX = MMX_ASLV;
 
 
 
 
IFDEF DEF_DECERR_SLV
   LOOP MX
     assign                         no_Amatch_MMX         = CONCAT((~Amatch_MMX_IDMMX_IDX) &);
   ENDLOOP MX
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       ERR_MSTR_reg <= #FFD {MSTR_BITS{1'b0}};
   LOOP MX
     else if (cmd_push_MMX & no_Amatch_MMX)
       ERR_MSTR_reg <= #FFD 'dMX;
   ENDLOOP MX
 
   assign                           ERR_MSTR = ERR_MSTR_reg;
ELSE DEF_DECERR_SLV
   assign                           ERR_MSTR = 'd0;
ENDIF DEF_DECERR_SLV
 
 
LOOP SX
   always @(SSX_ID or ERR_MSTR)
     begin
        case (SSX_ID)
          LOOP MX
          ID_MMX_IDMMX_IDX : SSX_MSTR = 'dMX;
          ENDLOOP MX
          default : SSX_MSTR = ERR_MSTR;
        endcase
     end
 
   always @(*)
     begin
        case (SSX_ID)
          LOOP MX
          ID_MMX_IDMMX_IDX : SSX_OK = slave_out_MMX_IDMMX_IDX == 'dSX;
          ENDLOOP MX
          default : SSX_OK = 1'b1; //SLVERR                                   
        endcase
     end
ENDLOOP SX
 
CREATE prgen_fifo.v DEFCMD(SWAP CONST(#FFD) #FFD)
LOOP MX
LOOP MMX_IDX
   prgen_fifo #(SLV_BITS, CMD_DEPTH)
   slave_fifo_MMX_IDMMX_IDX(
                    .clk(clk),
                    .reset(reset),
                    .push(cmd_push_MMX_IDMMX_IDX),
                    .pop(cmd_pop_MMX_IDMMX_IDX),
                    .din(slave_in_MMX_IDMMX_IDX),
                    .dout(slave_out_MMX_IDMMX_IDX),
                            .empty(slave_empty_MMX_IDMMX_IDX),
                            .full(slave_full_MMX_IDMMX_IDX)
                    );
 
ENDLOOP MMX_IDX
ENDLOOP MX
 
 
endmodule
 
 

Line No.	Rev	Author	Line
1	2	eyalhoc	`OUTFILE PREFIX_ic_registry_resp.v`
2
3			`ITER MX`
4			`ITER SX`
5
6			`LOOP MX`
7			`ITER MMX_IDX`
8			`ENDLOOP MX`
9
10			`module PREFIX_ic_registry_resp(PORTS);`
11
12			`input clk;`
13			`input reset;`
14
15			`port MMX_AGROUP_IC_AXI_CMD;`
16
17			`input [ID_BITS-1:0] SSX_ID;`
18			`input SSX_VALID;`
19			`input SSX_READY;`
20			`input SSX_LAST;`
21			`output [MSTR_BITS-1:0] SSX_MSTR;`
22			`output SSX_OK;`
23
24
25
26			`wire Amatch_MMX_IDMMX_IDX;`
27			`wire match_MMX_IDMMX_IDX;`
28			`wire no_Amatch_MMX;`
29
30			`wire cmd_push_MMX;`
31			`wire cmd_push_MMX_IDMMX_IDX;`
32
33			`wire cmd_pop_SSX;`
34			`LOOP MX`
35			`wire cmd_pop_MMX_IDMMX_IDX;`
36			`ENDLOOP MX`
37
38			`wire [SLV_BITS-1:0] slave_in_MMX_IDMMX_IDX;`
39			`wire [SLV_BITS-1:0] slave_out_MMX_IDMMX_IDX;`
40			`wire slave_empty_MMX_IDMMX_IDX;`
41			`wire slave_full_MMX_IDMMX_IDX;`
42
43			`reg [MSTR_BITS-1:0] ERR_MSTR_reg;`
44			`wire [MSTR_BITS-1:0] ERR_MSTR;`
45
46			`reg [MSTR_BITS-1:0] SSX_MSTR;`
47			`reg SSX_OK;`
48
49
50
51
52			`assign Amatch_MMX_IDMMX_IDX = MMX_AID == ID_MMX_IDMMX_IDX;`
53
54			`assign match_MMX_IDMMX_IDX = SSX_ID == ID_MMX_IDMMX_IDX;`
55
56
57			`assign cmd_push_MMX = MMX_AVALID & MMX_AREADY;`
58			`assign cmd_push_MMX_IDMMX_IDX = cmd_push_MMX & Amatch_MMX_IDMMX_IDX;`
59			`assign cmd_pop_SSX = SSX_VALID & SSX_READY & SSX_LAST;`
60
61			`LOOP MX`
62			`assign cmd_pop_MMX_IDMMX_IDX = CONCAT((cmd_pop_SSX & (SSX_ID == ID_MMX_IDMMX_IDX)) \|);`
63			`ENDLOOP MX`
64
65
66			`assign slave_in_MMX_IDMMX_IDX = MMX_ASLV;`
67
68
69
70
71			`IFDEF DEF_DECERR_SLV`
72			`LOOP MX`
73			`assign no_Amatch_MMX = CONCAT((~Amatch_MMX_IDMMX_IDX) &);`
74			`ENDLOOP MX`
75
76
77			`always @(posedge clk or posedge reset)`
78			`if (reset)`
79			`ERR_MSTR_reg <= #FFD {MSTR_BITS{1'b0}};`
80			`LOOP MX`
81			`else if (cmd_push_MMX & no_Amatch_MMX)`
82			`ERR_MSTR_reg <= #FFD 'dMX;`
83			`ENDLOOP MX`
84
85			`assign ERR_MSTR = ERR_MSTR_reg;`
86			`ELSE DEF_DECERR_SLV`
87			`assign ERR_MSTR = 'd0;`
88			`ENDIF DEF_DECERR_SLV`
89
90
91			`LOOP SX`
92			`always @(SSX_ID or ERR_MSTR)`
93			`begin`
94			`case (SSX_ID)`
95			`LOOP MX`
96			`ID_MMX_IDMMX_IDX : SSX_MSTR = 'dMX;`
97			`ENDLOOP MX`
98			`default : SSX_MSTR = ERR_MSTR;`
99			`endcase`
100			`end`
101
102			`always @(*)`
103			`begin`
104			`case (SSX_ID)`
105			`LOOP MX`
106			`ID_MMX_IDMMX_IDX : SSX_OK = slave_out_MMX_IDMMX_IDX == 'dSX;`
107			`ENDLOOP MX`
108			`default : SSX_OK = 1'b1; //SLVERR`
109			`endcase`
110			`end`
111			`ENDLOOP SX`
112
113			`CREATE prgen_fifo.v DEFCMD(SWAP CONST(#FFD) #FFD)`
114			`LOOP MX`
115			`LOOP MMX_IDX`
116			`prgen_fifo #(SLV_BITS, CMD_DEPTH)`
117			`slave_fifo_MMX_IDMMX_IDX(`
118			`.clk(clk),`
119			`.reset(reset),`
120			`.push(cmd_push_MMX_IDMMX_IDX),`
121			`.pop(cmd_pop_MMX_IDMMX_IDX),`
122			`.din(slave_in_MMX_IDMMX_IDX),`
123			`.dout(slave_out_MMX_IDMMX_IDX),`
124			`.empty(slave_empty_MMX_IDMMX_IDX),`
125			`.full(slave_full_MMX_IDMMX_IDX)`
126			`);`
127
128			`ENDLOOP MMX_IDX`
129			`ENDLOOP MX`
130
131
132			`endmodule`
133
134

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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [ic_registry_resp.v] - Blame information for rev 2