OpenCores
URL https://opencores.org/ocsvn/robust_axi_fabric/robust_axi_fabric/trunk

Subversion Repositories robust_axi_fabric

[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [ic_registry_resp.v] - Blame information for rev 23

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 23 eyalhoc
<##//////////////////////////////////////////////////////////////////
2
////                                                             ////
3
////  Author: Eyal Hochberg                                      ////
4
////          eyal@provartec.com                                 ////
5
////                                                             ////
6
////  Downloaded from: http://www.opencores.org                  ////
7
/////////////////////////////////////////////////////////////////////
8
////                                                             ////
9
//// Copyright (C) 2010 Provartec LTD                            ////
10
//// www.provartec.com                                           ////
11
//// info@provartec.com                                          ////
12
////                                                             ////
13
//// This source file may be used and distributed without        ////
14
//// restriction provided that this copyright statement is not   ////
15
//// removed from the file and that any derivative work contains ////
16
//// the original copyright notice and the associated disclaimer.////
17
////                                                             ////
18
//// This source file is free software; you can redistribute it  ////
19
//// and/or modify it under the terms of the GNU Lesser General  ////
20
//// Public License as published by the Free Software Foundation.////
21
////                                                             ////
22
//// This source is distributed in the hope that it will be      ////
23
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
24
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
25
//// PURPOSE.  See the GNU Lesser General Public License for more////
26
//// details. http://www.gnu.org/licenses/lgpl.html              ////
27
////                                                             ////
28
//////////////////////////////////////////////////////////////////##>
29 7 eyalhoc
 
30 2 eyalhoc
OUTFILE PREFIX_ic_registry_resp.v
31
 
32
ITER MX
33
ITER SX
34
 
35
module PREFIX_ic_registry_resp(PORTS);
36
 
37
   input                            clk;
38
   input                            reset;
39
 
40
   port                             MMX_AGROUP_IC_AXI_CMD;
41
 
42 11 eyalhoc
   input [ID_BITS-1:0]              SSX_ID;
43 2 eyalhoc
   input                            SSX_VALID;
44
   input                            SSX_READY;
45
   input                            SSX_LAST;
46 11 eyalhoc
   output [MSTR_BITS-1:0]           SSX_MSTR;
47 2 eyalhoc
   output                           SSX_OK;
48
 
49 16 eyalhoc
 
50
   wire                             Amatch_MMX_IDGROUP_MMX_ID.IDX;
51 2 eyalhoc
 
52 16 eyalhoc
   wire                             match_SSX_MMX_IDGROUP_MMX_ID.IDX;
53 2 eyalhoc
   wire                             no_Amatch_MMX;
54
 
55
   wire                             cmd_push_MMX;
56 16 eyalhoc
   wire                             cmd_push_MMX_IDGROUP_MMX_ID.IDX;
57 2 eyalhoc
 
58
   wire                             cmd_pop_SSX;
59 16 eyalhoc
   wire                             cmd_pop_MMX_IDGROUP_MMX_ID.IDX;
60 2 eyalhoc
 
61 16 eyalhoc
   wire [SLV_BITS-1:0]              slave_in_MMX_IDGROUP_MMX_ID.IDX;
62
   wire [SLV_BITS-1:0]              slave_out_MMX_IDGROUP_MMX_ID.IDX;
63
   wire                             slave_empty_MMX_IDGROUP_MMX_ID.IDX;
64
   wire                             slave_full_MMX_IDGROUP_MMX_ID.IDX;
65 2 eyalhoc
 
66 16 eyalhoc
   reg [MSTR_BITS-1:0]              ERR_MSTR_reg;
67
   wire [MSTR_BITS-1:0]             ERR_MSTR;
68 2 eyalhoc
 
69 16 eyalhoc
   reg [MSTR_BITS-1:0]              SSX_MSTR;
70
   reg                              SSX_OK;
71 2 eyalhoc
 
72
 
73
 
74
 
75 19 eyalhoc
   assign                           Amatch_MMX_IDGROUP_MMX_ID.IDX = MMX_AID == ID_BITS'bADD_IDGROUP_MMX_ID;
76 2 eyalhoc
 
77 19 eyalhoc
   assign                           match_SSX_MMX_IDGROUP_MMX_ID.IDX = SSX_ID == ID_BITS'bADD_IDGROUP_MMX_ID;
78 2 eyalhoc
 
79
 
80
   assign                           cmd_push_MMX           = MMX_AVALID & MMX_AREADY;
81 16 eyalhoc
   assign                           cmd_push_MMX_IDGROUP_MMX_ID.IDX = cmd_push_MMX & Amatch_MMX_IDGROUP_MMX_ID.IDX;
82 2 eyalhoc
   assign                           cmd_pop_SSX            = SSX_VALID & SSX_READY & SSX_LAST;
83
 
84 16 eyalhoc
LOOP MX
85
  assign                            cmd_pop_MMX_IDGROUP_MMX_ID.IDX = CONCAT((cmd_pop_SSX & match_SSX_MMX_IDGROUP_MMX_ID.IDX) |);
86
ENDLOOP MX
87
 
88
  assign                           slave_in_MMX_IDGROUP_MMX_ID.IDX = MMX_ASLV;
89 2 eyalhoc
 
90
 
91
IFDEF DEF_DECERR_SLV
92 16 eyalhoc
     assign                         no_Amatch_MMX         = GONCAT.REV((~Amatch_MMX_IDGROUP_MMX_ID.IDX) &);
93 2 eyalhoc
 
94
 
95
   always @(posedge clk or posedge reset)
96
     if (reset)
97
       ERR_MSTR_reg <= #FFD {MSTR_BITS{1'b0}};
98 16 eyalhoc
     else if (cmd_push_MMX & no_Amatch_MMX) ERR_MSTR_reg <= #FFD MSTR_BITS'dMX;
99 2 eyalhoc
 
100
   assign                           ERR_MSTR = ERR_MSTR_reg;
101
ELSE DEF_DECERR_SLV
102
   assign                           ERR_MSTR = 'd0;
103
ENDIF DEF_DECERR_SLV
104 19 eyalhoc
 
105 2 eyalhoc
 
106
LOOP SX
107 16 eyalhoc
   always @(*)
108 2 eyalhoc
     begin
109 19 eyalhoc
        case (SSX_ID)
110
          ID_BITS'bADD_IDGROUP_MMX_ID : SSX_MSTR = MSTR_BITS'dMX;
111 2 eyalhoc
          default : SSX_MSTR = ERR_MSTR;
112
        endcase
113
     end
114
 
115
   always @(*)
116
     begin
117 19 eyalhoc
        case (SSX_ID)
118
          ID_BITS'bADD_IDGROUP_MMX_ID : SSX_OK = slave_out_MMX_IDGROUP_MMX_ID.IDX == SLV_BITS'dSX;
119 2 eyalhoc
          default : SSX_OK = 1'b1; //SLVERR                                   
120
        endcase
121
     end
122
ENDLOOP SX
123
 
124
CREATE prgen_fifo.v DEFCMD(SWAP CONST(#FFD) #FFD)
125
LOOP MX
126 16 eyalhoc
 LOOP IX GROUP_MMX_ID.NUM
127 2 eyalhoc
   prgen_fifo #(SLV_BITS, CMD_DEPTH)
128 16 eyalhoc
   slave_fifo_MMX_IDIX(
129
                       .clk(clk),
130
                       .reset(reset),
131
                       .push(cmd_push_MMX_IDIX),
132
                       .pop(cmd_pop_MMX_IDIX),
133
                       .din(slave_in_MMX_IDIX),
134
                       .dout(slave_out_MMX_IDIX),
135
                       .empty(slave_empty_MMX_IDIX),
136
                       .full(slave_full_MMX_IDIX)
137
                       );
138 2 eyalhoc
 
139 16 eyalhoc
   ENDLOOP IX
140 2 eyalhoc
ENDLOOP MX
141
 
142
 
143
endmodule
144
 
145
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.