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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [ic_resp.v] - Blame information for rev 23

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1 23 eyalhoc
<##//////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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//////////////////////////////////////////////////////////////////##>
29 7 eyalhoc
 
30 2 eyalhoc
OUTFILE PREFIX_ic_resp.v
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ITER MX
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ITER SX
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module PREFIX_ic_resp (PORTS);
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   parameter                              STRB_BITS  = DATA_BITS/8;
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   input                                      clk;
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   input                                      reset;
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   port                                       MMX_AGROUP_IC_AXI_CMD;
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   port                                       MMX_GROUP_IC_AXI_R;
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   revport                                    SSX_GROUP_IC_AXI_R;
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   parameter                              RBUS_WIDTH = GONCAT(GROUP_IC_AXI_R.OUT.WIDTH +);
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   wire                                       SSX_req;
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   wire [RBUS_WIDTH-1:0]           SSX_RBUS;
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   wire [RBUS_WIDTH-1:0]           MMX_RBUS;
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   wire                                       SSX_MMX;
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   wire [MSTR_BITS-1:0]    SSX_MSTR;
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   wire                                       SSX_OK;
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   wire [SLVS-1:0]                         MMX_slave;
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   CREATE ic_registry_resp.v def_ic.txt
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   PREFIX_ic_registry_resp
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     PREFIX_ic_registry_resp (
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                              .clk(clk),
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                              .reset(reset),
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                              .MMX_ASLV(MMX_ASLV),
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                              .MMX_AID(MMX_AID),
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                              .MMX_AVALID(MMX_AVALID),
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                              .MMX_AREADY(MMX_AREADY),
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                              .SSX_ID(SSX_ID),
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                              .SSX_VALID(SSX_VALID),
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                              .SSX_READY(SSX_READY),
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                              .SSX_LAST(SSX_LAST),
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                              .SSX_MSTR(SSX_MSTR),
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                              .SSX_OK(SSX_OK),
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                              STOMP ,
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                              );
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   CREATE ic_arbiter.v def_ic.txt DEFCMD(SWAP MSTR_SLV slv) DEFCMD(SWAP MSTRNUM SLVS) DEFCMD(SWAP SLVNUM MSTRS) DEFCMD(DEFINE DEF_PRIO)
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   PREFIX_ic_slv_arbiter
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   PREFIX_ic_slv_arbiter(
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                         .clk(clk),
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                         .reset(reset),
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                         .MSX_slave(SSX_MSTR),
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                         .SMX_master(MMX_slave),
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                         .M_last({CONCAT(SSX_LAST ,)}),
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                         .M_req({CONCAT(SSX_req ,)}),
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                         .M_grant({CONCAT(SSX_READY ,)})
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                         );
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   assign                                        SSX_req = SSX_VALID & SSX_OK;
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   assign                                        SSX_MMX = MMX_slave[SX];
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   assign                                        SSX_RBUS   = {GONCAT(SSX_GROUP_IC_AXI_R.OUT ,)};
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   assign                                        {GONCAT(MMX_GROUP_IC_AXI_R.OUT ,)} = MMX_RBUS;
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   LOOP MX
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     assign                                      MMX_RBUS = CONCAT((SSX_RBUS & {RBUS_WIDTH{SSX_MMX}}) |);
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   ENDLOOP MX
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   LOOP SX
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       assign                                    SSX_READY = CONCAT((SSX_MMX & MMX_READY) |);
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   ENDLOOP SX
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endmodule
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