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[/] [rs232_interface/] [trunk/] [uart.vhd] - Blame information for rev 5

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----------------------------------------------------------------------------------
-- Create Date: 21:12:48 05/06/2010 
-- Module Name: UART - Behavioral
-- Used TAB of 4 Spaces
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity uart is
generic (
        CLK_FREQ        : integer := 50;                -- Main frequency (MHz)
        SER_FREQ        : integer := 9600               -- Baud rate (bps)
);
port (
        -- Control
        clk                     : in    std_logic;              -- Main clock
        rst                     : in    std_logic;              -- Main reset
        -- External Interface
        rx                      : in    std_logic;              -- RS232 received serial data
        tx                      : out   std_logic;              -- RS232 transmitted serial data
        -- uPC Interface
        tx_req          : in    std_logic;                                              -- Request SEND of data
        tx_end          : out   std_logic;                                              -- Data SENDED
        tx_data         : in    std_logic_vector(7 downto 0);    -- Data to transmit
        rx_ready        : out   std_logic;                                              -- Received data ready to uPC read
        rx_data         : out   std_logic_vector(7 downto 0)     -- Received data 
);
end uart;
 
architecture Behavioral of uart is
 
        -- Constants
        constant uart_idle      :       std_logic := '1';
        constant uart_start     :       std_logic := '0';
 
        -- Types
        type state is (idle,data,stop1,stop2);
 
        -- Signals
        signal rx_fsm                   :       state;
        signal tx_fsm                   :       state;
        signal clock_en         :       std_logic;
 
        -- Data Temp
        signal data_cnt_tx      :       std_logic_vector(2 downto 0) := "000";
        signal data_cnt_rx      :       std_logic_vector(2 downto 0) := "000";
        signal rx_data_tmp      :       std_logic_vector(7 downto 0);
        signal tx_data_tmp      :       std_logic_vector(7 downto 0);
 
begin
 
        clock_manager:process(clk)
                variable counter        :       integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);
        begin
                if clk'event and clk = '1' then
                        -- Normal Operation
                        if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 then
                                clock_en                <= '1';
                                counter         := 0;
                        else
                                clock_en                <= '0';
                                counter         := counter + 1;
                        end if;
                        -- Reset condition
                        if rst = '1' then
                                counter         :=      0;
                        end if;
                end if;
        end process;
 
        tx_proc:process(clk)
                variable data_cnt       : std_logic_vector(2 downto 0);
        begin
                if clk'event and clk = '1' then
                        if clock_en = '1' then
                                -- Default values
                                tx_end                                  <= '0';
                                tx                                                      <= uart_idle;
                                -- FSM description
                                case tx_fsm is
                                        -- Wait to transfer data
                                        when idle =>
                                                -- Send Init Bit
                                                if tx_req = '1' then
                                                        tx                              <= uart_start;
                                                        tx_data_tmp     <=      tx_data;
                                                        tx_fsm          <= data;
                                                        data_cnt_tx     <=      (others=>'1');
                                                end if;
                                        -- Data receive
                                        when data =>
                                                tx                                      <= tx_data_tmp(0);
                                                if data_cnt_tx = 0 then
                                                        tx_fsm          <=      stop1;
                                                        data_cnt_tx     <=      (others=>'1');
                                                else
                                                        tx_data_tmp     <=      '0' & tx_data_tmp(7 downto 1);
                                                        data_cnt_tx     <=      data_cnt_tx - 1;
                                                end if;
                                        -- End of communication
                                        when stop1 =>
                                                -- Send Stop Bit
                                                tx                                      <= uart_idle;
                                                tx_fsm                  <=      stop2;
                                        when stop2 =>
                                                -- Send Stop Bit
                                                tx_end                  <= '1';
                                                tx                                      <= uart_idle;
                                                tx_fsm                  <=      idle;
                                        -- Invalid States
                                        when others => null;
                                end case;
                                -- Reset condition
                                if rst = '1' then
                                        tx_fsm                          <=      idle;
                                        tx_data_tmp                     <= (others=>'0');
                                end if;
                        end if;
                end if;
        end process;
 
        rx_proc:process(clk)
        begin
                if clk'event and clk = '1' then
                        if clock_en = '1' then
                                -- Default values
                                rx_ready                        <= '0';
                                -- FSM description
                                case rx_fsm is
                                        -- Wait to transfer data
                                        when idle =>
                                                if rx = uart_start then
                                                        rx_fsm          <=      data;
                                                end if;
                                                data_cnt_rx             <=      (others=>'0');
                                        -- Data receive
                                        when data =>
                                                if data_cnt_rx = 7 then
                                                        rx_fsm          <=      idle;
                                                        rx_ready                <= '1';
                                                        rx_data(7)      <=      rx;
                                                        for i in 0 to 6 loop
                                                                rx_data(i)      <= rx_data_tmp(6-i);
                                                        end loop;
                                                else
                                                        rx_data_tmp     <=      rx_data_tmp(6 downto 0) & rx;
                                                        data_cnt_rx     <=      data_cnt_rx + 1;
                                                end if;
                                        when others => null;
                                end case;
                                -- Reset condition
                                if rst = '1' then
                                        rx_fsm                  <=      idle;
                                        rx_ready                        <= '0';
                                        rx_data                 <= (others=>'0');
                                        data_cnt_rx             <= (others=>'0');
                                end if;
                        end if;
                end if;
        end process;
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	3	akram.mash	`----------------------------------------------------------------------------------`
2			`-- Create Date: 21:12:48 05/06/2010`
3			`-- Module Name: UART - Behavioral`
4			`-- Used TAB of 4 Spaces`
5			`----------------------------------------------------------------------------------`
6			`library IEEE;`
7			`use IEEE.STD_LOGIC_1164.ALL;`
8			`use IEEE.STD_LOGIC_ARITH.ALL;`
9			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
10
11			`entity uart is`
12			`generic (`
13			`CLK_FREQ : integer := 50; -- Main frequency (MHz)`
14	5	akram.mash	`SER_FREQ : integer := 9600 -- Baud rate (bps)`
15	3	akram.mash	`);`
16			`port (`
17			`-- Control`
18	5	akram.mash	`clk : in std_logic; -- Main clock`
19			`rst : in std_logic; -- Main reset`
20	3	akram.mash	`-- External Interface`
21	5	akram.mash	`rx : in std_logic; -- RS232 received serial data`
22			`tx : out std_logic; -- RS232 transmitted serial data`
23	3	akram.mash	`-- uPC Interface`
24	5	akram.mash	`tx_req : in std_logic; -- Request SEND of data`
25			`tx_end : out std_logic; -- Data SENDED`
26			`tx_data : in std_logic_vector(7 downto 0); -- Data to transmit`
27			`rx_ready : out std_logic; -- Received data ready to uPC read`
28			`rx_data : out std_logic_vector(7 downto 0) -- Received data`
29	3	akram.mash	`);`
30			`end uart;`
31
32			`architecture Behavioral of uart is`
33
34			`-- Constants`
35			`constant uart_idle : std_logic := '1';`
36			`constant uart_start : std_logic := '0';`
37
38			`-- Types`
39			`type state is (idle,data,stop1,stop2);`
40
41			`-- Signals`
42			`signal rx_fsm : state;`
43			`signal tx_fsm : state;`
44			`signal clock_en : std_logic;`
45
46			`-- Data Temp`
47			`signal data_cnt_tx : std_logic_vector(2 downto 0) := "000";`
48			`signal data_cnt_rx : std_logic_vector(2 downto 0) := "000";`
49			`signal rx_data_tmp : std_logic_vector(7 downto 0);`
50			`signal tx_data_tmp : std_logic_vector(7 downto 0);`
51
52			`begin`
53
54			`clock_manager:process(clk)`
55			`variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);`
56			`begin`
57			`if clk'event and clk = '1' then`
58			`-- Normal Operation`
59			`if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 then`
60			`clock_en <= '1';`
61			`counter := 0;`
62			`else`
63			`clock_en <= '0';`
64			`counter := counter + 1;`
65			`end if;`
66			`-- Reset condition`
67			`if rst = '1' then`
68			`counter := 0;`
69			`end if;`
70			`end if;`
71			`end process;`
72
73			`tx_proc:process(clk)`
74			`variable data_cnt : std_logic_vector(2 downto 0);`
75			`begin`
76			`if clk'event and clk = '1' then`
77			`if clock_en = '1' then`
78			`-- Default values`
79			`tx_end <= '0';`
80			`tx <= uart_idle;`
81			`-- FSM description`
82			`case tx_fsm is`
83			`-- Wait to transfer data`
84			`when idle =>`
85			`-- Send Init Bit`
86			`if tx_req = '1' then`
87			`tx <= uart_start;`
88			`tx_data_tmp <= tx_data;`
89			`tx_fsm <= data;`
90			`data_cnt_tx <= (others=>'1');`
91			`end if;`
92			`-- Data receive`
93			`when data =>`
94			`tx <= tx_data_tmp(0);`
95			`if data_cnt_tx = 0 then`
96			`tx_fsm <= stop1;`
97			`data_cnt_tx <= (others=>'1');`
98			`else`
99			`tx_data_tmp <= '0' & tx_data_tmp(7 downto 1);`
100			`data_cnt_tx <= data_cnt_tx - 1;`
101			`end if;`
102			`-- End of communication`
103			`when stop1 =>`
104			`-- Send Stop Bit`
105			`tx <= uart_idle;`
106			`tx_fsm <= stop2;`
107			`when stop2 =>`
108			`-- Send Stop Bit`
109			`tx_end <= '1';`
110			`tx <= uart_idle;`
111			`tx_fsm <= idle;`
112			`-- Invalid States`
113			`when others => null;`
114			`end case;`
115			`-- Reset condition`
116			`if rst = '1' then`
117			`tx_fsm <= idle;`
118			`tx_data_tmp <= (others=>'0');`
119			`end if;`
120			`end if;`
121			`end if;`
122			`end process;`
123
124			`rx_proc:process(clk)`
125			`begin`
126			`if clk'event and clk = '1' then`
127			`if clock_en = '1' then`
128			`-- Default values`
129			`rx_ready <= '0';`
130			`-- FSM description`
131			`case rx_fsm is`
132			`-- Wait to transfer data`
133			`when idle =>`
134			`if rx = uart_start then`
135			`rx_fsm <= data;`
136			`end if;`
137			`data_cnt_rx <= (others=>'0');`
138			`-- Data receive`
139			`when data =>`
140			`if data_cnt_rx = 7 then`
141			`rx_fsm <= idle;`
142			`rx_ready <= '1';`
143			`rx_data(7) <= rx;`
144			`for i in 0 to 6 loop`
145			`rx_data(i) <= rx_data_tmp(6-i);`
146			`end loop;`
147			`else`
148			`rx_data_tmp <= rx_data_tmp(6 downto 0) & rx;`
149			`data_cnt_rx <= data_cnt_rx + 1;`
150			`end if;`
151			`when others => null;`
152			`end case;`
153			`-- Reset condition`
154			`if rst = '1' then`
155			`rx_fsm <= idle;`
156			`rx_ready <= '0';`
157			`rx_data <= (others=>'0');`
158			`data_cnt_rx <= (others=>'0');`
159			`end if;`
160			`end if;`
161			`end if;`
162			`end process;`
163
164			`end Behavioral;`
165

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[/] [rs232_interface/] [trunk/] [uart.vhd] - Blame information for rev 5