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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [LODS.v] - Blame information for rev 8

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//=============================================================================
//  LODS
//  Fetch string data from memory.
//
//
//  2009,2010,2013 Robert Finch
//  Stratford
//  robfinch<remove>@finitron.ca
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//=============================================================================
//
LODS:
        if (w && (si==16'hFFFF) && !df) begin
                ir <= `NOP;
                int_num <= 8'd13;
                state <= INT2;
        end
        else begin
                cyc_type <= `CT_RDMEM;
                lock_o <= w;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o  <= 1'b0;
                adr_o <= {seg_reg,`SEG_SHIFT} + si;
                state <= LODS_NACK;
        end
LODS_NACK:
        if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                lock_o <= w;
                cyc_o <= w;
                stb_o <= 1'b0;
                if (df) begin
                        si <= si_dec;
                        if (w)
                                b[15:8] <= dat_i;
                        else begin
                                b[ 7:0] <= dat_i;
                                b[15:8] <= {8{dat_i[7]}};
                        end
                end
                else begin
                        si <= si_inc;
                        b[ 7:0] <= dat_i;
                        b[15:8] <= {8{dat_i[7]}};
                end
                state <= w ? LODS1 : EXECUTE;
        end
 
LODS1:
        begin
                cyc_type <= `CT_RDMEM;
                stb_o <= 1'b1;
                adr_o <= {seg_reg,`SEG_SHIFT} + si;
                state <= LODS1_NACK;
        end
LODS1_NACK:
        if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                if (df) begin
                        si <= si_dec;
                        b[7:0] <= dat_i;
                end
                else begin
                        si <= si_inc;
                        b[15:8] <= dat_i;
                end
                state <= EXECUTE;
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`//=============================================================================`
2			`// LODS`
3			`// Fetch string data from memory.`
4			`//`
5			`//`
6	8	robfinch	`// 2009,2010,2013 Robert Finch`
7	2	robfinch	`// Stratford`
8	8	robfinch	`// robfinch<remove>@finitron.ca`
9	2	robfinch	`//`
10			`//`
11			`// This source file is free software: you can redistribute it and/or modify`
12			`// it under the terms of the GNU Lesser General Public License as published`
13			`// by the Free Software Foundation, either version 3 of the License, or`
14			`// (at your option) any later version.`
15			`//`
16			`// This source file is distributed in the hope that it will be useful,`
17			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
18			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
19			`// GNU General Public License for more details.`
20			`//`
21			`// You should have received a copy of the GNU General Public License`
22			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
23			`//`
24			`//=============================================================================`
25			`//`
26			`LODS:`
27			`if (w && (si==16'hFFFF) && !df) begin`
28			ir <= `NOP;
29			`int_num <= 8'd13;`
30	8	robfinch	`state <= INT2;`
31	2	robfinch	`end`
32			`else begin`
33			cyc_type <= `CT_RDMEM;
34			`lock_o <= w;`
35			`cyc_o <= 1'b1;`
36			`stb_o <= 1'b1;`
37			`we_o <= 1'b0;`
38			adr_o <= {seg_reg,`SEG_SHIFT} + si;
39			`state <= LODS_NACK;`
40			`end`
41			`LODS_NACK:`
42			`if (ack_i) begin`
43			cyc_type <= `CT_PASSIVE;
44			`lock_o <= w;`
45			`cyc_o <= w;`
46			`stb_o <= 1'b0;`
47			`if (df) begin`
48			`si <= si_dec;`
49			`if (w)`
50			`b[15:8] <= dat_i;`
51			`else begin`
52			`b[ 7:0] <= dat_i;`
53			`b[15:8] <= {8{dat_i[7]}};`
54			`end`
55			`end`
56			`else begin`
57			`si <= si_inc;`
58			`b[ 7:0] <= dat_i;`
59			`b[15:8] <= {8{dat_i[7]}};`
60			`end`
61			`state <= w ? LODS1 : EXECUTE;`
62			`end`
63
64			`LODS1:`
65			`begin`
66			cyc_type <= `CT_RDMEM;
67			`stb_o <= 1'b1;`
68			adr_o <= {seg_reg,`SEG_SHIFT} + si;
69			`state <= LODS1_NACK;`
70			`end`
71			`LODS1_NACK:`
72			`if (ack_i) begin`
73			cyc_type <= `CT_PASSIVE;
74			`lock_o <= 1'b0;`
75			`cyc_o <= 1'b0;`
76			`stb_o <= 1'b0;`
77			`if (df) begin`
78			`si <= si_dec;`
79			`b[7:0] <= dat_i;`
80			`end`
81			`else begin`
82			`si <= si_inc;`
83			`b[15:8] <= dat_i;`
84			`end`
85			`state <= EXECUTE;`
86			`end`
87

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [LODS.v] - Blame information for rev 8