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// ============================================================================
//        __
//   \\__/ o\    (C) 2018  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
// rtfSpriteController2.v
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
// ============================================================================
//
//`define USE_CLOCK_GATE        1'b1
 
`define TRUE    1'b1
`define FALSE   1'b0
`define HIGH    1'b1
`define LOW             1'b0
 
`define ABITS   31:0
// The cycle at which it's safe to update the working count and address.
// A good value is just before the end of the scan, but that depends on
// display resolution.
`define SPR_WCA 12'd638
 
module rtfSpriteController2(rst_i, clk_i, cs_i, cyc_i, stb_i, ack_o, we_i, sel_i, adr_i, dat_i, dat_o,
        m_clk_i, m_cyc_o, m_stb_o, m_ack_i, m_sel_o, m_adr_o, m_dat_i,
        dot_clk_i, hsync_i, vsync_i, zrgb_i, zrgb_o, test
);
// Bus slave port
input rst_i;
input clk_i;
input cs_i;
input cyc_i;
input stb_i;
output ack_o;
input we_i;
input [7:0] sel_i;
input [11:0] adr_i;
input [63:0] dat_i;
output reg [63:0] dat_o;
// Bus master port
input m_clk_i;
output reg m_cyc_o;
output m_stb_o;
input m_ack_i;
output [7:0] m_sel_o;
output reg [`ABITS] m_adr_o;
input [63:0] m_dat_i;
// Video port
input dot_clk_i;
input vsync_i;
input hsync_i;
input [31:0] zrgb_i;
output reg [31:0] zrgb_o;
input test;
 
parameter NSPR = 32;
parameter IDLE = 3'd0;
parameter DATA_FETCH = 3'd1;
parameter MEM_ACCESS = 3'd2;
parameter WAIT_NACK = 3'd3;
parameter NEXT_SPRITE = 3'd4;
 
integer n;
 
reg controller_enable;
wire vclk;
reg [2:0] state;
reg [1:0] lowres;
wire [5:0] flashcnt;
reg rst_collision;
reg [31:0] collision, c_collision;
reg [4:0] spriteno;
reg sprite;
reg [31:0] spriteEnable;
reg [31:0] spriteActive;
reg [11:0] sprite_pv [0:31];
reg [11:0] sprite_ph [0:31];
reg [3:0] sprite_pz [0:31];
(* ram_style="distributed" *)
reg [37:0] sprite_color [0:255];
reg [31:0] sprite_on;
reg [31:0] sprite_on_d1;
reg [31:0] sprite_on_d2;
reg [31:0] sprite_on_d3;
(* ram_style="distributed" *)
reg [`ABITS] spriteAddr [0:31];
reg [`ABITS] spriteWaddr [0:31];
reg [15:0] spriteMcnt [0:31];
reg [15:0] spriteWcnt [0:31];
reg [63:0] m_spriteBmp [0:31];
reg [63:0] spriteBmp [0:31];
reg [31:0] spriteLink1;
reg [7:0] spriteColorNdx [0:31];
 
initial begin
        for (n = 0; n < 256; n = n + 1) begin
                sprite_color[n] <= 38'h0000FF1F1F;
        end
        for (n = 0; n < 32; n = n + 1) begin
                sprite_ph[n] <= 260 + n * 40;
                sprite_pv[n] <= 41 + n * 20;
                sprite_pz[n] <= 8'h00;
                spriteMcnt[n] <= 60 * 32;
                spriteBmp[n] <= 64'hFFFFFFFFFFFFFFFF;
        end
end
 
wire pe_hsync, pe_vsync;
wire [11:0] hctr, vctr;
reg [11:0] m_hctr, m_vctr;
 
// Generate acknowledge signal
wire cs = cs_i & cyc_i & stb_i;
reg rdy1,rdy2,rdy3;
always @(posedge clk_i)
        rdy1 <= cs;
always @(posedge clk_i)
        rdy2 <= rdy1 & cs;
always @(posedge clk_i)
        rdy3 <= rdy2 & cs;
assign ack_o = (cs & we_i) ? 1'b1 : rdy3;
 
(* ram_style="block" *)
reg [63:0] shadow_ram [0:511];
reg [8:0] sradr;
always @(posedge clk_i)
        if (cs & we_i) begin
                if (sel_i[0]) shadow_ram[adr_i[11:3]][ 7: 0] <= dat_i;
                if (sel_i[1]) shadow_ram[adr_i[11:3]][15: 8] <= dat_i;
                if (sel_i[2]) shadow_ram[adr_i[11:3]][23:16] <= dat_i;
                if (sel_i[3]) shadow_ram[adr_i[11:3]][31:24] <= dat_i;
                if (sel_i[4]) shadow_ram[adr_i[11:3]][39:32] <= dat_i;
                if (sel_i[5]) shadow_ram[adr_i[11:3]][47:40] <= dat_i;
                if (sel_i[6]) shadow_ram[adr_i[11:3]][55:48] <= dat_i;
                if (sel_i[7]) shadow_ram[adr_i[11:3]][63:56] <= dat_i;
        end
always @(posedge clk_i)
        sradr <= adr_i[11:3];
always @(posedge clk_i)
case(adr_i[11:3])
9'b1010_0001_0: dat_o <= c_collision;
default:        dat_o <= shadow_ram[sradr];
endcase
 
always @(posedge clk_i)
if (rst_i) begin
        rst_collision <= `FALSE;
        controller_enable <= `TRUE;
        spriteEnable <= 32'hFFFFFFFF;
        spriteLink1 <= 32'h0;
end
else begin
        rst_collision <= `FALSE;
        if (cs & we_i) begin
                casez(adr_i[11:3])
                9'b0???_????_?: sprite_color[adr_i[10:3]] <= dat_i[37:0];
                9'b100?_????_0: spriteAddr[adr_i[8:4]] <= dat_i[`ABITS];
                9'b100?_????_1:
                        begin
                                if (|sel_i[1:0]) sprite_ph[adr_i[8:4]] <= dat_i[11: 0];
                                if (|sel_i[3:2]) sprite_pv[adr_i[8:4]] <= dat_i[27:16];
                                if ( sel_i[  4]) sprite_pz[adr_i[8:4]] <= dat_i[39:32];
                                if (|sel_i[7:6]) spriteMcnt[adr_i[8:4]] <= dat_i[63:48];
                        end
                9'b1010_0000_0: spriteEnable <= dat_i[31:0];
                9'b1010_0000_1: spriteLink1 <= dat_i[31:0];
                9'b1010_0001_0: rst_collision <= `TRUE;
                9'b1010_0001_1:
                        begin
                                lowres <= dat_i[1:0];
                                controller_enable <= dat_i[8];
                        end
                endcase
        end
end
 
assign m_stb_o = m_cyc_o;
assign m_sel_o = 8'hFF;
 
// Register hctr to m_clk_i domain
always @(posedge m_clk_i)
        m_hctr <= hctr;
 
// State machine
always @(posedge m_clk_i)
if (rst_i)
        state <= IDLE;
else begin
        case(state)
        IDLE:
                // dot_clk_i is likely faster than m_clk_i, so check for a trigger zone.
                if (m_hctr < 12'd10 && controller_enable)
                        state <= DATA_FETCH;
        DATA_FETCH:
                if (spriteActive[spriteno])
                        state <= MEM_ACCESS;
                else
                        state <= NEXT_SPRITE;
        MEM_ACCESS:
                if (m_ack_i)
                        state <= WAIT_NACK;
        WAIT_NACK:
                if (~m_ack_i)
                        state <= NEXT_SPRITE;
        NEXT_SPRITE:
                if (spriteno==5'd31)
                        state <= IDLE;
                else
                        state <= DATA_FETCH;
        endcase
end
 
always @(posedge m_clk_i)
if (rst_i) begin
        m_cyc_o <= `LOW;
        spriteno <= 5'd0;
end
else begin
        case(state)
        IDLE:
                spriteno <= 5'd0;
        DATA_FETCH:
                if (spriteActive[spriteno]) begin
                        m_cyc_o <= `HIGH;
                        m_adr_o <= spriteWaddr[spriteno];
                end
        MEM_ACCESS:
                if (m_ack_i) begin
                        m_cyc_o <= `LOW;
                        m_spriteBmp[spriteno] <= dat_i;
                        if (test)
                                m_spriteBmp[spriteno] <= 64'h00005555AAAAFFFF;
                end
        NEXT_SPRITE:
                spriteno <= spriteno + 5'd1;
        endcase
end
 
// Register collision onto clk_i domain.
always @(posedge clk_i)
        c_collision <= collision;
 
`ifdef USE_CLOCK_GATE
BUFHCE ucb1
(
        .I(dot_clk_i),
        .CE(controller_enable),
        .O(vclk)
);
`else
assign vclk = dot_clk_i;
`endif
 
edge_det ued1 (.clk(vclk), .ce(1'b1), .i(hsync_i), .pe(pe_hsync), .ne(), .ee());
edge_det ued2 (.clk(vclk), .ce(1'b1), .i(vsync_i), .pe(pe_vsync), .ne(), .ee());
 
VT163 #(12) uhctr (.clk(vclk), .clr_n(!rst_i), .ent(1'b1),     .enp(1'b1), .ld_n(!pe_hsync), .d(12'd0), .q(hctr), .rco());
VT163 #(12) uvctr (.clk(vclk), .clr_n(!rst_i), .ent(pe_hsync), .enp(1'b1), .ld_n(!pe_vsync), .d(12'd0), .q(vctr), .rco());
VT163 # (6) ufctr (.clk(vclk), .clr_n(!rst_i), .ent(pe_vsync), .enp(1'b1), .ld_n(1'b1),  .d( 6'd0), .q(flashcnt), .rco());
 
always @(posedge vclk)
begin
        if (rst_collision)
                collision <= 32'd0;
        else
                case(sprite_on)
                32'b00000000000000000000000000000000,
                32'b00000000000000000000000000000001,
                32'b00000000000000000000000000000010,
                32'b00000000000000000000000000000100,
                32'b00000000000000000000000000001000,
                32'b00000000000000000000000000010000,
                32'b00000000000000000000000000100000,
                32'b00000000000000000000000001000000,
                32'b00000000000000000000000010000000,
                32'b00000000000000000000000100000000,
                32'b00000000000000000000001000000000,
                32'b00000000000000000000010000000000,
                32'b00000000000000000000100000000000,
                32'b00000000000000000001000000000000,
                32'b00000000000000000010000000000000,
                32'b00000000000000000100000000000000,
                32'b00000000000000001000000000000000,
                32'b00000000000000010000000000000000,
                32'b00000000000000100000000000000000,
                32'b00000000000001000000000000000000,
                32'b00000000000010000000000000000000,
                32'b00000000000100000000000000000000,
                32'b00000000001000000000000000000000,
                32'b00000000010000000000000000000000,
                32'b00000000100000000000000000000000,
                32'b00000001000000000000000000000000,
                32'b00000010000000000000000000000000,
                32'b00000100000000000000000000000000,
                32'b00001000000000000000000000000000,
                32'b00010000000000000000000000000000,
                32'b00100000000000000000000000000000,
                32'b01000000000000000000000000000000,
                32'b10000000000000000000000000000000:   ;
                default:        collision <= collision | sprite_on;
                endcase
end
 
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// clock edge #-1
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// Compute when to shift sprite bitmaps.
// Set sprite active flag
// Increment working count and address
 
reg [31:0] spriteShift;
always @(posedge vclk)
for (n = 0; n < NSPR; n = n + 1)
  begin
        spriteShift[n] <= `FALSE;
          case(lowres)
          2'd0,2'd3:    if (hctr >= sprite_ph[n]) spriteShift[n] <= `TRUE;
                2'd1:           if (hctr[11:1] >= sprite_ph[n]) spriteShift[n] <= `TRUE;
                2'd2:           if (hctr[11:2] >= sprite_ph[n]) spriteShift[n] <= `TRUE;
                endcase
        end
 
always @(posedge vclk)
for (n = 0; n < NSPR; n = n + 1)
        spriteActive[n] = (spriteWcnt[n] <= spriteMcnt[n]) && spriteEnable[n];
 
always @(posedge vclk)
for (n = 0; n < NSPR; n = n + 1)
        begin
          case(lowres)
          2'd0,2'd3:    if ((vctr == sprite_pv[n]) && (hctr == 12'h005)) spriteWcnt[n] <= 16'd0;
                2'd1:           if ((vctr[11:1] == sprite_pv[n]) && (hctr == 12'h005)) spriteWcnt[n] <= 16'd0;
                2'd2:           if ((vctr[11:2] == sprite_pv[n]) && (hctr == 12'h005)) spriteWcnt[n] <= 16'd0;
                endcase
                // The following assumes there are at least 640 clocks in a scan line.
                if (hctr==`SPR_WCA)     // must be after image data fetch
                if (spriteActive[n])
                case(lowres)
                2'd0,2'd3:      spriteWcnt[n] <= spriteWcnt[n] + 16'd32;
                2'd1:           if (vctr[0]) spriteWcnt[n] <= spriteWcnt[n] + 16'd32;
                2'd2:           if (vctr[1:0]==2'b11) spriteWcnt[n] <= spriteWcnt[n] + 16'd32;
                endcase
        end
 
always @(posedge vclk)
for (n = 0; n < NSPR; n = n + 1)
        begin
   case(lowres)
   2'd0,2'd3:   if ((vctr == sprite_pv[n]) && (hctr == 12'h005)) spriteWaddr[n] <= spriteAddr[n];
                2'd1:           if ((vctr[11:1] == sprite_pv[n]) && (hctr == 12'h005)) spriteWaddr[n] <= spriteAddr[n];
                2'd2:           if ((vctr[11:2] == sprite_pv[n]) && (hctr == 12'h005)) spriteWaddr[n] <= spriteAddr[n];
                endcase
                if (hctr==`SPR_WCA)     // must be after image data fetch
                case(lowres)
                2'd0,2'd3:      spriteWaddr[n] <= spriteWaddr[n] + 32'd8;
                2'd1:           if (vctr[0]) spriteWaddr[n] <= spriteWaddr[n] + 32'd8;
                2'd2:           if (vctr[1:0]==2'b11) spriteWaddr[n] <= spriteWaddr[n] + 32'd8;
                endcase
        end
 
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// clock edge #0
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// Get the sprite display status
// Load the sprite bitmap from ram
// Determine when sprite output should appear
// Shift the sprite bitmap
// Compute color indexes for all sprites
 
always @(posedge vclk)
begin
  for (n = 0; n < NSPR; n = n + 1)
    if (spriteActive[n] & spriteShift[n]) begin
      sprite_on[n] <=
        spriteLink1[n] ? |{spriteBmp[(n+1)&31][63:62],spriteBmp[n][63:62]} :
        |spriteBmp[n][63:62];
    end
    else
      sprite_on[n] <= 1'b0;
end
 
// Load / shift sprite bitmap
// Register sprite data back to vclk domain
always @(posedge vclk)
begin
        if (hctr==12'h5)
                for (n = 0; n < NSPR; n = n + 1)
                        spriteBmp[n] <= m_spriteBmp[n];
  for (n = 0; n < NSPR; n = n + 1)
    if (spriteShift[n])
        case(lowres)
        2'd0,2'd3:      spriteBmp[n] <= {spriteBmp[n][61:0],2'h0};
        2'd1:   if (hctr[0]) spriteBmp[n] <= {spriteBmp[n][61:0],2'h0};
        2'd2:   if (&hctr[1:0]) spriteBmp[n] <= {spriteBmp[n][61:0],2'h0};
                        endcase
end
 
always @(posedge vclk)
for (n = 0; n < NSPR; n = n + 1)
if (spriteLink1[n])
  spriteColorNdx[n] <= {n[3:0],spriteBmp[(n+1)&31][63:62],spriteBmp[n][63:62]};
else if (spriteLink1[(n-1)&31])
        spriteColorNdx[n] <= 8'h00;     // transparent
else
  spriteColorNdx[n] <= {1'b0,n[4:0],spriteBmp[n][63:62]};
 
// Compute index into sprite color palette
// If none of the sprites are linked, each sprite has it's own set of colors.
// If the sprites are linked once the colors are available in groups.
// If the sprites are linked twice they all share the same set of colors.
// Pipelining register
reg blank1, blank2, blank3, blank4;
reg border1, border2, border3, border4;
reg any_sprite_on2, any_sprite_on3, any_sprite_on4;
reg [31:0] zrgb_i3, zrgb_i4;
reg [7:0] zb_i3, zb_i4;
reg [7:0] sprite_z1, sprite_z2, sprite_z3, sprite_z4;
reg [7:0] sprite_pzx;
// The color index from each sprite can be mux'ed into a single value used to
// access the color palette because output color is a priority chain. This
// saves having mulriple read ports on the color palette.
reg [37:0] spriteColorOut2;
reg [37:0] spriteColorOut3;
reg [7:0] spriteClrNdx;
 
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// clock edge #1
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// Mux color index
// Fetch sprite Z order
 
always @(posedge vclk)
    sprite_on_d1 <= sprite_on;
 
always @(posedge vclk)
begin
        spriteClrNdx <= 8'd0;
        for (n = NSPR-1; n >= 0; n = n -1)
                if (sprite_on[n])
                        spriteClrNdx <= spriteColorNdx[n];
end
 
always @(posedge vclk)
begin
        sprite_z1 <= 8'hff;
        for (n = NSPR-1; n >= 0; n = n -1)
                if (sprite_on[n])
                        sprite_z1 <= sprite_pz[n];
end
 
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// clock edge #2
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// Lookup color from palette
 
always @(posedge vclk)
    sprite_on_d2 <= sprite_on_d1;
always @(posedge vclk)
    any_sprite_on2 <= |sprite_on_d1;
always @(posedge vclk)
    blank2 <= blank1;
always @(posedge vclk)
    border2 <= border1;
always @(posedge vclk)
    spriteColorOut2 <= sprite_color[spriteClrNdx];
always @(posedge vclk)
    sprite_z2 <= sprite_z1;
 
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// clock edge #3
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// Compute alpha blending
 
wire [15:0] alphaRed = (zrgb_i[23:16] * spriteColorOut2[31:24]) + (spriteColorOut2[23:16] * (9'h100 - spriteColorOut2[31:24]));
wire [15:0] alphaGreen = (zrgb_i[15:8] * spriteColorOut2[31:24]) + (spriteColorOut2[15:8]  * (9'h100 - spriteColorOut2[31:24]));
wire [15:0] alphaBlue = (zrgb_i[7:0] * spriteColorOut2[31:24]) + (spriteColorOut2[7:0]  * (9'h100 - spriteColorOut2[31:24]));
reg [23:0] alphaOut;
 
always @(posedge vclk)
    alphaOut <= {alphaRed[15:8],alphaGreen[15:8],alphaBlue[15:8]};
always @(posedge vclk)
    sprite_z3 <= sprite_z2;
always @(posedge vclk)
    any_sprite_on3 <= any_sprite_on2;
always @(posedge vclk)
    zrgb_i3 <= zrgb_i;
always @(posedge vclk)
    zb_i3 <= zrgb_i[31:24];
always @(posedge vclk)
    blank3 <= blank2;
always @(posedge vclk)
    border3 <= border2;
always @(posedge vclk)
    spriteColorOut3 <= spriteColorOut2;
 
reg [23:0] flashOut;
wire [23:0] reverseVideoOut = spriteColorOut2[37] ? alphaOut ^ 24'hFFFFFF : alphaOut;
 
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// clock edge #4
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// Compute flash output
 
always @(posedge vclk)
    flashOut <= spriteColorOut3[36] ? (((flashcnt[5:2] & spriteColorOut3[35:32])!=4'b0000) ? reverseVideoOut : zrgb_i3) : reverseVideoOut;
always @(posedge vclk)
    zrgb_i4 <= zrgb_i3;
always @(posedge vclk)
    sprite_z4 <= sprite_z3;
always @(posedge vclk)
    any_sprite_on4 <= any_sprite_on3;
always @(posedge vclk)
    zb_i4 <= zb_i3;
always @(posedge vclk)
    blank4 <= blank3;
always @(posedge vclk)
    border4 <= border3;
 
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// clock edge #5
// -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -
// final output registration
 
always @(posedge dot_clk_i)
        case(any_sprite_on4 & controller_enable)
        1'b1:           zrgb_o <= (zb_i4 < sprite_z4) ? zrgb_i4 : {sprite_z4,flashOut};
        1'b0:           zrgb_o <= zrgb_i4;
        endcase
 
endmodule
 

Line No.	Rev	Author	Line
1	4	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2018 Robert Finch, Waterloo`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@finitron.ca`
6			`// \|\|`
7			`//`
8			`// rtfSpriteController2.v`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`// ============================================================================`
24			`//`
25	5	robfinch	//`define USE_CLOCK_GATE 1'b1
26
27	4	robfinch	`define TRUE 1'b1
28			`define FALSE 1'b0
29			`define HIGH 1'b1
30			`define LOW 1'b0
31
32			`define ABITS 31:0
33	5	robfinch	`// The cycle at which it's safe to update the working count and address.`
34			`// A good value is just before the end of the scan, but that depends on`
35			`// display resolution.`
36			`define SPR_WCA 12'd638
37	4	robfinch
38			`module rtfSpriteController2(rst_i, clk_i, cs_i, cyc_i, stb_i, ack_o, we_i, sel_i, adr_i, dat_i, dat_o,`
39			`m_clk_i, m_cyc_o, m_stb_o, m_ack_i, m_sel_o, m_adr_o, m_dat_i,`
40			`dot_clk_i, hsync_i, vsync_i, zrgb_i, zrgb_o, test`
41			`);`
42			`// Bus slave port`
43			`input rst_i;`
44			`input clk_i;`
45			`input cs_i;`
46			`input cyc_i;`
47			`input stb_i;`
48			`output ack_o;`
49			`input we_i;`
50			`input [7:0] sel_i;`
51			`input [11:0] adr_i;`
52			`input [63:0] dat_i;`
53			`output reg [63:0] dat_o;`
54			`// Bus master port`
55			`input m_clk_i;`
56			`output reg m_cyc_o;`
57			`output m_stb_o;`
58			`input m_ack_i;`
59			`output [7:0] m_sel_o;`
60			output reg [`ABITS] m_adr_o;
61			`input [63:0] m_dat_i;`
62			`// Video port`
63			`input dot_clk_i;`
64			`input vsync_i;`
65			`input hsync_i;`
66			`input [31:0] zrgb_i;`
67			`output reg [31:0] zrgb_o;`
68			`input test;`
69
70			`parameter NSPR = 32;`
71			`parameter IDLE = 3'd0;`
72			`parameter DATA_FETCH = 3'd1;`
73			`parameter MEM_ACCESS = 3'd2;`
74			`parameter WAIT_NACK = 3'd3;`
75			`parameter NEXT_SPRITE = 3'd4;`
76
77			`integer n;`
78
79			`reg controller_enable;`
80			`wire vclk;`
81			`reg [2:0] state;`
82			`reg [1:0] lowres;`
83	5	robfinch	`wire [5:0] flashcnt;`
84	4	robfinch	`reg rst_collision;`
85			`reg [31:0] collision, c_collision;`
86			`reg [4:0] spriteno;`
87			`reg sprite;`
88			`reg [31:0] spriteEnable;`
89			`reg [31:0] spriteActive;`
90			`reg [11:0] sprite_pv [0:31];`
91			`reg [11:0] sprite_ph [0:31];`
92			`reg [3:0] sprite_pz [0:31];`
93	5	robfinch	`(* ram_style="distributed" *)`
94	4	robfinch	`reg [37:0] sprite_color [0:255];`
95			`reg [31:0] sprite_on;`
96			`reg [31:0] sprite_on_d1;`
97			`reg [31:0] sprite_on_d2;`
98			`reg [31:0] sprite_on_d3;`
99	5	robfinch	`(* ram_style="distributed" *)`
100	4	robfinch	reg [`ABITS] spriteAddr [0:31];
101			reg [`ABITS] spriteWaddr [0:31];
102			`reg [15:0] spriteMcnt [0:31];`
103			`reg [15:0] spriteWcnt [0:31];`
104			`reg [63:0] m_spriteBmp [0:31];`
105			`reg [63:0] spriteBmp [0:31];`
106			`reg [31:0] spriteLink1;`
107	5	robfinch	`reg [7:0] spriteColorNdx [0:31];`
108	4	robfinch
109			`initial begin`
110			`for (n = 0; n < 256; n = n + 1) begin`
111	5	robfinch	`sprite_color[n] <= 38'h0000FF1F1F;`
112	4	robfinch	`end`
113			`for (n = 0; n < 32; n = n + 1) begin`
114	5	robfinch	`sprite_ph[n] <= 260 + n * 40;`
115			`sprite_pv[n] <= 41 + n * 20;`
116			`sprite_pz[n] <= 8'h00;`
117			`spriteMcnt[n] <= 60 * 32;`
118			`spriteBmp[n] <= 64'hFFFFFFFFFFFFFFFF;`
119	4	robfinch	`end`
120			`end`
121
122			`wire pe_hsync, pe_vsync;`
123	5	robfinch	`wire [11:0] hctr, vctr;`
124			`reg [11:0] m_hctr, m_vctr;`
125	4	robfinch
126			`// Generate acknowledge signal`
127			`wire cs = cs_i & cyc_i & stb_i;`
128			`reg rdy1,rdy2,rdy3;`
129			`always @(posedge clk_i)`
130			`rdy1 <= cs;`
131			`always @(posedge clk_i)`
132			`rdy2 <= rdy1 & cs;`
133			`always @(posedge clk_i)`
134			`rdy3 <= rdy2 & cs;`
135	5	robfinch	`assign ack_o = (cs & we_i) ? 1'b1 : rdy3;`
136	4	robfinch
137			`(* ram_style="block" *)`
138			`reg [63:0] shadow_ram [0:511];`
139	5	robfinch	`reg [8:0] sradr;`
140	4	robfinch	`always @(posedge clk_i)`
141			`if (cs & we_i) begin`
142			`if (sel_i[0]) shadow_ram[adr_i[11:3]][ 7: 0] <= dat_i;`
143			`if (sel_i[1]) shadow_ram[adr_i[11:3]][15: 8] <= dat_i;`
144			`if (sel_i[2]) shadow_ram[adr_i[11:3]][23:16] <= dat_i;`
145			`if (sel_i[3]) shadow_ram[adr_i[11:3]][31:24] <= dat_i;`
146			`if (sel_i[4]) shadow_ram[adr_i[11:3]][39:32] <= dat_i;`
147			`if (sel_i[5]) shadow_ram[adr_i[11:3]][47:40] <= dat_i;`
148			`if (sel_i[6]) shadow_ram[adr_i[11:3]][55:48] <= dat_i;`
149			`if (sel_i[7]) shadow_ram[adr_i[11:3]][63:56] <= dat_i;`
150			`end`
151			`always @(posedge clk_i)`
152			`sradr <= adr_i[11:3];`
153			`always @(posedge clk_i)`
154			`case(adr_i[11:3])`
155			`9'b1010_0001_0: dat_o <= c_collision;`
156			`default: dat_o <= shadow_ram[sradr];`
157			`endcase`
158
159			`always @(posedge clk_i)`
160			`if (rst_i) begin`
161			rst_collision <= `FALSE;
162			controller_enable <= `TRUE;
163			`spriteEnable <= 32'hFFFFFFFF;`
164	5	robfinch	`spriteLink1 <= 32'h0;`
165	4	robfinch	`end`
166			`else begin`
167			rst_collision <= `FALSE;
168			`if (cs & we_i) begin`
169			`casez(adr_i[11:3])`
170			`9'b0???_????_?: sprite_color[adr_i[10:3]] <= dat_i[37:0];`
171			9'b100?_????_0: spriteAddr[adr_i[8:4]] <= dat_i[`ABITS];
172			`9'b100?_????_1:`
173			`begin`
174			`if (\|sel_i[1:0]) sprite_ph[adr_i[8:4]] <= dat_i[11: 0];`
175			`if (\|sel_i[3:2]) sprite_pv[adr_i[8:4]] <= dat_i[27:16];`
176	5	robfinch	`if ( sel_i[ 4]) sprite_pz[adr_i[8:4]] <= dat_i[39:32];`
177	4	robfinch	`if (\|sel_i[7:6]) spriteMcnt[adr_i[8:4]] <= dat_i[63:48];`
178			`end`
179			`9'b1010_0000_0: spriteEnable <= dat_i[31:0];`
180			`9'b1010_0000_1: spriteLink1 <= dat_i[31:0];`
181			9'b1010_0001_0: rst_collision <= `TRUE;
182			`9'b1010_0001_1:`
183			`begin`
184			`lowres <= dat_i[1:0];`
185			`controller_enable <= dat_i[8];`
186			`end`
187			`endcase`
188			`end`
189			`end`
190
191			`assign m_stb_o = m_cyc_o;`
192			`assign m_sel_o = 8'hFF;`
193
194			`// Register hctr to m_clk_i domain`
195			`always @(posedge m_clk_i)`
196			`m_hctr <= hctr;`
197
198			`// State machine`
199			`always @(posedge m_clk_i)`
200			`if (rst_i)`
201			`state <= IDLE;`
202			`else begin`
203			`case(state)`
204			`IDLE:`
205			`// dot_clk_i is likely faster than m_clk_i, so check for a trigger zone.`
206			`if (m_hctr < 12'd10 && controller_enable)`
207			`state <= DATA_FETCH;`
208			`DATA_FETCH:`
209			`if (spriteActive[spriteno])`
210			`state <= MEM_ACCESS;`
211			`else`
212			`state <= NEXT_SPRITE;`
213			`MEM_ACCESS:`
214			`if (m_ack_i)`
215			`state <= WAIT_NACK;`
216			`WAIT_NACK:`
217			`if (~m_ack_i)`
218			`state <= NEXT_SPRITE;`
219			`NEXT_SPRITE:`
220			`if (spriteno==5'd31)`
221			`state <= IDLE;`
222			`else`
223			`state <= DATA_FETCH;`
224			`endcase`
225			`end`
226
227			`always @(posedge m_clk_i)`
228			`if (rst_i) begin`
229			m_cyc_o <= `LOW;
230			`spriteno <= 5'd0;`
231			`end`
232			`else begin`
233			`case(state)`
234			`IDLE:`
235			`spriteno <= 5'd0;`
236			`DATA_FETCH:`
237			`if (spriteActive[spriteno]) begin`
238			m_cyc_o <= `HIGH;
239			`m_adr_o <= spriteWaddr[spriteno];`
240			`end`
241			`MEM_ACCESS:`
242			`if (m_ack_i) begin`
243			m_cyc_o <= `LOW;
244	5	robfinch	`m_spriteBmp[spriteno] <= dat_i;`
245	4	robfinch	`if (test)`
246	5	robfinch	`m_spriteBmp[spriteno] <= 64'h00005555AAAAFFFF;`
247	4	robfinch	`end`
248			`NEXT_SPRITE:`
249			`spriteno <= spriteno + 5'd1;`
250			`endcase`
251			`end`
252
253			`// Register collision onto clk_i domain.`
254			`always @(posedge clk_i)`
255			`c_collision <= collision;`
256
257	5	robfinch	`ifdef USE_CLOCK_GATE
258	4	robfinch	`BUFHCE ucb1`
259			`(`
260			`.I(dot_clk_i),`
261			`.CE(controller_enable),`
262			`.O(vclk)`
263			`);`
264	5	robfinch	`else
265			`assign vclk = dot_clk_i;`
266			`endif
267	4	robfinch
268			`edge_det ued1 (.clk(vclk), .ce(1'b1), .i(hsync_i), .pe(pe_hsync), .ne(), .ee());`
269			`edge_det ued2 (.clk(vclk), .ce(1'b1), .i(vsync_i), .pe(pe_vsync), .ne(), .ee());`
270
271	5	robfinch	`VT163 #(12) uhctr (.clk(vclk), .clr_n(!rst_i), .ent(1'b1), .enp(1'b1), .ld_n(!pe_hsync), .d(12'd0), .q(hctr), .rco());`
272			`VT163 #(12) uvctr (.clk(vclk), .clr_n(!rst_i), .ent(pe_hsync), .enp(1'b1), .ld_n(!pe_vsync), .d(12'd0), .q(vctr), .rco());`
273			`VT163 # (6) ufctr (.clk(vclk), .clr_n(!rst_i), .ent(pe_vsync), .enp(1'b1), .ld_n(1'b1), .d( 6'd0), .q(flashcnt), .rco());`
274	4	robfinch
275			`always @(posedge vclk)`
276			`begin`
277			`if (rst_collision)`
278			`collision <= 32'd0;`
279			`else`
280			`case(sprite_on)`
281			`32'b00000000000000000000000000000000,`
282			`32'b00000000000000000000000000000001,`
283			`32'b00000000000000000000000000000010,`
284			`32'b00000000000000000000000000000100,`
285			`32'b00000000000000000000000000001000,`
286			`32'b00000000000000000000000000010000,`
287			`32'b00000000000000000000000000100000,`
288			`32'b00000000000000000000000001000000,`
289			`32'b00000000000000000000000010000000,`
290			`32'b00000000000000000000000100000000,`
291			`32'b00000000000000000000001000000000,`
292			`32'b00000000000000000000010000000000,`
293			`32'b00000000000000000000100000000000,`
294			`32'b00000000000000000001000000000000,`
295			`32'b00000000000000000010000000000000,`
296			`32'b00000000000000000100000000000000,`
297			`32'b00000000000000001000000000000000,`
298			`32'b00000000000000010000000000000000,`
299			`32'b00000000000000100000000000000000,`
300			`32'b00000000000001000000000000000000,`
301			`32'b00000000000010000000000000000000,`
302			`32'b00000000000100000000000000000000,`
303			`32'b00000000001000000000000000000000,`
304			`32'b00000000010000000000000000000000,`
305			`32'b00000000100000000000000000000000,`
306			`32'b00000001000000000000000000000000,`
307			`32'b00000010000000000000000000000000,`
308			`32'b00000100000000000000000000000000,`
309			`32'b00001000000000000000000000000000,`
310			`32'b00010000000000000000000000000000,`
311			`32'b00100000000000000000000000000000,`
312			`32'b01000000000000000000000000000000,`
313			`32'b10000000000000000000000000000000: ;`
314			`default: collision <= collision \| sprite_on;`
315			`endcase`
316			`end`
317
318			`// - - - - - - - - - - - - - - - - - - - - - - - - - -`
319			`// clock edge #-1`
320			`// - - - - - - - - - - - - - - - - - - - - - - - - - -`
321			`// Compute when to shift sprite bitmaps.`
322			`// Set sprite active flag`
323			`// Increment working count and address`
324
325			`reg [31:0] spriteShift;`
326			`always @(posedge vclk)`
327			`for (n = 0; n < NSPR; n = n + 1)`
328			`begin`
329			spriteShift[n] <= `FALSE;
330			`case(lowres)`
331			2'd0,2'd3: if (hctr >= sprite_ph[n]) spriteShift[n] <= `TRUE;
332			2'd1: if (hctr[11:1] >= sprite_ph[n]) spriteShift[n] <= `TRUE;
333			2'd2: if (hctr[11:2] >= sprite_ph[n]) spriteShift[n] <= `TRUE;
334			`endcase`
335			`end`
336
337			`always @(posedge vclk)`
338			`for (n = 0; n < NSPR; n = n + 1)`
339			`spriteActive[n] = (spriteWcnt[n] <= spriteMcnt[n]) && spriteEnable[n];`
340
341			`always @(posedge vclk)`
342			`for (n = 0; n < NSPR; n = n + 1)`
343			`begin`
344			`case(lowres)`
345			`2'd0,2'd3: if ((vctr == sprite_pv[n]) && (hctr == 12'h005)) spriteWcnt[n] <= 16'd0;`
346			`2'd1: if ((vctr[11:1] == sprite_pv[n]) && (hctr == 12'h005)) spriteWcnt[n] <= 16'd0;`
347			`2'd2: if ((vctr[11:2] == sprite_pv[n]) && (hctr == 12'h005)) spriteWcnt[n] <= 16'd0;`
348			`endcase`
349			`// The following assumes there are at least 640 clocks in a scan line.`
350	5	robfinch	if (hctr==`SPR_WCA) // must be after image data fetch
351	4	robfinch	`if (spriteActive[n])`
352			`case(lowres)`
353			`2'd0,2'd3: spriteWcnt[n] <= spriteWcnt[n] + 16'd32;`
354			`2'd1: if (vctr[0]) spriteWcnt[n] <= spriteWcnt[n] + 16'd32;`
355			`2'd2: if (vctr[1:0]==2'b11) spriteWcnt[n] <= spriteWcnt[n] + 16'd32;`
356			`endcase`
357			`end`
358
359			`always @(posedge vclk)`
360			`for (n = 0; n < NSPR; n = n + 1)`
361			`begin`
362			`case(lowres)`
363			`2'd0,2'd3: if ((vctr == sprite_pv[n]) && (hctr == 12'h005)) spriteWaddr[n] <= spriteAddr[n];`
364			`2'd1: if ((vctr[11:1] == sprite_pv[n]) && (hctr == 12'h005)) spriteWaddr[n] <= spriteAddr[n];`
365			`2'd2: if ((vctr[11:2] == sprite_pv[n]) && (hctr == 12'h005)) spriteWaddr[n] <= spriteAddr[n];`
366			`endcase`
367	5	robfinch	if (hctr==`SPR_WCA) // must be after image data fetch
368	4	robfinch	`case(lowres)`
369	5	robfinch	`2'd0,2'd3: spriteWaddr[n] <= spriteWaddr[n] + 32'd8;`
370			`2'd1: if (vctr[0]) spriteWaddr[n] <= spriteWaddr[n] + 32'd8;`
371			`2'd2: if (vctr[1:0]==2'b11) spriteWaddr[n] <= spriteWaddr[n] + 32'd8;`
372	4	robfinch	`endcase`
373			`end`
374
375			`// - - - - - - - - - - - - - - - - - - - - - - - - - -`
376			`// clock edge #0`
377			`// - - - - - - - - - - - - - - - - - - - - - - - - - -`
378			`// Get the sprite display status`
379			`// Load the sprite bitmap from ram`
380			`// Determine when sprite output should appear`
381			`// Shift the sprite bitmap`
382			`// Compute color indexes for all sprites`
383
384			`always @(posedge vclk)`
385			`begin`
386			`for (n = 0; n < NSPR; n = n + 1)`
387			`if (spriteActive[n] & spriteShift[n]) begin`
388			`sprite_on[n] <=`
389			`spriteLink1[n] ? \|{spriteBmp[(n+1)&31][63:62],spriteBmp[n][63:62]} :`
390			`\|spriteBmp[n][63:62];`
391			`end`
392			`else`
393			`sprite_on[n] <= 1'b0;`
394			`end`
395
396			`// Load / shift sprite bitmap`
397			`// Register sprite data back to vclk domain`
398			`always @(posedge vclk)`
399			`begin`
400			`if (hctr==12'h5)`
401			`for (n = 0; n < NSPR; n = n + 1)`
402			`spriteBmp[n] <= m_spriteBmp[n];`
403	5	robfinch	`for (n = 0; n < NSPR; n = n + 1)`
404			`if (spriteShift[n])`
405			`case(lowres)`
406			`2'd0,2'd3: spriteBmp[n] <= {spriteBmp[n][61:0],2'h0};`
407			`2'd1: if (hctr[0]) spriteBmp[n] <= {spriteBmp[n][61:0],2'h0};`
408			`2'd2: if (&hctr[1:0]) spriteBmp[n] <= {spriteBmp[n][61:0],2'h0};`
409			`endcase`
410	4	robfinch	`end`
411
412			`always @(posedge vclk)`
413			`for (n = 0; n < NSPR; n = n + 1)`
414	5	robfinch	`if (spriteLink1[n])`
415	4	robfinch	`spriteColorNdx[n] <= {n[3:0],spriteBmp[(n+1)&31][63:62],spriteBmp[n][63:62]};`
416	5	robfinch	`else if (spriteLink1[(n-1)&31])`
417	4	robfinch	`spriteColorNdx[n] <= 8'h00; // transparent`
418			`else`
419	5	robfinch	`spriteColorNdx[n] <= {1'b0,n[4:0],spriteBmp[n][63:62]};`
420	4	robfinch
421			`// Compute index into sprite color palette`
422			`// If none of the sprites are linked, each sprite has it's own set of colors.`
423			`// If the sprites are linked once the colors are available in groups.`
424			`// If the sprites are linked twice they all share the same set of colors.`
425			`// Pipelining register`
426			`reg blank1, blank2, blank3, blank4;`
427			`reg border1, border2, border3, border4;`
428			`reg any_sprite_on2, any_sprite_on3, any_sprite_on4;`
429			`reg [31:0] zrgb_i3, zrgb_i4;`
430			`reg [7:0] zb_i3, zb_i4;`
431			`reg [7:0] sprite_z1, sprite_z2, sprite_z3, sprite_z4;`
432			`reg [7:0] sprite_pzx;`
433			`// The color index from each sprite can be mux'ed into a single value used to`
434			`// access the color palette because output color is a priority chain. This`
435			`// saves having mulriple read ports on the color palette.`
436	5	robfinch	`reg [37:0] spriteColorOut2;`
437			`reg [37:0] spriteColorOut3;`
438	4	robfinch	`reg [7:0] spriteClrNdx;`
439
440			`// - - - - - - - - - - - - - - - - - - - - - - - - - -`
441			`// clock edge #1`
442			`// - - - - - - - - - - - - - - - - - - - - - - - - - -`
443			`// Mux color index`
444			`// Fetch sprite Z order`
445
446			`always @(posedge vclk)`
447			`sprite_on_d1 <= sprite_on;`
448
449			`always @(posedge vclk)`
450			`begin`
451			`spriteClrNdx <= 8'd0;`
452			`for (n = NSPR-1; n >= 0; n = n -1)`
453			`if (sprite_on[n])`
454			`spriteClrNdx <= spriteColorNdx[n];`
455			`end`
456
457			`always @(posedge vclk)`
458			`begin`
459	5	robfinch	`sprite_z1 <= 8'hff;`
460	4	robfinch	`for (n = NSPR-1; n >= 0; n = n -1)`
461			`if (sprite_on[n])`
462			`sprite_z1 <= sprite_pz[n];`
463			`end`
464
465			`// - - - - - - - - - - - - - - - - - - - - - - - - - -`
466			`// clock edge #2`
467			`// - - - - - - - - - - - - - - - - - - - - - - - - - -`
468			`// Lookup color from palette`
469
470			`always @(posedge vclk)`
471			`sprite_on_d2 <= sprite_on_d1;`
472			`always @(posedge vclk)`
473			`any_sprite_on2 <= \|sprite_on_d1;`
474			`always @(posedge vclk)`
475			`blank2 <= blank1;`
476			`always @(posedge vclk)`
477			`border2 <= border1;`
478			`always @(posedge vclk)`
479			`spriteColorOut2 <= sprite_color[spriteClrNdx];`
480			`always @(posedge vclk)`
481			`sprite_z2 <= sprite_z1;`
482
483			`// - - - - - - - - - - - - - - - - - - - - - - - - - -`
484			`// clock edge #3`
485			`// - - - - - - - - - - - - - - - - - - - - - - - - - -`
486			`// Compute alpha blending`
487
488	5	robfinch	`wire [15:0] alphaRed = (zrgb_i[23:16] * spriteColorOut2[31:24]) + (spriteColorOut2[23:16] * (9'h100 - spriteColorOut2[31:24]));`
489			`wire [15:0] alphaGreen = (zrgb_i[15:8] * spriteColorOut2[31:24]) + (spriteColorOut2[15:8] * (9'h100 - spriteColorOut2[31:24]));`
490			`wire [15:0] alphaBlue = (zrgb_i[7:0] * spriteColorOut2[31:24]) + (spriteColorOut2[7:0] * (9'h100 - spriteColorOut2[31:24]));`
491	4	robfinch	`reg [23:0] alphaOut;`
492
493			`always @(posedge vclk)`
494	5	robfinch	`alphaOut <= {alphaRed[15:8],alphaGreen[15:8],alphaBlue[15:8]};`
495	4	robfinch	`always @(posedge vclk)`
496			`sprite_z3 <= sprite_z2;`
497			`always @(posedge vclk)`
498			`any_sprite_on3 <= any_sprite_on2;`
499			`always @(posedge vclk)`
500			`zrgb_i3 <= zrgb_i;`

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[/] [rtf_sprite_controller/] [trunk/] [rtl/] [verilog/] [rtfSpriteController2.v] - Blame information for rev 5