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// ============================================================================
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// __
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// \\__/ o\ (C) 2018-2023 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// ||
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//
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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`define VENDOR_XILINX
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module rfTextScreenRam(clka_i, csa_i, wea_i, sela_i, adra_i, data_i, data_o,
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clkb_i, csb_i, web_i, selb_i, adrb_i, datb_i, datb_o);
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input clka_i;
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input csa_i;
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input wea_i;
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input [7:0] sela_i;
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input [16:3] adra_i;
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input [63:0] data_i;
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output [63:0] data_o;
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input clkb_i;
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input csb_i;
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input web_i;
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input [7:0] selb_i;
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input [16:3] adrb_i;
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input [63:0] datb_i;
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output [63:0] datb_o;
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parameter TEXT_CELL_COUNT = 16384;
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localparam AWID = $clog2(TEXT_CELL_COUNT);
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// xpm_memory_tdpram: True Dual Port RAM
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// Xilinx Parameterized Macro, version 2020.2
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`ifdef VENDOR_XILINX
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xpm_memory_tdpram #(
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.ADDR_WIDTH_A(AWID),
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.ADDR_WIDTH_B(AWID),
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.AUTO_SLEEP_TIME(0),
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.BYTE_WRITE_WIDTH_A(8),
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.BYTE_WRITE_WIDTH_B(8),
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.CASCADE_HEIGHT(0),
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.CLOCKING_MODE("independent_clock"), // String
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.ECC_MODE("no_ecc"), // String
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.MEMORY_INIT_FILE("none"), // String
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.MEMORY_INIT_PARAM("0"), // String
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.MEMORY_OPTIMIZATION("true"), // String
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.MEMORY_PRIMITIVE("block"), // String
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.MEMORY_SIZE(TEXT_CELL_COUNT*64),
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.MESSAGE_CONTROL(0),
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.READ_DATA_WIDTH_A(64),
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.READ_DATA_WIDTH_B(64),
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.READ_LATENCY_A(2),
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.READ_LATENCY_B(1),
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.READ_RESET_VALUE_A("0"), // String
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.READ_RESET_VALUE_B("0"), // String
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.RST_MODE_A("SYNC"), // String
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.RST_MODE_B("SYNC"), // String
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.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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.USE_EMBEDDED_CONSTRAINT(0), // DECIMAL
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.USE_MEM_INIT(1),
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.WAKEUP_TIME("disable_sleep"), // String
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.WRITE_DATA_WIDTH_A(64),
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.WRITE_DATA_WIDTH_B(64),
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.WRITE_MODE_A("no_change"), // String
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.WRITE_MODE_B("no_change") // String
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)
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xpm_memory_tdpram_inst (
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.dbiterra(), // 1-bit output: Status signal to indicate double bit error occurrence
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// on the data output of port A.
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.dbiterrb(), // 1-bit output: Status signal to indicate double bit error occurrence
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// on the data output of port A.
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.douta(data_o), // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
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.doutb(datb_o), // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
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.sbiterra(), // 1-bit output: Status signal to indicate single bit error occurrence
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// on the data output of port A.
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.sbiterrb(), // 1-bit output: Status signal to indicate single bit error occurrence
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// on the data output of port B.
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.addra(adra_i), // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
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.addrb(adrb_i), // ADDR_WIDTH_B-bit input: Address for port B write and read operations.
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.clka(clka_i), // 1-bit input: Clock signal for port A. Also clocks port B when
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// parameter CLOCKING_MODE is "common_clock".
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.clkb(clkb_i), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
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// "independent_clock". Unused when parameter CLOCKING_MODE is
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// "common_clock".
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.dina(data_i), // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
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.dinb(datb_i), // WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations.
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.ena(csa_i), // 1-bit input: Memory enable signal for port A. Must be high on clock
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// cycles when read or write operations are initiated. Pipelined
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// internally.
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.enb(csb_i), // 1-bit input: Memory enable signal for port B. Must be high on clock
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// cycles when read or write operations are initiated. Pipelined
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// internally.
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.injectdbiterra(1'b0), // 1-bit input: Controls double bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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.injectdbiterrb(1'b0), // 1-bit input: Controls double bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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.injectsbiterra(1'b0), // 1-bit input: Controls single bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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.injectsbiterrb(1'b0), // 1-bit input: Controls single bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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.regcea(csa_i), // 1-bit input: Clock Enable for the last register stage on the output
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// data path.
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.regceb(csb_i), // 1-bit input: Clock Enable for the last register stage on the output
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// data path.
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.rsta(1'b0), // 1-bit input: Reset signal for the final port A output register stage.
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// Synchronously resets output port douta to the value specified by
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// parameter READ_RESET_VALUE_A.
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.rstb(1'b0), // 1-bit input: Reset signal for the final port B output register stage.
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// Synchronously resets output port doutb to the value specified by
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// parameter READ_RESET_VALUE_B.
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.sleep(1'b0), // 1-bit input: sleep signal to enable the dynamic power saving feature.
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.wea({8{wea_i}} & sela_i), // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
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// for port A input data port dina. 1 bit wide when word-wide writes are
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// used. In byte-wide write configurations, each bit controls the
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// writing one byte of dina to address addra. For example, to
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// synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
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// is 32, wea would be 4'b0010.
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.web({8{web_i}} & selb_i) // WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
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// for port B input data port dinb. 1 bit wide when word-wide writes are
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// used. In byte-wide write configurations, each bit controls the
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// writing one byte of dinb to address addrb. For example, to
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// synchronously write only bits [15-8] of dinb when WRITE_DATA_WIDTH_B
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// is 32, web would be 4'b0010.
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);
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`elsif VENDOR_ALTERA
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always_comb
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begin
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$display("ToDo: Add ALTERA RAM support.");
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$finish();
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end
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`else
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always_comb
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begin
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$display("No RAM vendor selected.");
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$finish();
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end
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`endif
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endmodule
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