Subversion Repositories rv01_riscv_core

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-- RV01 top-level module synthesis script

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Tcl script rv01_selftest_syn.tcl creates a Vivado project synthesizing

RV01 core top-level module and mapping it to Nexis 4 board Artix-7

FPGA.

The script has been generated using Vivado ver. 2017.3.

This directory includes the design files required by the project

(except for the VHDL source code, which is located into VHDL

directory):

1) RV01_selftest_syn.tcl, tcl script creating top-level module project.

2) RV01_artix.xdc, timing and I/O constraint (clock period = 10ns).

Note: the synthesis top-level module is RV01_SELTEST_SYN (from file

RV01_selftest_syn.vhd), which is a wrapper around the core top-level module

RV01_SELFTEST (from file RV01_selftest.vhd) needed to change reset input

active level (the one provided by the bard cpu-reset button is active-low)

and set two of the board LED's to a known, fixed, state (one permantently

on and the other permanently off, as a simple visual confirmation that

the FPGA has been programmed).

Note: tcl script can be run from Vivado shell entering the

following commands to the Tcl Console:

set argv [list "--origin_dir" ]

set argc [llength $argv]

set argv0 RV01_selftest_syn.tcl

source $argv0