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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [s1_top/] [s1_defs.h] - Blame information for rev 114
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fafa1971 |
/*
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114 |
albert.wat |
* S1 Definitions
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fafa1971 |
*
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114 |
albert.wat |
* (C) Copyleft 2007 Fabrizio Fazzino
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fafa1971 |
*
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* LICENSE:
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* This is a Free Hardware Design; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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* The above named program is distributed in the hope that it will
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* be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* DESCRIPTION:
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* Simple constant definitions used by the S1 Core design.
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*/
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`include "t1_defs.h"
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`timescale 1ns/100ps
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fafa1971 |
`define FPGA_SYN
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`define FPGA_SYN_1THREAD
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`define FPGA_SYN_NO_SPU
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fafa1971 |
// Size of the buses
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`define WB_ADDR_WIDTH 64
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`define WB_DATA_WIDTH 64
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// States of the FSM of the bridge
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`define STATE_WAKEUP 4'b0000
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`define STATE_IDLE 4'b0001
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`define STATE_REQUEST_LATCHED 4'b0010
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`define STATE_PACKET_LATCHED 4'b0011
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`define STATE_REQUEST_GRANTED 4'b0100
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`define STATE_ACCESS2_BEGIN 4'b0101
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`define STATE_ACCESS2_END 4'b0110
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`define STATE_ACCESS3_BEGIN 4'b0111
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`define STATE_ACCESS3_END 4'b1000
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`define STATE_ACCESS4_BEGIN 4'b1001
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`define STATE_ACCESS4_END 4'b1010
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`define STATE_PACKET_READY 4'b1011
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// Constants used by the timer of the Reset Controller
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`define TIMER_BITS 16
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`define RESET_CYCLES_1 100
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`define RESET_CYCLES_2 1000
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`define RESET_CYCLES_3 2000
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`define RESET_CYCLES_4 3000
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`define GCLK_CYCLES 900
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