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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [bw_r_rf16x160.v] - Blame information for rev 113

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1 95 fafa1971 
// ========== Copyright Header Begin ==========================================
2 
//
3 
// OpenSPARC T1 Processor File: bw_r_rf16x160.v
4 
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5 
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6 
//
7 
// The above named program is free software; you can redistribute it and/or
8 
// modify it under the terms of the GNU General Public
9 
// License version 2 as published by the Free Software Foundation.
10 
//
11 
// The above named program is distributed in the hope that it will be
12 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 
// General Public License for more details.
15 
//
16 
// You should have received a copy of the GNU General Public
17 
// License along with this work; if not, write to the Free Software
18 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19 
//
20 
// ========== Copyright Header End ============================================
21 
 ////////////////////////////////////////////////////////////////////////
22 
// 16 X 160 R1 W1 RF macro
23 
// REad/Write ports can be accessed in PH1 only.
24 
////////////////////////////////////////////////////////////////////////
25 
 
26 
//FPGA_SYN enables all FPGA related modifications
27 113 albert.wat 
`ifdef FPGA_SYN
28 
`define FPGA_SYN_16x160
29 
`endif
30 95 fafa1971 
 
31 
module bw_r_rf16x160(/*AUTOARG*/
32 
   // Outputs
33 
   dout, so_w, so_r,
34 
   // Inputs
35 
   din, rd_adr, wr_adr, read_en, wr_en, rst_tri_en, word_wen,
36 
   byte_wen, rd_clk, wr_clk, se, si_r, si_w, reset_l, sehold
37 
   );
38 
 
39 
   input [159:0]  din; // data input
40 
   input [3:0]    rd_adr;   // read addr
41 
   input [3:0]     wr_adr;  // write addr
42 
   input          read_en;
43 
   input          wr_en;        //   used in conjunction with
44 
                                //  word_wen and byte_wen
45 
   input          rst_tri_en ; // gates off writes during SCAN.
46 
   input [3:0]    word_wen; // word enables ( if you don't use these
47 
                            // tie them to Vdd )
48 
   input [19:0]    byte_wen;     // byte enables ( if you don't use these
49 
                            // tie them to Vdd )
50 
   input          rd_clk;
51 
   input          wr_clk;
52 
   input          se, si_r, si_w ;
53 
   input          reset_l;
54 
   input          sehold; // hold scan in data.
55 
 
56 
   output [159:0] dout;
57 
   output         so_w;
58 
   output         so_r;
59 
 
60 
 
61 
   // local signals
62 
   reg  [159:0]   wrdata_d1;
63 
 
64 
   reg  [3:0]     rdptr_d1, wrptr_d1;
65 
   reg            ren_d1;
66 
   reg            wr_en_d1;
67 
 
68 
 
69 113 albert.wat 
`ifdef DEFINE_0IN
70 95 fafa1971 
   wire          so;
71 113 albert.wat 
`else
72 
   wire          so;
73 95 fafa1971 
 
74 113 albert.wat 
`ifdef FPGA_SYN_16x160
75 
`else
76 
   reg [159:0] dout;
77 
   // memory array
78 
   reg [159:0]  inq_ary [15:0];
79 
`endif
80 
`endif
81 95 fafa1971 
 
82 
   // internal variable
83 
   integer          i, j;
84 
   reg     [159:0]  temp, data_in, tmp_dout;
85 
   reg     [3:0]    word_wen_d1;
86 
   reg     [3:0]    word_wen_d2;
87 
   reg     [19:0]   byte_wen_d1;
88 
   reg                  rst_tri_en_d1;
89 
 
90 
 
91 
//-------
92 
 
93 
always @ (posedge wr_clk)
94 
begin
95 
  wrdata_d1[159:0]  <= (sehold) ? wrdata_d1[159:0]  : din[159:0];
96 
  wr_en_d1          <= (sehold) ? wr_en_d1          : wr_en;
97 
  word_wen_d1[3:0]  <= (sehold) ? word_wen_d1[3:0]  : word_wen[3:0];
98 
  word_wen_d2[3:0]  <= (sehold) ? word_wen_d2[3:0]  : (word_wen[3:0] &
99 
                                {4{wr_en & ~rst_tri_en}});
100 
  byte_wen_d1[19:0] <= (sehold) ? byte_wen_d1[19:0] : byte_wen[19:0];
101 
  wrptr_d1[3:0]     <= (sehold) ? wrptr_d1[3:0]     : wr_adr[3:0];
102 
 
103 
  rst_tri_en_d1 <= rst_tri_en ; // not a real flop. ONly used as a trigger.
104 
end
105 
//-------
106 
 
107 
 
108 113 albert.wat 
`ifdef DEFINE_0IN
109 
   wire [159:0] bit_en_d1;
110 95 fafa1971 
 
111 113 albert.wat 
  assign bit_en_d1[0]  = word_wen_d1[0] & byte_wen_d1[0] & ~rst_tri_en;
112 
  assign bit_en_d1[1]  = word_wen_d1[1] & byte_wen_d1[0] & ~rst_tri_en;
113 
  assign bit_en_d1[2]  = word_wen_d1[2] & byte_wen_d1[0] & ~rst_tri_en;
114 
  assign bit_en_d1[3]  = word_wen_d1[3] & byte_wen_d1[0] & ~rst_tri_en;
115 
  assign bit_en_d1[4]  = word_wen_d1[0] & byte_wen_d1[0] & ~rst_tri_en;
116 
  assign bit_en_d1[5]  = word_wen_d1[1] & byte_wen_d1[0] & ~rst_tri_en;
117 
  assign bit_en_d1[6]  = word_wen_d1[2] & byte_wen_d1[0] & ~rst_tri_en;
118 
  assign bit_en_d1[7]  = word_wen_d1[3] & byte_wen_d1[0] & ~rst_tri_en;
119 
  assign bit_en_d1[8]  = word_wen_d1[0] & byte_wen_d1[1] & ~rst_tri_en;
120 
  assign bit_en_d1[9]  = word_wen_d1[1] & byte_wen_d1[1] & ~rst_tri_en;
121 
  assign bit_en_d1[10] = word_wen_d1[2] & byte_wen_d1[1] & ~rst_tri_en;
122 
  assign bit_en_d1[11] = word_wen_d1[3] & byte_wen_d1[1] & ~rst_tri_en;
123 
  assign bit_en_d1[12] = word_wen_d1[0] & byte_wen_d1[1] & ~rst_tri_en;
124 
  assign bit_en_d1[13] = word_wen_d1[1] & byte_wen_d1[1] & ~rst_tri_en;
125 
  assign bit_en_d1[14] = word_wen_d1[2] & byte_wen_d1[1] & ~rst_tri_en;
126 
  assign bit_en_d1[15] = word_wen_d1[3] & byte_wen_d1[1] & ~rst_tri_en;
127 
  assign bit_en_d1[16] = word_wen_d1[0] & byte_wen_d1[2] & ~rst_tri_en;
128 
  assign bit_en_d1[17] = word_wen_d1[1] & byte_wen_d1[2] & ~rst_tri_en;
129 
  assign bit_en_d1[18] = word_wen_d1[2] & byte_wen_d1[2] & ~rst_tri_en;
130 
  assign bit_en_d1[19] = word_wen_d1[3] & byte_wen_d1[2] & ~rst_tri_en;
131 
  assign bit_en_d1[20] = word_wen_d1[0] & byte_wen_d1[2] & ~rst_tri_en;
132 
  assign bit_en_d1[21] = word_wen_d1[1] & byte_wen_d1[2] & ~rst_tri_en;
133 
  assign bit_en_d1[22] = word_wen_d1[2] & byte_wen_d1[2] & ~rst_tri_en;
134 
  assign bit_en_d1[23] = word_wen_d1[3] & byte_wen_d1[2] & ~rst_tri_en;
135 
  assign bit_en_d1[24] = word_wen_d1[0] & byte_wen_d1[3] & ~rst_tri_en;
136 
  assign bit_en_d1[25] = word_wen_d1[1] & byte_wen_d1[3] & ~rst_tri_en;
137 
  assign bit_en_d1[26] = word_wen_d1[2] & byte_wen_d1[3] & ~rst_tri_en;
138 
  assign bit_en_d1[27] = word_wen_d1[3] & byte_wen_d1[3] & ~rst_tri_en;
139 
  assign bit_en_d1[28] = word_wen_d1[0] & byte_wen_d1[3] & ~rst_tri_en;
140 
  assign bit_en_d1[29] = word_wen_d1[1] & byte_wen_d1[3] & ~rst_tri_en;
141 
  assign bit_en_d1[30] = word_wen_d1[2] & byte_wen_d1[3] & ~rst_tri_en;
142 
  assign bit_en_d1[31] = word_wen_d1[3] & byte_wen_d1[3] & ~rst_tri_en;
143 
  assign bit_en_d1[32] = word_wen_d1[0] & byte_wen_d1[4] & ~rst_tri_en;
144 
  assign bit_en_d1[33] = word_wen_d1[1] & byte_wen_d1[4] & ~rst_tri_en;
145 
  assign bit_en_d1[34] = word_wen_d1[2] & byte_wen_d1[4] & ~rst_tri_en;
146 
  assign bit_en_d1[35] = word_wen_d1[3] & byte_wen_d1[4] & ~rst_tri_en;
147 
  assign bit_en_d1[36] = word_wen_d1[0] & byte_wen_d1[4] & ~rst_tri_en;
148 
  assign bit_en_d1[37] = word_wen_d1[1] & byte_wen_d1[4] & ~rst_tri_en;
149 
  assign bit_en_d1[38] = word_wen_d1[2] & byte_wen_d1[4] & ~rst_tri_en;
150 
  assign bit_en_d1[39] = word_wen_d1[3] & byte_wen_d1[4] & ~rst_tri_en;
151 
  assign bit_en_d1[40] = word_wen_d1[0] & byte_wen_d1[5] & ~rst_tri_en;
152 
  assign bit_en_d1[41] = word_wen_d1[1] & byte_wen_d1[5] & ~rst_tri_en;
153 
  assign bit_en_d1[42] = word_wen_d1[2] & byte_wen_d1[5] & ~rst_tri_en;
154 
  assign bit_en_d1[43] = word_wen_d1[3] & byte_wen_d1[5] & ~rst_tri_en;
155 
  assign bit_en_d1[44] = word_wen_d1[0] & byte_wen_d1[5] & ~rst_tri_en;
156 
  assign bit_en_d1[45] = word_wen_d1[1] & byte_wen_d1[5] & ~rst_tri_en;
157 
  assign bit_en_d1[46] = word_wen_d1[2] & byte_wen_d1[5] & ~rst_tri_en;
158 
  assign bit_en_d1[47] = word_wen_d1[3] & byte_wen_d1[5] & ~rst_tri_en;
159 
  assign bit_en_d1[48] = word_wen_d1[0] & byte_wen_d1[6] & ~rst_tri_en;
160 
  assign bit_en_d1[49] = word_wen_d1[1] & byte_wen_d1[6] & ~rst_tri_en;
161 
  assign bit_en_d1[50] = word_wen_d1[2] & byte_wen_d1[6] & ~rst_tri_en;
162 
  assign bit_en_d1[51] = word_wen_d1[3] & byte_wen_d1[6] & ~rst_tri_en;
163 
  assign bit_en_d1[52] = word_wen_d1[0] & byte_wen_d1[6] & ~rst_tri_en;
164 
  assign bit_en_d1[53] = word_wen_d1[1] & byte_wen_d1[6] & ~rst_tri_en;
165 
  assign bit_en_d1[54] = word_wen_d1[2] & byte_wen_d1[6] & ~rst_tri_en;
166 
  assign bit_en_d1[55] = word_wen_d1[3] & byte_wen_d1[6] & ~rst_tri_en;
167 
  assign bit_en_d1[56] = word_wen_d1[0] & byte_wen_d1[7] & ~rst_tri_en;
168 
  assign bit_en_d1[57] = word_wen_d1[1] & byte_wen_d1[7] & ~rst_tri_en;
169 
  assign bit_en_d1[58] = word_wen_d1[2] & byte_wen_d1[7] & ~rst_tri_en;
170 
  assign bit_en_d1[59] = word_wen_d1[3] & byte_wen_d1[7] & ~rst_tri_en;
171 
  assign bit_en_d1[60] = word_wen_d1[0] & byte_wen_d1[7] & ~rst_tri_en;
172 
  assign bit_en_d1[61] = word_wen_d1[1] & byte_wen_d1[7] & ~rst_tri_en;
173 
  assign bit_en_d1[62] = word_wen_d1[2] & byte_wen_d1[7] & ~rst_tri_en;
174 
  assign bit_en_d1[63] = word_wen_d1[3] & byte_wen_d1[7] & ~rst_tri_en;
175 
  assign bit_en_d1[64] = word_wen_d1[0] & byte_wen_d1[8] & ~rst_tri_en;
176 
  assign bit_en_d1[65] = word_wen_d1[1] & byte_wen_d1[8] & ~rst_tri_en;
177 
  assign bit_en_d1[66] = word_wen_d1[2] & byte_wen_d1[8] & ~rst_tri_en;
178 
  assign bit_en_d1[67] = word_wen_d1[3] & byte_wen_d1[8] & ~rst_tri_en;
179 
  assign bit_en_d1[68] = word_wen_d1[0] & byte_wen_d1[8] & ~rst_tri_en;
180 
  assign bit_en_d1[69] = word_wen_d1[1] & byte_wen_d1[8] & ~rst_tri_en;
181 
  assign bit_en_d1[70] = word_wen_d1[2] & byte_wen_d1[8] & ~rst_tri_en;
182 
  assign bit_en_d1[71] = word_wen_d1[3] & byte_wen_d1[8] & ~rst_tri_en;
183 
  assign bit_en_d1[72] = word_wen_d1[0] & byte_wen_d1[9] & ~rst_tri_en;
184 
  assign bit_en_d1[73] = word_wen_d1[1] & byte_wen_d1[9] & ~rst_tri_en;
185 
  assign bit_en_d1[74] = word_wen_d1[2] & byte_wen_d1[9] & ~rst_tri_en;
186 
  assign bit_en_d1[75] = word_wen_d1[3] & byte_wen_d1[9] & ~rst_tri_en;
187 
  assign bit_en_d1[76] = word_wen_d1[0] & byte_wen_d1[9] & ~rst_tri_en;
188 
  assign bit_en_d1[77] = word_wen_d1[1] & byte_wen_d1[9] & ~rst_tri_en;
189 
  assign bit_en_d1[78] = word_wen_d1[2] & byte_wen_d1[9] & ~rst_tri_en;
190 
  assign bit_en_d1[79] = word_wen_d1[3] & byte_wen_d1[9] & ~rst_tri_en;
191 
  assign bit_en_d1[80] = word_wen_d1[0] & byte_wen_d1[10] & ~rst_tri_en;
192 
  assign bit_en_d1[81] = word_wen_d1[1] & byte_wen_d1[10] & ~rst_tri_en;
193 
  assign bit_en_d1[82] = word_wen_d1[2] & byte_wen_d1[10] & ~rst_tri_en;
194 
  assign bit_en_d1[83] = word_wen_d1[3] & byte_wen_d1[10] & ~rst_tri_en;
195 
  assign bit_en_d1[84] = word_wen_d1[0] & byte_wen_d1[10] & ~rst_tri_en;
196 
  assign bit_en_d1[85] = word_wen_d1[1] & byte_wen_d1[10] & ~rst_tri_en;
197 
  assign bit_en_d1[86] = word_wen_d1[2] & byte_wen_d1[10] & ~rst_tri_en;
198 
  assign bit_en_d1[87] = word_wen_d1[3] & byte_wen_d1[10] & ~rst_tri_en;
199 
  assign bit_en_d1[88] = word_wen_d1[0] & byte_wen_d1[11] & ~rst_tri_en;
200 
  assign bit_en_d1[89] = word_wen_d1[1] & byte_wen_d1[11] & ~rst_tri_en;
201 
  assign bit_en_d1[90] = word_wen_d1[2] & byte_wen_d1[11] & ~rst_tri_en;
202 
  assign bit_en_d1[91] = word_wen_d1[3] & byte_wen_d1[11] & ~rst_tri_en;
203 
  assign bit_en_d1[92] = word_wen_d1[0] & byte_wen_d1[11] & ~rst_tri_en;
204 
  assign bit_en_d1[93] = word_wen_d1[1] & byte_wen_d1[11] & ~rst_tri_en;
205 
  assign bit_en_d1[94] = word_wen_d1[2] & byte_wen_d1[11] & ~rst_tri_en;
206 
  assign bit_en_d1[95] = word_wen_d1[3] & byte_wen_d1[11] & ~rst_tri_en;
207 
  assign bit_en_d1[96] = word_wen_d1[0] & byte_wen_d1[12] & ~rst_tri_en;
208 
  assign bit_en_d1[97] = word_wen_d1[1] & byte_wen_d1[12] & ~rst_tri_en;
209 
  assign bit_en_d1[98] = word_wen_d1[2] & byte_wen_d1[12] & ~rst_tri_en;
210 
  assign bit_en_d1[99] = word_wen_d1[3] & byte_wen_d1[12] & ~rst_tri_en;
211 
  assign bit_en_d1[100] = word_wen_d1[0] & byte_wen_d1[12] & ~rst_tri_en;
212 
  assign bit_en_d1[101] = word_wen_d1[1] & byte_wen_d1[12] & ~rst_tri_en;
213 
  assign bit_en_d1[102] = word_wen_d1[2] & byte_wen_d1[12] & ~rst_tri_en;
214 
  assign bit_en_d1[103] = word_wen_d1[3] & byte_wen_d1[12] & ~rst_tri_en;
215 
  assign bit_en_d1[104] = word_wen_d1[0] & byte_wen_d1[13] & ~rst_tri_en;
216 
  assign bit_en_d1[105] = word_wen_d1[1] & byte_wen_d1[13] & ~rst_tri_en;
217 
  assign bit_en_d1[106] = word_wen_d1[2] & byte_wen_d1[13] & ~rst_tri_en;
218 
  assign bit_en_d1[107] = word_wen_d1[3] & byte_wen_d1[13] & ~rst_tri_en;
219 
  assign bit_en_d1[108] = word_wen_d1[0] & byte_wen_d1[13] & ~rst_tri_en;
220 
  assign bit_en_d1[109] = word_wen_d1[1] & byte_wen_d1[13] & ~rst_tri_en;
221 
  assign bit_en_d1[110] = word_wen_d1[2] & byte_wen_d1[13] & ~rst_tri_en;
222 
  assign bit_en_d1[111] = word_wen_d1[3] & byte_wen_d1[13] & ~rst_tri_en;
223 
  assign bit_en_d1[112] = word_wen_d1[0] & byte_wen_d1[14] & ~rst_tri_en;
224 
  assign bit_en_d1[113] = word_wen_d1[1] & byte_wen_d1[14] & ~rst_tri_en;
225 
  assign bit_en_d1[114] = word_wen_d1[2] & byte_wen_d1[14] & ~rst_tri_en;
226 
  assign bit_en_d1[115] = word_wen_d1[3] & byte_wen_d1[14] & ~rst_tri_en;
227 
  assign bit_en_d1[116] = word_wen_d1[0] & byte_wen_d1[14] & ~rst_tri_en;
228 
  assign bit_en_d1[117] = word_wen_d1[1] & byte_wen_d1[14] & ~rst_tri_en;
229 
  assign bit_en_d1[118] = word_wen_d1[2] & byte_wen_d1[14] & ~rst_tri_en;
230 
  assign bit_en_d1[119] = word_wen_d1[3] & byte_wen_d1[14] & ~rst_tri_en;
231 
  assign bit_en_d1[120] = word_wen_d1[0] & byte_wen_d1[15] & ~rst_tri_en;
232 
  assign bit_en_d1[121] = word_wen_d1[1] & byte_wen_d1[15] & ~rst_tri_en;
233 
  assign bit_en_d1[122] = word_wen_d1[2] & byte_wen_d1[15] & ~rst_tri_en;
234 
  assign bit_en_d1[123] = word_wen_d1[3] & byte_wen_d1[15] & ~rst_tri_en;
235 
  assign bit_en_d1[124] = word_wen_d1[0] & byte_wen_d1[15] & ~rst_tri_en;
236 
  assign bit_en_d1[125] = word_wen_d1[1] & byte_wen_d1[15] & ~rst_tri_en;
237 
  assign bit_en_d1[126] = word_wen_d1[2] & byte_wen_d1[15] & ~rst_tri_en;
238 
  assign bit_en_d1[127] = word_wen_d1[3] & byte_wen_d1[15] & ~rst_tri_en;
239 
  assign bit_en_d1[128] = word_wen_d1[0] & byte_wen_d1[16] & ~rst_tri_en;
240 
  assign bit_en_d1[129] = word_wen_d1[1] & byte_wen_d1[16] & ~rst_tri_en;
241 
  assign bit_en_d1[130] = word_wen_d1[2] & byte_wen_d1[16] & ~rst_tri_en;
242 
  assign bit_en_d1[131] = word_wen_d1[3] & byte_wen_d1[16] & ~rst_tri_en;
243 
  assign bit_en_d1[132] = word_wen_d1[0] & byte_wen_d1[16] & ~rst_tri_en;
244 
  assign bit_en_d1[133] = word_wen_d1[1] & byte_wen_d1[16] & ~rst_tri_en;
245 
  assign bit_en_d1[134] = word_wen_d1[2] & byte_wen_d1[16] & ~rst_tri_en;
246 
  assign bit_en_d1[135] = word_wen_d1[3] & byte_wen_d1[16] & ~rst_tri_en;
247 
  assign bit_en_d1[136] = word_wen_d1[0] & byte_wen_d1[17] & ~rst_tri_en;
248 
  assign bit_en_d1[137] = word_wen_d1[1] & byte_wen_d1[17] & ~rst_tri_en;
249 
  assign bit_en_d1[138] = word_wen_d1[2] & byte_wen_d1[17] & ~rst_tri_en;
250 
  assign bit_en_d1[139] = word_wen_d1[3] & byte_wen_d1[17] & ~rst_tri_en;
251 
  assign bit_en_d1[140] = word_wen_d1[0] & byte_wen_d1[17] & ~rst_tri_en;
252 
  assign bit_en_d1[141] = word_wen_d1[1] & byte_wen_d1[17] & ~rst_tri_en;
253 
  assign bit_en_d1[142] = word_wen_d1[2] & byte_wen_d1[17] & ~rst_tri_en;
254 
  assign bit_en_d1[143] = word_wen_d1[3] & byte_wen_d1[17] & ~rst_tri_en;
255 
  assign bit_en_d1[144] = word_wen_d1[0] & byte_wen_d1[18] & ~rst_tri_en;
256 
  assign bit_en_d1[145] = word_wen_d1[1] & byte_wen_d1[18] & ~rst_tri_en;
257 
  assign bit_en_d1[146] = word_wen_d1[2] & byte_wen_d1[18] & ~rst_tri_en;
258 
  assign bit_en_d1[147] = word_wen_d1[3] & byte_wen_d1[18] & ~rst_tri_en;
259 
  assign bit_en_d1[148] = word_wen_d1[0] & byte_wen_d1[18] & ~rst_tri_en;
260 
  assign bit_en_d1[149] = word_wen_d1[1] & byte_wen_d1[18] & ~rst_tri_en;
261 
  assign bit_en_d1[150] = word_wen_d1[2] & byte_wen_d1[18] & ~rst_tri_en;
262 
  assign bit_en_d1[151] = word_wen_d1[3] & byte_wen_d1[18] & ~rst_tri_en;
263 
  assign bit_en_d1[152] = word_wen_d1[0] & byte_wen_d1[19] & ~rst_tri_en;
264 
  assign bit_en_d1[153] = word_wen_d1[1] & byte_wen_d1[19] & ~rst_tri_en;
265 
  assign bit_en_d1[154] = word_wen_d1[2] & byte_wen_d1[19] & ~rst_tri_en;
266 
  assign bit_en_d1[155] = word_wen_d1[3] & byte_wen_d1[19] & ~rst_tri_en;
267 
  assign bit_en_d1[156] = word_wen_d1[0] & byte_wen_d1[19] & ~rst_tri_en;
268 
  assign bit_en_d1[157] = word_wen_d1[1] & byte_wen_d1[19] & ~rst_tri_en;
269 
  assign bit_en_d1[158] = word_wen_d1[2] & byte_wen_d1[19] & ~rst_tri_en;
270 
  assign bit_en_d1[159] = word_wen_d1[3] & byte_wen_d1[19] & ~rst_tri_en;
271 
`else
272 95 fafa1971 
 
273 113 albert.wat 
`endif
274 95 fafa1971 
//-------
275 
 
276 
always @ (posedge rd_clk)
277 
begin
278 
  ren_d1        <= (sehold) ? ren_d1        : read_en;
279 
  rdptr_d1[3:0] <= (sehold) ? rdptr_d1[3:0] : rd_adr[3:0];
280 
end
281 
//-------
282 
 
283 
 
284 113 albert.wat 
`ifdef DEFINE_0IN
285 
rf16x160 rf16x160 ( .rdclk(rd_clk), .wrclk(~wr_clk), .radr(rdptr_d1), .wadr(wrptr_d1), .ren(ren_d1),
286 
                        .we(wr_en_d1), .wm(bit_en_d1), .din(wrdata_d1), .dout(dout) );
287 
`else
288 95 fafa1971 
 
289 113 albert.wat 
`ifdef FPGA_SYN_16x160
290 95 fafa1971 
 
291 
bw_r_rf16x2 arr0 (
292 
        .word_wen(word_wen_d2),
293 
        .wen(byte_wen_d1[ 0]),
294 
        .ren(ren_d1),
295 
        .wr_addr(wrptr_d1),
296 
        .rd_addr(rdptr_d1),
297 
        .wr_data(wrdata_d1[  7:  0]),
298 
        .rd_data(dout[  7:  0]),
299 
        .clk(wr_clk),
300 
        .rd_clk(rd_clk),
301 
        .reset_l(reset_l));
302 
 
303 
bw_r_rf16x2 arr1 (
304 
        .word_wen(word_wen_d2),
305 
        .wen(byte_wen_d1[ 1]),
306 
        .ren(ren_d1),
307 
        .wr_addr(wrptr_d1),
308 
        .rd_addr(rdptr_d1),
309 
        .wr_data(wrdata_d1[ 15:  8]),
310 
        .rd_data(dout[ 15:  8]),
311 
        .clk(wr_clk),
312 
        .rd_clk(rd_clk),
313 
        .reset_l(reset_l));
314 
 
315 
bw_r_rf16x2 arr2 (
316 
        .word_wen(word_wen_d2),
317 
        .wen(byte_wen_d1[ 2]),
318 
        .ren(ren_d1),
319 
        .wr_addr(wrptr_d1),
320 
        .rd_addr(rdptr_d1),
321 
        .wr_data(wrdata_d1[ 23: 16]),
322 
        .rd_data(dout[ 23: 16]),
323 
        .clk(wr_clk),
324 
        .rd_clk(rd_clk),
325 
        .reset_l(reset_l));
326 
 
327 
bw_r_rf16x2 arr3 (
328 
        .word_wen(word_wen_d2),
329 
        .wen(byte_wen_d1[ 3]),
330 
        .ren(ren_d1),
331 
        .wr_addr(wrptr_d1),
332 
        .rd_addr(rdptr_d1),
333 
        .wr_data(wrdata_d1[ 31: 24]),
334 
        .rd_data(dout[ 31: 24]),
335 
        .clk(wr_clk),
336 
        .rd_clk(rd_clk),
337 
        .reset_l(reset_l));
338 
 
339 
bw_r_rf16x2 arr4 (
340 
        .word_wen(word_wen_d2),
341 
        .wen(byte_wen_d1[ 4]),
342 
        .ren(ren_d1),
343 
        .wr_addr(wrptr_d1),
344 
        .rd_addr(rdptr_d1),
345 
        .wr_data(wrdata_d1[ 39: 32]),
346 
        .rd_data(dout[ 39: 32]),
347 
        .clk(wr_clk),
348 
        .rd_clk(rd_clk),
349 
        .reset_l(reset_l));
350 
 
351 
bw_r_rf16x2 arr5 (
352 
        .word_wen(word_wen_d2),
353 
        .wen(byte_wen_d1[ 5]),
354 
        .ren(ren_d1),
355 
        .wr_addr(wrptr_d1),
356 
        .rd_addr(rdptr_d1),
357 
        .wr_data(wrdata_d1[ 47: 40]),
358 
        .rd_data(dout[ 47: 40]),
359 
        .clk(wr_clk),
360 
        .rd_clk(rd_clk),
361 
        .reset_l(reset_l));
362 
 
363 
bw_r_rf16x2 arr6 (
364 
        .word_wen(word_wen_d2),
365 
        .wen(byte_wen_d1[ 6]),
366 
        .ren(ren_d1),
367 
        .wr_addr(wrptr_d1),
368 
        .rd_addr(rdptr_d1),
369 
        .wr_data(wrdata_d1[ 55: 48]),
370 
        .rd_data(dout[ 55: 48]),
371 
        .clk(wr_clk),
372 
        .rd_clk(rd_clk),
373 
        .reset_l(reset_l));
374 
 
375 
bw_r_rf16x2 arr7 (
376 
        .word_wen(word_wen_d2),
377 
        .wen(byte_wen_d1[ 7]),
378 
        .ren(ren_d1),
379 
        .wr_addr(wrptr_d1),
380 
        .rd_addr(rdptr_d1),
381 
        .wr_data(wrdata_d1[ 63: 56]),
382 
        .rd_data(dout[ 63: 56]),
383 
        .clk(wr_clk),
384 
        .rd_clk(rd_clk),
385 
        .reset_l(reset_l));
386 
 
387 
bw_r_rf16x2 arr8 (
388 
        .word_wen(word_wen_d2),
389 
        .wen(byte_wen_d1[ 8]),
390 
        .ren(ren_d1),
391 
        .wr_addr(wrptr_d1),
392 
        .rd_addr(rdptr_d1),
393 
        .wr_data(wrdata_d1[ 71: 64]),
394 
        .rd_data(dout[ 71: 64]),
395 
        .clk(wr_clk),
396 
        .rd_clk(rd_clk),
397 
        .reset_l(reset_l));
398 
 
399 
bw_r_rf16x2 arr9 (
400 
        .word_wen(word_wen_d2),
401 
        .wen(byte_wen_d1[ 9]),
402 
        .ren(ren_d1),
403 
        .wr_addr(wrptr_d1),
404 
        .rd_addr(rdptr_d1),
405 
        .wr_data(wrdata_d1[ 79: 72]),
406 
        .rd_data(dout[ 79: 72]),
407 
        .clk(wr_clk),
408 
        .rd_clk(rd_clk),
409 
        .reset_l(reset_l));
410 
 
411 
bw_r_rf16x2 arr10(
412 
        .word_wen(word_wen_d2),
413 
        .wen(byte_wen_d1[10]),
414 
        .ren(ren_d1),
415 
        .wr_addr(wrptr_d1),
416 
        .rd_addr(rdptr_d1),
417 
        .wr_data(wrdata_d1[ 87: 80]),
418 
        .rd_data(dout[ 87: 80]),
419 
        .clk(wr_clk),
420 
        .rd_clk(rd_clk),
421 
        .reset_l(reset_l));
422 
 
423 
bw_r_rf16x2 arr11(
424 
        .word_wen(word_wen_d2),
425 
        .wen(byte_wen_d1[11]),
426 
        .ren(ren_d1),
427 
        .wr_addr(wrptr_d1),
428 
        .rd_addr(rdptr_d1),
429 
        .wr_data(wrdata_d1[ 95: 88]),
430 
        .rd_data(dout[ 95: 88]),
431 
        .clk(wr_clk),
432 
        .rd_clk(rd_clk),
433 
        .reset_l(reset_l));
434 
 
435 
bw_r_rf16x2 arr12(
436 
        .word_wen(word_wen_d2),
437 
        .wen(byte_wen_d1[12]),
438 
        .ren(ren_d1),
439 
        .wr_addr(wrptr_d1),
440 
        .rd_addr(rdptr_d1),
441 
        .wr_data(wrdata_d1[103: 96]),
442 
        .rd_data(dout[103: 96]),
443 
        .clk(wr_clk),
444 
        .rd_clk(rd_clk),
445 
        .reset_l(reset_l));
446 
 
447 
bw_r_rf16x2 arr13(
448 
        .word_wen(word_wen_d2),
449 
        .wen(byte_wen_d1[13]),
450 
        .ren(ren_d1),
451 
        .wr_addr(wrptr_d1),
452 
        .rd_addr(rdptr_d1),
453 
        .wr_data(wrdata_d1[111:104]),
454 
        .rd_data(dout[111:104]),
455 
        .clk(wr_clk),
456 
        .rd_clk(rd_clk),
457 
        .reset_l(reset_l));
458 
 
459 
bw_r_rf16x2 arr14(
460 
        .word_wen(word_wen_d2),
461 
        .wen(byte_wen_d1[14]),
462 
        .ren(ren_d1),
463 
        .wr_addr(wrptr_d1),
464 
        .rd_addr(rdptr_d1),
465 
        .wr_data(wrdata_d1[119:112]),
466 
        .rd_data(dout[119:112]),
467 
        .clk(wr_clk),
468 
        .rd_clk(rd_clk),
469 
        .reset_l(reset_l));
470 
 
471 
bw_r_rf16x2 arr15(
472 
        .word_wen(word_wen_d2),
473 
        .wen(byte_wen_d1[15]),
474 
        .ren(ren_d1),
475 
        .wr_addr(wrptr_d1),
476 
        .rd_addr(rdptr_d1),
477 
        .wr_data(wrdata_d1[127:120]),
478 
        .rd_data(dout[127:120]),
479 
        .clk(wr_clk),
480 
        .rd_clk(rd_clk),
481 
        .reset_l(reset_l));
482 
 
483 
bw_r_rf16x2 arr16(
484 
        .word_wen(word_wen_d2),
485 
        .wen(byte_wen_d1[16]),
486 
        .ren(ren_d1),
487 
        .wr_addr(wrptr_d1),
488 
        .rd_addr(rdptr_d1),
489 
        .wr_data(wrdata_d1[135:128]),
490 
        .rd_data(dout[135:128]),
491 
        .clk(wr_clk),
492 
        .rd_clk(rd_clk),
493 
        .reset_l(reset_l));
494 
 
495 
bw_r_rf16x2 arr17(
496 
        .word_wen(word_wen_d2),
497 
        .wen(byte_wen_d1[17]),
498 
        .ren(ren_d1),
499 
        .wr_addr(wrptr_d1),
500 
        .rd_addr(rdptr_d1),
501 
        .wr_data(wrdata_d1[143:136]),
502 
        .rd_data(dout[143:136]),
503 
        .clk(wr_clk),
504 
        .rd_clk(rd_clk),
505 
        .reset_l(reset_l));
506 
 
507 
bw_r_rf16x2 arr18(
508 
        .word_wen(word_wen_d2),
509 
        .wen(byte_wen_d1[18]),
510 
        .ren(ren_d1),
511 
        .wr_addr(wrptr_d1),
512 
        .rd_addr(rdptr_d1),
513 
        .wr_data(wrdata_d1[151:144]),
514 
        .rd_data(dout[151:144]),
515 
        .clk(wr_clk),
516 
        .rd_clk(rd_clk),
517 
        .reset_l(reset_l));
518 
 
519 
bw_r_rf16x2 arr19(
520 
        .word_wen(word_wen_d2),
521 
        .wen(byte_wen_d1[19]),
522 
        .ren(ren_d1),
523 
        .wr_addr(wrptr_d1),
524 
        .rd_addr(rdptr_d1),
525 
        .wr_data(wrdata_d1[159:152]),
526 
        .rd_data(dout[159:152]),
527 
        .clk(wr_clk),
528 
        .rd_clk(rd_clk),
529 
        .reset_l(reset_l));
530 
 
531 
 
532 113 albert.wat 
`else
533 
//
534 
// Read Operation
535 
//
536 95 fafa1971 
 
537 113 albert.wat 
  always @(/*AUTOSENSE*/ /*memory or*/ byte_wen_d1 or rdptr_d1
538 
           or ren_d1 or reset_l or rst_tri_en_d1 or word_wen_d1
539 
           or wr_en_d1 or wrptr_d1)
540 
    begin
541 
      if (reset_l)
542 
        begin
543 
          if (ren_d1==1'b1)
544 
            begin
545 
            // Checking for Xs on the rd pointer input when read is enabled
546 95 fafa1971 
 
547 113 albert.wat 
// synopsys translate_off
548 95 fafa1971 
 
549 113 albert.wat 
`ifdef INNO_MUXEX
550 
`else
551 
              if (rdptr_d1 == 4'bx)
552 
                begin
553 
                  $error("rf_error"," read pointer error %h ", rdptr_d1[3:0]);
554 
                end
555 
`endif
556 95 fafa1971 
 
557 113 albert.wat 
// synopsys translate_on
558 95 fafa1971 
 
559 113 albert.wat 
              tmp_dout = inq_ary[rdptr_d1] ;
560 
              j = 0;
561 95 fafa1971 
 
562 113 albert.wat 
              for (i=0; i<= 159; i=i+8)
563 
                begin
564 
                  if (rdptr_d1 == wrptr_d1)
565 
                    begin
566 
                      //dout[i]   = (wr_en_d1 & bit_en_d1[i]) ? 1'bx : tmp_dout[i];
567 95 fafa1971 
 
568 113 albert.wat 
                      dout[i]   = (wr_en_d1 & word_wen_d1[0] & byte_wen_d1[j] & ~rst_tri_en) ?
569 
                                      1'bx : tmp_dout[i] ;
570 
                      dout[i+1] = (wr_en_d1 & word_wen_d1[1] & byte_wen_d1[j] & ~rst_tri_en) ?
571 
                                      1'bx : tmp_dout[i+1] ;
572 
                      dout[i+2] = (wr_en_d1 & word_wen_d1[2] & byte_wen_d1[j] & ~rst_tri_en) ?
573 
                                      1'bx : tmp_dout[i+2] ;
574 
                      dout[i+3] = (wr_en_d1 & word_wen_d1[3] & byte_wen_d1[j] & ~rst_tri_en) ?
575 
                                      1'bx : tmp_dout[i+3] ;
576 
                      dout[i+4] = (wr_en_d1 & word_wen_d1[0] & byte_wen_d1[j] & ~rst_tri_en) ?
577 
                                      1'bx : tmp_dout[i+4] ;
578 
                      dout[i+5] = (wr_en_d1 & word_wen_d1[1] & byte_wen_d1[j] & ~rst_tri_en) ?
579 
                                      1'bx : tmp_dout[i+5] ;
580 
                      dout[i+6] = (wr_en_d1 & word_wen_d1[2] & byte_wen_d1[j] & ~rst_tri_en) ?
581 
                                      1'bx : tmp_dout[i+6] ;
582 
                      dout[i+7] = (wr_en_d1 & word_wen_d1[3] & byte_wen_d1[j] & ~rst_tri_en) ?
583 
                                      1'bx : tmp_dout[i+7] ;
584 
                      j = j+1;
585 
                    end
586 
                  else
587 
                    begin
588 
                      //dout[i]   = tmp_dout[i] ;
589 
                      dout[i]   = tmp_dout[i] ;
590 
                      dout[i+1] = tmp_dout[i+1] ;
591 
                      dout[i+2] = tmp_dout[i+2] ;
592 
                      dout[i+3] = tmp_dout[i+3] ;
593 
                      dout[i+4] = tmp_dout[i+4] ;
594 
                      dout[i+5] = tmp_dout[i+5] ;
595 
                      dout[i+6] = tmp_dout[i+6] ;
596 
                      dout[i+7] = tmp_dout[i+7] ;
597 
                    end
598 
                end
599 
            end
600 
        end
601 
      else dout[159:0] = 160'b0 ;
602 
  end // always @ (...
603 95 fafa1971 
 
604 
 
605 
 
606 113 albert.wat 
//
607 
// Write Operation
608 
//
609 
  always @ (/*AUTOSENSE*/byte_wen_d1 or reset_l or rst_tri_en_d1
610 
            or word_wen_d1 or wr_en_d1 or wrdata_d1 or wrptr_d1)
611 
    begin
612 
      if (reset_l)
613 
        begin
614 
        // Checking for Xs on bit write enables that are derived from
615 
        // the word_enables and wr enable input.
616 95 fafa1971 
 
617 113 albert.wat 
// synopsys translate_off
618 95 fafa1971 
 
619 113 albert.wat 
`ifdef INNO_MUXEX
620 
`else
621 
          if (wr_en_d1 == 1'bx)
622 
            begin
623 
              $error("rf_error"," write enable error %h ", wr_en_d1);
624 
            end
625 
          if (word_wen_d1 == 4'bx)
626 
            begin
627 
              $error("rf_error"," word enable error %h ", word_wen_d1[3:0]);
628 
            end
629 
          if (byte_wen_d1 == 20'bx)
630 
            begin
631 
              $error("rf_error"," byte enable error %h ", byte_wen_d1[19:0]);
632 
            end
633 
`endif
634 95 fafa1971 
 
635 113 albert.wat 
// synopsys translate_on
636 95 fafa1971 
 
637 113 albert.wat 
          if (wr_en_d1 & ~rst_tri_en)
638 
            begin
639 95 fafa1971 
 
640 113 albert.wat 
// synopsys translate_off
641 95 fafa1971 
 
642 113 albert.wat 
`ifdef INNO_MUXEX
643 
`else
644 
              if (wrptr_d1 == 4'bx)
645 
                begin
646 
                  $error("rf_error"," write pointer error %h ", wrptr_d1[3:0]);
647 
                end
648 
`endif
649 95 fafa1971 
 
650 113 albert.wat 
// synopsys translate_on
651 95 fafa1971 
 
652 113 albert.wat 
              temp = inq_ary[wrptr_d1];
653 
              j = 0;
654 95 fafa1971 
 
655 113 albert.wat 
              for (i=0; i<=159; i=i+8)
656 
                begin
657 
                  //data_in[i] = (bit_en_d1[i]) ? wrdata_d1[i] : temp[i] ;
658 
                  data_in[i]   = (wr_en_d1 & word_wen_d1[0] & byte_wen_d1[j] & ~rst_tri_en) ?
659 
                                   wrdata_d1[i]   : temp[i] ;
660 
                  data_in[i+1] = (wr_en_d1 & word_wen_d1[1] & byte_wen_d1[j] & ~rst_tri_en) ?
661 
                                   wrdata_d1[i+1] : temp[i+1] ;
662 
                  data_in[i+2] = (wr_en_d1 & word_wen_d1[2] & byte_wen_d1[j] & ~rst_tri_en) ?
663 
                                   wrdata_d1[i+2] : temp[i+2] ;
664 
                  data_in[i+3] = (wr_en_d1 & word_wen_d1[3] & byte_wen_d1[j] & ~rst_tri_en) ?
665 
                                   wrdata_d1[i+3] : temp[i+3] ;
666 
                  data_in[i+4] = (wr_en_d1 & word_wen_d1[0] & byte_wen_d1[j] & ~rst_tri_en) ?
667 
                                   wrdata_d1[i+4] : temp[i+4] ;
668 
                  data_in[i+5] = (wr_en_d1 & word_wen_d1[1] & byte_wen_d1[j] & ~rst_tri_en) ?
669 
                                   wrdata_d1[i+5] : temp[i+5] ;
670 
                  data_in[i+6] = (wr_en_d1 & word_wen_d1[2] & byte_wen_d1[j] & ~rst_tri_en) ?
671 
                                   wrdata_d1[i+6] : temp[i+6] ;
672 
                  data_in[i+7] = (wr_en_d1 & word_wen_d1[3] & byte_wen_d1[j] & ~rst_tri_en) ?
673 
                                   wrdata_d1[i+7] : temp[i+7] ;
674 
                  j = j+1;
675 
                end
676 
              inq_ary[wrptr_d1] = data_in ;
677 
            end
678 
        end
679 
    end // always @ (...
680 95 fafa1971 
 
681 113 albert.wat 
`endif
682 
`endif
683 95 fafa1971 
 
684 
endmodule // rf_16x160
685 
 
686 113 albert.wat 
`ifdef FPGA_SYN_16x160
687 95 fafa1971 
 
688 
module bw_r_rf16x2(word_wen, wen, ren, wr_addr, rd_addr, wr_data,
689 
        rd_data, clk, rd_clk, reset_l);
690 
  input [3:0] word_wen;
691 
  input       wen;
692 
  input       ren;
693 
  input [3:0] wr_addr;
694 
  input [3:0] rd_addr;
695 
  input [7:0] wr_data;
696 
  output [7:0] rd_data;
697 
  input clk;
698 
  input rd_clk;
699 
  input reset_l;
700 
 
701 
  reg   [7:0] rd_data_temp;
702 
 
703 
  reg [1:0] inq_ary0[15:0];
704 
  reg [1:0] inq_ary1[15:0];
705 
  reg [1:0] inq_ary2[15:0];
706 
  reg [1:0] inq_ary3[15:0];
707 
 
708 
  always @(posedge clk) begin
709 
    if(reset_l & wen & word_wen[0])
710 
      inq_ary0[wr_addr] = {wr_data[4],wr_data[0]};
711 
    if(reset_l & wen & word_wen[1])
712 
      inq_ary1[wr_addr] = {wr_data[5],wr_data[1]};
713 
    if(reset_l & wen & word_wen[2])
714 
      inq_ary2[wr_addr] = {wr_data[6],wr_data[2]};
715 
    if(reset_l & wen & word_wen[3])
716 
      inq_ary3[wr_addr] = {wr_data[7],wr_data[3]};
717 
  end
718 
 
719 
  always @(negedge rd_clk) begin
720 
    if (~reset_l) begin
721 
      rd_data_temp = 8'b0;
722 
    end else if(ren == 1'b1) begin
723 
        rd_data_temp = {inq_ary3[rd_addr], inq_ary2[rd_addr], inq_ary1[rd_addr], inq_ary0[rd_addr]};
724 
    end
725 
  end
726 
 
727 
  assign rd_data = {rd_data_temp[7], rd_data_temp[5], rd_data_temp[3],
728 
                rd_data_temp[1], rd_data_temp[6], rd_data_temp[4],
729 
                rd_data_temp[2], rd_data_temp[0]};
730 
 
731 
endmodule
732 113 albert.wat 
`endif
733 95 fafa1971 
 
734 
 

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