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// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T1 Processor File: sparc_ifu_thrfsm.v
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================
`ifdef SIMPLY_RISC_TWEAKS
`define SIMPLY_RISC_SCANIN .si(0)
`else
`define SIMPLY_RISC_SCANIN .si()
`endif
////////////////////////////////////////////////////////////////////////
/*
//  Module Name: sparc_ifu_swlthrfsm
//  Description:
//  The switch logithrfsm contains the thread state machine.
*/
 
`include "ifu.h"
 
module sparc_ifu_thrfsm(/*AUTOARG*/
   // Outputs
   so, thr_state,
   // Inputs
   completion, schedule, spec_ld, ldhit, stall, int_activate,
   start_thread, thaw_thread, nuke_thread, rst_thread, switch_out,
   halt_thread, sw_cond, clk, se, si, reset
   );
 
   // thread specific input
   input  completion,   // the op this thread was waiting for is complete
                schedule,     // this thread was just switched in
                spec_ld,      // speculative switch in
                ldhit,        // speculation was correct
                stall,        // stall thread for ldmiss, imiss or trap
                int_activate, // activate this thread
          halt_thread,
                start_thread,    // wake up this thread from dead state
                nuke_thread,
          thaw_thread,
                rst_thread;      // reset this thread
 
   // common inputs
   input  switch_out,   // this thread was just switched out
                sw_cond;        // wait until completion signal is received
 
   input       clk, se, si, reset;
 
   output      so;
 
   output [4:0] thr_state;
 
   // local signals
   reg [4:0]    next_state;
 
   //
   // Code Begins Here
   //
 
//   assign       spec_rdy     = thr_state[`TCR_READY];
 
   always @ (/*AUTOSENSE*/ completion
             or halt_thread or int_activate or ldhit or nuke_thread
             or rst_thread or schedule or spec_ld or stall
             or start_thread or sw_cond or switch_out or thaw_thread
             or thr_state)
     begin
              case (thr_state[4:0])
          `THRFSM_IDLE:  // 5'b00000
                  begin
                     if (rst_thread | thaw_thread)
                             next_state = `THRFSM_WAIT;
                     else if (start_thread)
                             next_state = `THRFSM_RDY;
                     else  // all other interrupts ignored
                             next_state = thr_state[4:0];
                  end
 
                `THRFSM_HALT:  // 5'b00010
                  begin
                     if (nuke_thread)
                             next_state = `THRFSM_IDLE;
                     else if (rst_thread | thaw_thread)
                             next_state = `THRFSM_WAIT;
                     else if (int_activate | start_thread)
                             next_state = `THRFSM_RDY;
                     else
                             next_state = thr_state[4:0];
                  end
 
                `THRFSM_RDY:       // 5'b11001
                  begin
                     if (stall)
                             // trap also kills inst_s2 and nir
                             // Ldmiss should not happen in this state
                             next_state = `THRFSM_WAIT;
                     else if (schedule)
                             next_state = `THRFSM_RUN;
                     else
                             next_state = thr_state[4:0];
                  end // case: `THRFSM_RDY
 
                `THRFSM_RUN:       // 5'b00101
                  begin
                     if (stall | sw_cond)
                             // trap also kills inst_s2 and nir
                             // ldmiss should not happen in this state           
                             next_state = `THRFSM_WAIT;
                     else if (switch_out)
                       // on an interrupt or thread stall, the fcl has to
                       // switch out the thread and inform the fsm 
                             next_state = `THRFSM_RDY;
                     else
                             next_state = thr_state[4:0];
                  end // case: `THRFSM_RUN
 
                `THRFSM_WAIT:       // 5'b00001
                  begin
                     if (nuke_thread)
                             next_state = `THRFSM_IDLE;
                     else if (halt_thread) // exclusive with above
                             next_state = `THRFSM_HALT;
                     else if (stall) // excl. with above
                             next_state = `THRFSM_WAIT;
                     else if (spec_ld) // exclusive with above
                             next_state = `THRFSM_SPEC_RDY;
                     else if (completion & ~halt_thread)
                             next_state = `THRFSM_RDY;
                     else
                             next_state = thr_state[4:0];
                  end // case: `THRFSM_WAIT
 
                `THRFSM_SPEC_RDY:       // 5'b10011
                  begin
                     if (stall)
                             next_state = `THRFSM_WAIT;
                     else if (schedule & ~ldhit) // exclusive
                             next_state = `THRFSM_SPEC_RUN;
                     else if (schedule & ldhit)  // exclusive
                             next_state = `THRFSM_RUN;
                     else if (ldhit)
                             next_state = `THRFSM_RDY;
                     else
                             next_state = thr_state[4:0];
                  end // case: `THRFSM_SPEC_RDY
 
                `THRFSM_SPEC_RUN:       // 5'b00111
                  begin
                     if (stall | sw_cond)
                             next_state = `THRFSM_WAIT;
                     else if ((ldhit) & switch_out)
                             next_state = `THRFSM_RDY;
                     else if ((ldhit) & ~switch_out)
                             next_state = `THRFSM_RUN;
                     else if (~(ldhit) & switch_out)
                             next_state = `THRFSM_SPEC_RDY;
                     // on an interrupt or thread stall, the fcl has to
                     // switch out the thread and inform the fsm 
                     else
                             next_state = thr_state[4:0];
                  end // case: `THRFSM_SPEC_RUN
 
//VCS coverage off
                default:
                  begin
               // synopsys translate_off
                     // 0in <fire -message "thrfsm.v: Error! Invalid State"
`ifdef DEFINE_0IN
`else
                `ifdef MODELSIM
                     $display("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);
                `else
                     $error("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);
                `endif
`endif
               // synopsys translate_on
                     if (rst_thread)
                             next_state = `THRFSM_WAIT;
                     else if (nuke_thread)
                             next_state = `THRFSM_IDLE;
                     else
                             next_state = thr_state[4:0];
                  end
//VCS coverage on
              endcase // casex({thr_state[4:0]})
     end // always @ (...
 
   // thread config register (tcr)
   dffr_s #(5) tcr(.din  (next_state),
                     .clk  (clk),
                     .q    (thr_state),
                     .rst  (reset),
                     .se   (se), .so(), `SIMPLY_RISC_SCANIN);
 
 
endmodule

Line No.	Rev	Author	Line
1	95	fafa1971	`// ========== Copyright Header Begin ==========================================`
2			`//`
3			`// OpenSPARC T1 Processor File: sparc_ifu_thrfsm.v`
4			`// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.`
5			`// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.`
6			`//`
7			`// The above named program is free software; you can redistribute it and/or`
8			`// modify it under the terms of the GNU General Public`
9			`// License version 2 as published by the Free Software Foundation.`
10			`//`
11			`// The above named program is distributed in the hope that it will be`
12			`// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
14			`// General Public License for more details.`
15			`//`
16			`// You should have received a copy of the GNU General Public`
17			`// License along with this work; if not, write to the Free Software`
18			`// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
19			`//`
20			`// ========== Copyright Header End ============================================`
21	113	albert.wat	`ifdef SIMPLY_RISC_TWEAKS
22			`define SIMPLY_RISC_SCANIN .si(0)
23			`else
24			`define SIMPLY_RISC_SCANIN .si()
25			`endif
26	95	fafa1971	`////////////////////////////////////////////////////////////////////////`
27			`/*`
28			`// Module Name: sparc_ifu_swlthrfsm`
29			`// Description:`
30			`// The switch logithrfsm contains the thread state machine.`
31			`*/`
32
33	113	albert.wat	`include "ifu.h"
34	95	fafa1971
35			`module sparc_ifu_thrfsm(/AUTOARG/`
36			`// Outputs`
37			`so, thr_state,`
38			`// Inputs`
39			`completion, schedule, spec_ld, ldhit, stall, int_activate,`
40			`start_thread, thaw_thread, nuke_thread, rst_thread, switch_out,`
41			`halt_thread, sw_cond, clk, se, si, reset`
42			`);`
43
44			`// thread specific input`
45			`input completion, // the op this thread was waiting for is complete`
46			`schedule, // this thread was just switched in`
47			`spec_ld, // speculative switch in`
48			`ldhit, // speculation was correct`
49			`stall, // stall thread for ldmiss, imiss or trap`
50			`int_activate, // activate this thread`
51			`halt_thread,`
52			`start_thread, // wake up this thread from dead state`
53			`nuke_thread,`
54			`thaw_thread,`
55			`rst_thread; // reset this thread`
56
57			`// common inputs`
58			`input switch_out, // this thread was just switched out`
59			`sw_cond; // wait until completion signal is received`
60
61			`input clk, se, si, reset;`
62
63			`output so;`
64
65			`output [4:0] thr_state;`
66
67			`// local signals`
68			`reg [4:0] next_state;`
69
70			`//`
71			`// Code Begins Here`
72			`//`
73
74			// assign spec_rdy = thr_state[`TCR_READY];
75
76			`always @ (/AUTOSENSE/ completion`
77			`or halt_thread or int_activate or ldhit or nuke_thread`
78			`or rst_thread or schedule or spec_ld or stall`
79			`or start_thread or sw_cond or switch_out or thaw_thread`
80			`or thr_state)`
81			`begin`
82			`case (thr_state[4:0])`
83	113	albert.wat	`THRFSM_IDLE: // 5'b00000
84	95	fafa1971	`begin`
85			`if (rst_thread \| thaw_thread)`
86	113	albert.wat	next_state = `THRFSM_WAIT;
87	95	fafa1971	`else if (start_thread)`
88	113	albert.wat	next_state = `THRFSM_RDY;
89	95	fafa1971	`else // all other interrupts ignored`
90			`next_state = thr_state[4:0];`
91			`end`
92
93	113	albert.wat	`THRFSM_HALT: // 5'b00010
94	95	fafa1971	`begin`
95			`if (nuke_thread)`
96	113	albert.wat	next_state = `THRFSM_IDLE;
97	95	fafa1971	`else if (rst_thread \| thaw_thread)`
98	113	albert.wat	next_state = `THRFSM_WAIT;
99	95	fafa1971	`else if (int_activate \| start_thread)`
100	113	albert.wat	next_state = `THRFSM_RDY;
101	95	fafa1971	`else`
102			`next_state = thr_state[4:0];`
103			`end`
104
105	113	albert.wat	`THRFSM_RDY: // 5'b11001
106	95	fafa1971	`begin`
107			`if (stall)`
108			`// trap also kills inst_s2 and nir`
109			`// Ldmiss should not happen in this state`
110	113	albert.wat	next_state = `THRFSM_WAIT;
111	95	fafa1971	`else if (schedule)`
112	113	albert.wat	next_state = `THRFSM_RUN;
113	95	fafa1971	`else`
114			`next_state = thr_state[4:0];`
115			end // case: `THRFSM_RDY
116
117	113	albert.wat	`THRFSM_RUN: // 5'b00101
118	95	fafa1971	`begin`
119			`if (stall \| sw_cond)`
120			`// trap also kills inst_s2 and nir`
121			`// ldmiss should not happen in this state`
122	113	albert.wat	next_state = `THRFSM_WAIT;
123	95	fafa1971	`else if (switch_out)`
124			`// on an interrupt or thread stall, the fcl has to`
125			`// switch out the thread and inform the fsm`
126	113	albert.wat	next_state = `THRFSM_RDY;
127	95	fafa1971	`else`
128			`next_state = thr_state[4:0];`
129			end // case: `THRFSM_RUN
130
131	113	albert.wat	`THRFSM_WAIT: // 5'b00001
132	95	fafa1971	`begin`
133			`if (nuke_thread)`
134	113	albert.wat	next_state = `THRFSM_IDLE;
135	95	fafa1971	`else if (halt_thread) // exclusive with above`
136	113	albert.wat	next_state = `THRFSM_HALT;
137	95	fafa1971	`else if (stall) // excl. with above`
138	113	albert.wat	next_state = `THRFSM_WAIT;
139	95	fafa1971	`else if (spec_ld) // exclusive with above`
140	113	albert.wat	next_state = `THRFSM_SPEC_RDY;
141	95	fafa1971	`else if (completion & ~halt_thread)`
142	113	albert.wat	next_state = `THRFSM_RDY;
143	95	fafa1971	`else`
144			`next_state = thr_state[4:0];`
145			end // case: `THRFSM_WAIT
146
147	113	albert.wat	`THRFSM_SPEC_RDY: // 5'b10011
148	95	fafa1971	`begin`
149			`if (stall)`
150	113	albert.wat	next_state = `THRFSM_WAIT;
151	95	fafa1971	`else if (schedule & ~ldhit) // exclusive`
152	113	albert.wat	next_state = `THRFSM_SPEC_RUN;
153	95	fafa1971	`else if (schedule & ldhit) // exclusive`
154	113	albert.wat	next_state = `THRFSM_RUN;
155	95	fafa1971	`else if (ldhit)`
156	113	albert.wat	next_state = `THRFSM_RDY;
157	95	fafa1971	`else`
158			`next_state = thr_state[4:0];`
159			end // case: `THRFSM_SPEC_RDY
160
161	113	albert.wat	`THRFSM_SPEC_RUN: // 5'b00111
162	95	fafa1971	`begin`
163			`if (stall \| sw_cond)`
164	113	albert.wat	next_state = `THRFSM_WAIT;
165	95	fafa1971	`else if ((ldhit) & switch_out)`
166	113	albert.wat	next_state = `THRFSM_RDY;
167	95	fafa1971	`else if ((ldhit) & ~switch_out)`
168	113	albert.wat	next_state = `THRFSM_RUN;
169	95	fafa1971	`else if (~(ldhit) & switch_out)`
170	113	albert.wat	next_state = `THRFSM_SPEC_RDY;
171	95	fafa1971	`// on an interrupt or thread stall, the fcl has to`
172			`// switch out the thread and inform the fsm`
173			`else`
174			`next_state = thr_state[4:0];`
175			end // case: `THRFSM_SPEC_RUN
176
177			`//VCS coverage off`
178			`default:`
179			`begin`
180			`// synopsys translate_off`
181			`// 0in <fire -message "thrfsm.v: Error! Invalid State"`
182	113	albert.wat	`ifdef DEFINE_0IN
183			`else
184			`ifdef MODELSIM
185			`$display("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);`
186			`else
187			`$error("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);`
188			`endif
189			`endif
190	95	fafa1971	`// synopsys translate_on`
191			`if (rst_thread)`
192	113	albert.wat	next_state = `THRFSM_WAIT;
193	95	fafa1971	`else if (nuke_thread)`
194	113	albert.wat	next_state = `THRFSM_IDLE;
195	95	fafa1971	`else`
196			`next_state = thr_state[4:0];`
197			`end`
198			`//VCS coverage on`
199			`endcase // casex({thr_state[4:0]})`
200			`end // always @ (...`
201
202			`// thread config register (tcr)`
203	113	albert.wat	`dffr_s #(5) tcr(.din (next_state),`
204	95	fafa1971	`.clk (clk),`
205			`.q (thr_state),`
206			`.rst (reset),`
207	113	albert.wat	.se (se), .so(), `SIMPLY_RISC_SCANIN);
208	95	fafa1971
209
210			`endmodule`

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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [sparc_ifu_thrfsm.v] - Blame information for rev 113