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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: tlu_mmu_ctl.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

`ifdef SIMPLY_RISC_TWEAKS

`define SIMPLY_RISC_SCANIN .si(0)

`else

`define SIMPLY_RISC_SCANIN .si()

`endif

///////////////////////////////////////////////////////////////////////

/*

//      Description:    MMU Control - I & D.

*/

////////////////////////////////////////////////////////////////////////

// Global header file includes

////////////////////////////////////////////////////////////////////////

`include        "sys.h" // system level definition file which contains the 

                                        // time scale definition

////////////////////////////////////////////////////////////////////////

// Local header file includes / local defines

////////////////////////////////////////////////////////////////////////

module tlu_mmu_ctl ( /*AUTOARG*/

   // Outputs

   dmmu_any_sfsr_wr, dmmu_sfsr_wr_en_l, dmmu_sfar_wr_en_l,

   immu_any_sfsr_wr, immu_sfsr_wr_en_l, immu_tsb_rd_en, tlu_tte_tag_g,

   tlu_dtlb_rw_index_vld_g,  tlu_dtlb_rw_index_g,

   tlu_dtlb_data_rd_g, tlu_dtlb_tag_rd_g, tlu_itlb_rw_index_vld_g,

   tlu_itlb_wr_vld_g, itlb_wr_vld_g, tlu_itlb_rw_index_g,

   tlu_itlb_data_rd_g, tlu_itlb_tag_rd_g, tlu_idtsb_8k_ptr,

   tlu_dtlb_invalidate_all_g, tlu_itlb_invalidate_all_g, tlu_slxa_thrd_sel,

   tlu_lsu_ldxa_tid_w2, tlu_itlb_dmp_vld_g,

   tlu_itlb_dmp_all_g, tlu_itlb_dmp_pctxt_g, tlu_itlb_dmp_actxt_g,

   tlu_itlb_dmp_nctxt_g, tlu_dtlb_dmp_vld_g, tlu_dtlb_dmp_all_g,

   tlu_dtlb_dmp_pctxt_g, tlu_dtlb_dmp_sctxt_g, tlu_dtlb_dmp_nctxt_g,

   tlu_dtlb_dmp_actxt_g, tlu_idtlb_dmp_thrid_g, tlu_dmp_key_vld_g,

   tlu_int_asi_load, tlu_int_asi_store, tlu_int_asi_thrid,

   tlu_int_asi_vld, tlb_access_rst_l,

   tlu_lsu_stxa_ack, tlu_lsu_stxa_ack_tid, mra_wr_ptr, mra_rd_ptr,

   mra_wr_vld, mra_rd_vld, tag_access_wdata_sel,

   tlu_admp_key_sel, mra_byte_wen,

   tlu_tte_wr_pid_g, tlu_lsu_ldxa_async_data_vld, tlu_tte_real_g,

   tlu_ldxa_l1mx1_sel, tlu_ldxa_l1mx2_sel, tlu_ldxa_l2mx1_sel,

   lsu_ifu_inj_ack, tlu_tlb_tag_invrt_parity,  tlu_tlb_data_invrt_parity,

   tlu_sun4r_tte_g, so, lsu_exu_ldxa_m, tlu_lng_ltncy_en_l,

   tlu_tag_access_ctxt_sel_m, tlu_tsb_rd_ps0_sel, tlu_tlb_access_en_l_d1,

   // Inputs

   ifu_lsu_ld_inst_e, ifu_lsu_st_inst_e, spu_tlu_rsrv_illgl_m,

   lsu_tlu_dmmu_miss_g,

   tlu_dtsb_split_w2, tlu_dtsb_size_w2, tlu_dtag_access_w2, tlu_itsb_split_w2,

   tlu_itsb_size_w2, tlu_ctxt_cfg_w2, lsu_tlu_st_rs3_data_g,

   lsu_tlu_st_rs3_data_b48_g, lsu_tlu_st_rs3_data_b12t0_g,

   ifu_tlu_immu_miss_m, ifu_lsu_thrid_s,

   ifu_lsu_alt_space_e, lsu_tlu_dtlb_done,

   ifu_tlu_itlb_done, lsu_tlu_tlb_asi_state_m, lsu_tlu_tlb_ldst_va_m,

   lsu_tlu_tlb_ld_inst_m, lsu_tlu_tlb_st_inst_m,

   lsu_tlu_tlb_access_tid_m, dmmu_sfsr_trp_wr,

   immu_sfsr_trp_wr, lsu_tlu_daccess_excptn_g,

   lsu_tlu_daccess_prot_g,

   lsu_pid_state0, lsu_pid_state1, lsu_pid_state2, lsu_pid_state3,

   lsu_tlu_nucleus_ctxt_m, lsu_tlu_tte_pg_sz_g, ifu_lsu_error_inj,

   ifu_tlu_alt_space_d, ifu_lsu_imm_asi_d,

   ifu_lsu_memref_d, lsu_asi_reg0, lsu_asi_reg1, lsu_asi_reg2,

   lsu_asi_reg3, exu_mmu_early_va_e, rclk, arst_l, grst_l,

   si,se,ifu_tlu_flush_m,tlu_mmu_early_flush_pipe_w,lsu_mmu_early_flush_w,

   tlu_tag_access_ctxt_g, tlu_lsu_tl_zero,

   exu_tlu_va_oor_jl_ret_m, exu_tlu_va_oor_m, tlu_lsu_pstate_am, tlu_tsb_base_w2_d1,

   lsu_mmu_flush_pipe_w, ifu_tlu_inst_vld_m, ifu_mmu_trap_m, ffu_tlu_ill_inst_m,

   exu_lsu_priority_trap_m, sehold, rst_tri_en, tlu_itag_acc_sel_g, lsu_mmu_defr_trp_taken_g,

   ifu_tlu_priv_violtn_m

   ) ;

/*AUTOINPUT*/

// Beginning of automatic inputs (from unused autoinst inputs)

// End of automatics

input                   ifu_lsu_ld_inst_e;      // inst_is_load (src-decode)

input                   ifu_lsu_st_inst_e;      // inst is store (src-decode)

input                   lsu_tlu_dmmu_miss_g ;   // ld/st misses in dtlb.

input                   spu_tlu_rsrv_illgl_m ;

input                   tlu_itag_acc_sel_g ;

input                   lsu_mmu_defr_trp_taken_g ;

// The timing on these signals can be changed to any earlier stage.

// For both SPARC_HPV_EN and non-SPARC_HPV_EN - tsb,tag-access 

// dtsb maps to ps0. itsb maps to ps1.

input  [47:13]          tlu_tsb_base_w2_d1 ;

//input  [47:13]                tlu_dtsb_base_w2 ;

input                   tlu_dtsb_split_w2 ;

input  [3:0]             tlu_dtsb_size_w2 ;

input  [47:13]          tlu_dtag_access_w2 ;    // used to represent both i/d.

//input  [47:13]                tlu_itsb_base_w2 ;

input                   tlu_itsb_split_w2 ;

input  [3:0]             tlu_itsb_size_w2 ;

// For SPARC_HPV_EN - BEGIN

input  [5:0]             tlu_ctxt_cfg_w2 ;       // i/d context zero/non-zero config.

//input                         tlu_tag_access_nctxt_g ;// tag-access contains nucleus context.

// For SPARC_HPV_EN - END

input   [62:61]         lsu_tlu_st_rs3_data_g ;     // Page Size (1,0) bits of TTE

input                   lsu_tlu_st_rs3_data_b48_g ; // Page Size (2)   bits of TTE

//input   [2:0]           lsu_tlu_st_rs3_data_b10t8_g ; // ps1 of ctxt-cfg

input   [12:0]          lsu_tlu_st_rs3_data_b12t0_g ;

//input   [2:0]           lsu_tlu_st_rs3_data_b2t0_g ; // sun4v tte size

input                   ifu_tlu_immu_miss_m ;

input   [1:0]           ifu_lsu_thrid_s ;        // Thread id.

input                   ifu_lsu_alt_space_e ;   // alt-space access

input                   lsu_tlu_dtlb_done ; // dtlb rd/wr/dmp complete

input                   ifu_tlu_itlb_done ; // itlb rd/wr/dmp complete

//input                 int_tlu_asi_data_vld ;  // asi return vld for int blk

//input                 int_tlu_ldxa_illgl_va ; // int asi has illgl va

input  [7:0]             lsu_tlu_tlb_asi_state_m ;

input  [10:0]           lsu_tlu_tlb_ldst_va_m ;

input                   lsu_tlu_tlb_ld_inst_m ;

input                   lsu_tlu_tlb_st_inst_m ;

input  [1:0]             lsu_tlu_tlb_access_tid_m ;

input                   ifu_tlu_flush_m ;

input                   tlu_mmu_early_flush_pipe_w ;

input                   lsu_mmu_early_flush_w ;

input   [3:0]    dmmu_sfsr_trp_wr ;

input   [3:0]    immu_sfsr_trp_wr ;

//input                         tlu_inst_vld_m ;        // qualified inst vld

input                   lsu_tlu_daccess_excptn_g ; // data access exception 

input                   lsu_tlu_daccess_prot_g ;// data access protection

                                                // obsolete with SPARC_HPV_EN !!!

//input                 lsu_tlu_asi_rd_unc ;    // uncorrectable error for tlb rd

input   [2:0]    lsu_pid_state0 ;        // pid thread0 ; global use

input   [2:0]    lsu_pid_state1 ;        // pid thread1 ; global use

input   [2:0]    lsu_pid_state2 ;        // pid thread2 ; global use

input   [2:0]    lsu_pid_state3 ;        // pid thread3 ; global use

input                   lsu_tlu_nucleus_ctxt_m ;// access is nucleus context

input   [2:0]            lsu_tlu_tte_pg_sz_g ;   // page-size of tte 

input   [3:0]           ifu_lsu_error_inj ;     // inject parity error into tlb

// BEGIN - MMU_ASI_RD_CHANGE

// !! early va required.

input                   ifu_tlu_alt_space_d ;   // alt space access - new;_e exists

//input                 ifu_lsu_imm_asi_vld_d ; // imm asi is vld - current

input   [8:0]            ifu_lsu_imm_asi_d ;     // imm asi - current

input                   ifu_lsu_memref_d;       // ld/st - prefer ld_inst_e;

input   [7:0]    lsu_asi_reg0 ;          // asi state - thread0

input   [7:0]    lsu_asi_reg1 ;          // asi state - thread1

input   [7:0]    lsu_asi_reg2 ;          // asi state - thread2

input   [7:0]    lsu_asi_reg3 ;          // asi state - thread3

//input [1:0]           ifu_tlu_thrid_d ;       // thread id

input   [7:0]            exu_mmu_early_va_e;     // early va from exu

// END - MMU_ASI_RD_CHANGE

input [12:0]          tlu_tag_access_ctxt_g ;

input [3:0] tlu_lsu_tl_zero;   // trap level is zero.

//input           exu_tlu_ttype_vld_m;    // exu src ttype vld

input           exu_tlu_va_oor_jl_ret_m;

input           exu_tlu_va_oor_m;

input [3:0] tlu_lsu_pstate_am;

input           lsu_mmu_flush_pipe_w ;

input           ifu_tlu_inst_vld_m ;

input           ifu_mmu_trap_m ;

input           ffu_tlu_ill_inst_m ;

input           exu_lsu_priority_trap_m ; // fill/ue

input           ifu_tlu_priv_violtn_m ;

input           rclk ;

input           arst_l, grst_l;

input           si,se;

input           sehold ;

input           rst_tri_en ;

/*AUTOOUTPUT*/

// Beginning of automatic outputs (from unused autoinst outputs)

// End of automatics

output                  dmmu_any_sfsr_wr ;

output  [3:0]            dmmu_sfsr_wr_en_l ;

output  [3:0]            dmmu_sfar_wr_en_l ;

//output        [3:0]           dmmu_tsb_wr_en ;

//output        [3:0]           dmmu_tsb_rd_en ;

//output        [3:0]           dmmu_tag_access_wr_en ;

//output        [3:0]           dmmu_tag_access_rd_en ;

//output                        dmmu_tag_read_en ; 

output                  immu_any_sfsr_wr ;

output  [3:0]            immu_sfsr_wr_en_l ;

//output        [3:0]           immu_tsb_wr_en ;

output  [3:0]            immu_tsb_rd_en ;

//output        [3:0]           immu_tag_access_wr_en ;

//output        [3:0]           immu_tag_access_rd_en ;

//output                        immu_tag_read_en ; 

// tlb/itlb related control can potentially be

// made g-stage.

output  [2:0]            tlu_tte_tag_g ;

output                  tlu_dtlb_rw_index_vld_g ;

output  [5:0]            tlu_dtlb_rw_index_g ;

output                  tlu_dtlb_data_rd_g ;

output                  tlu_dtlb_tag_rd_g ;

output                  tlu_itlb_rw_index_vld_g ;

output                  tlu_itlb_wr_vld_g ;

output                  itlb_wr_vld_g ;

output  [5:0]            tlu_itlb_rw_index_g ;

output                  tlu_itlb_data_rd_g ;

output                  tlu_itlb_tag_rd_g ;

output  [47:0]           tlu_idtsb_8k_ptr ;      // maps to ps0/ps1 ptr. require only 1.

output                  tlu_dtlb_invalidate_all_g ;

output                  tlu_itlb_invalidate_all_g ;

output  [3:0]           tlu_slxa_thrd_sel ;

output  [1:0]            tlu_lsu_ldxa_tid_w2 ;

output                  tlu_itlb_dmp_vld_g ;

output                  tlu_itlb_dmp_all_g ;

output                  tlu_itlb_dmp_pctxt_g ;

output                  tlu_itlb_dmp_actxt_g ;

output                  tlu_itlb_dmp_nctxt_g ;

output                  tlu_dtlb_dmp_vld_g ;

output                  tlu_dtlb_dmp_all_g ;

output                  tlu_dtlb_dmp_pctxt_g ;

output                  tlu_dtlb_dmp_sctxt_g ;

output                  tlu_dtlb_dmp_nctxt_g ;

output                  tlu_dtlb_dmp_actxt_g ;

output  [1:0]            tlu_idtlb_dmp_thrid_g ;

output  [4:0]           tlu_dmp_key_vld_g ;

output                  tlu_int_asi_load;

output                  tlu_int_asi_store;

output  [1:0]            tlu_int_asi_thrid;

output                  tlu_int_asi_vld;

//output                        tlb_access_en_l ;

output                  tlb_access_rst_l ;

output                  tlu_lsu_stxa_ack ;         // write to tlb is complete.

output   [1:0]           tlu_lsu_stxa_ack_tid ;

output   [3:0]          mra_wr_ptr ;    // wr ptr for mra

output   [3:0]          mra_rd_ptr ;    // thrd id for rd.

output                  mra_wr_vld ;    // write pointer vld

output                  mra_rd_vld ;    // read vld

output   [19:0]          mra_byte_wen ;

output   [2:0]           tag_access_wdata_sel ;

output                  tlu_admp_key_sel ;

//output                        tlu_mmu_sync_data_excp_g ;      // sync asi related data excp

//output                        tlu_lsu_dtlb_rd_unc ;           // unc error for tlb rd

//output   [3:0]          tlu_dldxa_mx2_sel ;           // obsolete for SPARC_HPV_EN

//output   [2:0]          tlu_dldxa_mx3_sel ;           // obsolete for SPARC_HPV_EN

//output   [2:0]          tlu_dldxa_fmx_sel ;           // obsolete for SPARC_HPV_EN

//output   [3:0]          tlu_ildxa_mx1_sel ;           // obsolete for SPARC_HPV_EN

//output   [2:0]          tlu_ildxa_fmx_sel ;           // obsolete for SPARC_HPV_EN

output   [2:0]           tlu_tte_wr_pid_g ;      // thread selected pid

output                  tlu_lsu_ldxa_async_data_vld ;   // tlu_lsu_ldxa_data_vld is for async op.

output                  tlu_tte_real_g ;                // tte is real

output  [3:0]    tlu_ldxa_l1mx1_sel ;    // mmu ldxa level1 mx1 sel

output  [3:0]    tlu_ldxa_l1mx2_sel ;    // mmu ldxa level1 mx2 sel

output  [2:0]    tlu_ldxa_l2mx1_sel ;    // mmu ldxa level2 mx1 sel

output  [3:0]           lsu_ifu_inj_ack ;       // ack for tlb error injection.

output                  tlu_tlb_tag_invrt_parity ;      // invert parity on write tag.

output                  tlu_tlb_data_invrt_parity ;     // invert parity on write data.

output                  tlu_sun4r_tte_g ;       // sun4r vs. sun4v tte.

output                  lsu_exu_ldxa_m ;

output                  tlu_lng_ltncy_en_l ;

output  [2:0]            tlu_tag_access_ctxt_sel_m ;

output                  tlu_tsb_rd_ps0_sel ;

output                  tlu_tlb_access_en_l_d1 ;

output                  so ;

/*AUTOWIRE*/

// Beginning of automatic wires (for undeclared instantiated-module outputs)

`ifdef SIMPLY_RISC_TWEAKS

wire alt_space_e;

`endif

// End of automatics

reg                     dmmu_invalidate_all_en_m ;

reg                     immu_invalidate_all_en_m ;

reg     dmmu_decode_asi58_e ;

reg     immu_decode_asi50_e ;

reg     dmmu_8k_ptr_e,dmmu_64k_ptr_e,dmmu_direct_ptr_e ;

reg     immu_8k_ptr_e,immu_64k_ptr_e;

reg     dmmu_zctxt_ps0_tsb_e, dmmu_zctxt_ps1_tsb_e ;

reg     dmmu_nzctxt_ps0_tsb_e, dmmu_nzctxt_ps1_tsb_e ;

reg     dmmu_zctxt_cfg_e, dmmu_nzctxt_cfg_e ;

reg     immu_zctxt_ps0_tsb_e, immu_zctxt_ps1_tsb_e ;

reg     immu_nzctxt_ps0_tsb_e, immu_nzctxt_ps1_tsb_e ;

reg     immu_zctxt_cfg_e, immu_nzctxt_cfg_e ;

reg                     dmmu_data_in_en_m,dmmu_data_access_en_m;

reg                     dmmu_tag_read_en_m,dmmu_demap_en_m;

wire                    sehold_d1 ;

wire                    tlb_access_en_l ;

wire                    dmmu_sync_illgl_va_g ;

wire                    dmmu_async_supported_asi,dmmu_async_illgl_va_g ;

wire                    immu_sync_illgl_va_g ;

wire                    immu_async_supported_asi,immu_async_illgl_va_g ;

wire                    ld_inst_m,st_inst_m ;

wire                    ld_inst_g,st_inst_g ;

wire [3:0]               tsb_size ;

wire                    tsb_split ;

//wire [47:13]          tsb_base ;

wire [47:13]            tag_access ;

/*wire  tsb_sz_8k_b0_mx1_out,tsb_sz_8k_b1_mx1_out,tsb_sz_8k_b2_mx1_out,tsb_sz_8k_b3_mx1_out;

wire    tsb_sz_8k_b4_mx1_out,tsb_sz_8k_b5_mx1_out,tsb_sz_8k_b6_mx1_out,tsb_sz_8k_b7_mx1_out;

wire    tsb_sz_8k_b0_mx2_out,tsb_sz_8k_b1_mx2_out,tsb_sz_8k_b2_mx2_out,tsb_sz_8k_b3_mx2_out;

wire    tsb_sz_8k_b4_mx2_out,tsb_sz_8k_b5_mx2_out,tsb_sz_8k_b6_mx2_out,tsb_sz_8k_b7_mx2_out;

wire    tsb_sz_8k_b0_mx3_out,tsb_sz_8k_b1_mx3_out,tsb_sz_8k_b2_mx3_out,tsb_sz_8k_b3_mx3_out;

wire    tsb_sz_8k_b4_mx3_out,tsb_sz_8k_b5_mx3_out,tsb_sz_8k_b6_mx3_out,tsb_sz_8k_b7_mx3_out;

wire    tsb_sz_64k_b0_mx1_out,tsb_sz_64k_b1_mx1_out,tsb_sz_64k_b2_mx1_out,tsb_sz_64k_b3_mx1_out;

wire    tsb_sz_64k_b4_mx1_out,tsb_sz_64k_b5_mx1_out,tsb_sz_64k_b6_mx1_out,tsb_sz_64k_b7_mx1_out;

wire    tsb_sz_64k_b0_mx2_out,tsb_sz_64k_b1_mx2_out,tsb_sz_64k_b2_mx2_out,tsb_sz_64k_b3_mx2_out;

wire    tsb_sz_64k_b4_mx2_out,tsb_sz_64k_b5_mx2_out,tsb_sz_64k_b6_mx2_out ;

wire    tsb_sz_64k_b0_mx3_out,tsb_sz_64k_b1_mx3_out,tsb_sz_64k_b2_mx3_out,tsb_sz_64k_b3_mx3_out;

wire    tsb_sz_64k_b4_mx3_out ;*/

wire    dtlb_rw_index_vld_g,dtlb_wr_vld_g ;

wire            dmmu_data_in_wr_en, dmmu_data_access_wr_en ;

wire            dmmu_tag_read_rd_en, dmmu_data_access_rd_en ;

wire            immu_data_in_wr_en, immu_data_access_wr_en ;

wire            immu_data_access_rd_en, immu_tag_read_rd_en ;

wire            itlb_rw_index_vld_g,itlb_wr_vld_g;

wire            tlu_ldxa_data_vld ;

wire    tlu_dldxa_data_vld ;

wire    [1:0]    thrid_d,thrid_e,thrid_m,thrid_g ;

wire            thread0_sel_g, thread1_sel_g ;

wire            thread2_sel_g, thread3_sel_g ;

wire            alt_space_m, alt_space_g ;

wire            immu_miss_g;

wire            ddemap_by_page,ddemap_by_ctxt,ddemap_all;

wire            idemap_by_page,idemap_by_ctxt,idemap_all;

wire            demap_pctxt,demap_sctxt,demap_nctxt ;

//wire          lsu_tlu_page_ebit_g ;

wire            ddemap_vld, idemap_vld ;

wire    [2:0]   tlu_tte_tag_g ;

wire            demap_resrv ;

wire    itlb_wr_pend,itlb_data_rd_pend,itlb_tag_rd_pend ;

wire    dtlb_wr_pend,dtlb_data_rd_pend,dtlb_tag_rd_pend ;

wire    tlb_access_en ;

wire    tlb_access_rst ;

wire    dmra_wr_g, imra_wr_g ;

wire                    dmmu_data_in_en, dmmu_data_access_en, dmmu_tag_read_en, dmmu_demap_en ;

wire                    immu_data_in_en, immu_data_access_en, immu_tag_read_en, immu_demap_en ;

wire    immu_invalidate_all_en,dmmu_invalidate_all_en ;

wire    tlb_wr_vld_g ;

wire    tlb_admp_en, tlb_admp_rst, tlb_wr_rst ;

wire    tlb_admp_mode,tlb_write_mode ;

wire    tlb_ldst_inst_m ;

wire    tlb_admp_mode_d1 ;

wire    itlb_wr_vld_unmsked,dtlb_wr_vld_unmsked;

wire    idemap_pend, ddemap_pend ;

wire    itlb_tag_rd_en, dtlb_tag_rd_en ;

wire    [3:0]    dsfsr_asi_wr_en ;

wire    [3:0]    isfsr_asi_wr_en ;

wire    [10:3]  tlb_ldst_va_g ;

wire            tlb_ld_inst_g,tlb_st_inst_g ;

wire            tlb_ld_inst_unflushed,tlb_st_inst_unflushed ;

wire    [1:0]    tlb_access_tid_g ;

wire            inst_vld_g ;

wire    st_inst_unflushed, ld_inst_unflushed ;

wire    imra_lng_lat_rd,dmra_lng_lat_rd ;

wire    iside_mra_access_rd, iside_mra_access_wr ;

wire    [1:0]    mra_raccess_tid ;

//wire  dmmu_sync_rd_only_asi_g ;

//wire  immu_sync_rd_only_asi_g ;

wire    dptr0_pg64k_en,dptr1_pg64k_en,dptr2_pg64k_en,dptr3_pg64k_en;

wire    dptr0_pg64k_vld,dptr1_pg64k_vld,dptr2_pg64k_vld,dptr3_pg64k_vld;

//wire  dmmu_direct_ptr_rd_en ;

wire    tlu_dtlb_rd_done ;

wire    dmmu_ctxt_cfg_en, immu_ctxt_cfg_en ;

//wire  dmmu_ctxt_cfg_rd_en ;

wire    dacc_prot_ps1_match ;

wire    tacc_nctxt, itacc_nctxt, dtacc_nctxt ;  // for in-pipe access

wire    tacc_anctxt, itacc_anctxt, dtacc_anctxt ;// for async access

wire    thread0_async_g,thread1_async_g,thread2_async_g ;

wire    sun4r_tte_g ;

wire    dmmu_decode_asi58_m, immu_decode_asi50_m ;

wire    dmmu_zctxt_ps0_tsb_m, dmmu_zctxt_ps1_tsb_m,

        dmmu_nzctxt_ps0_tsb_m, dmmu_nzctxt_ps1_tsb_m,

        dmmu_zctxt_cfg_m, dmmu_nzctxt_cfg_m,

        immu_zctxt_ps0_tsb_m, immu_zctxt_ps1_tsb_m,

        immu_nzctxt_ps0_tsb_m, immu_nzctxt_ps1_tsb_m,

        immu_zctxt_cfg_m, immu_nzctxt_cfg_m ;

wire    dmmu_sync_fsr_en, dmmu_sync_far_en,

        dmmu_zctxt_ps0_tsb_en, dmmu_zctxt_ps1_tsb_en,

        dmmu_nzctxt_ps0_tsb_en, dmmu_nzctxt_ps1_tsb_en,

        dmmu_zctxt_cfg_en, dmmu_nzctxt_cfg_en,

        immu_sync_fsr_en,

        immu_zctxt_ps0_tsb_en, immu_zctxt_ps1_tsb_en,

        immu_nzctxt_ps0_tsb_en, immu_nzctxt_ps1_tsb_en,

        immu_zctxt_cfg_en, immu_nzctxt_cfg_en ;

wire    dmmu_tag_target_en_m,dmmu_tag_access_en_m;

wire    immu_tag_target_en_m,immu_tag_access_en_m;

wire    dmmu_tag_access_en;

wire    immu_tag_access_en;

wire    dmmu_8k_ptr_en_m,dmmu_64k_ptr_en_m,dmmu_direct_ptr_en_m ;

wire    immu_8k_ptr_en_m,immu_64k_ptr_en_m ;

wire    dmmu_sync_fsr_en_m, dmmu_sync_far_en_m,

        dmmu_zctxt_ps0_tsb_en_m, dmmu_zctxt_ps1_tsb_en_m,

        dmmu_nzctxt_ps0_tsb_en_m, dmmu_nzctxt_ps1_tsb_en_m,

        dmmu_zctxt_cfg_en_m, dmmu_nzctxt_cfg_en_m,

        immu_sync_fsr_en_m,

        immu_zctxt_ps0_tsb_en_m, immu_zctxt_ps1_tsb_en_m,

        immu_nzctxt_ps0_tsb_en_m, immu_nzctxt_ps1_tsb_en_m,

        immu_zctxt_cfg_en_m, immu_nzctxt_cfg_en_m ;

wire    thread0_d,thread1_d,thread2_d,thread3_d;

wire    thread0_e, thread1_e, thread2_e, thread3_e ;

wire [7:0]       asi_state_d, asi_state_e ;

wire    memref_e,memref_m ;

wire [7:0] early_va_m ;

wire    idmra_rd_d ;

wire idmra_nzctxt_rd_d ;

wire idmra_fault_rd_d ;

wire    dmmu_tsb_en_m, dmmu_ctxt_cfg_en_m ;

wire    immu_tsb_en_m, immu_ctxt_cfg_en_m ;

wire    tlu_ildxa_data_vld ;

wire    dmmu_direct_8kptr_sel_g ;       // direct ptr should select 8k ptr

        wire    dmmu_tsb_en ;

        wire    immu_tsb_en ;

wire    mra_field1_en, mra_field2_en ;

wire    mra_field3_en, mra_field4_en ;

//=========================================================================================

//      RESET/CLK

//=========================================================================================

    wire       clk;

    assign     clk = rclk;

    wire       rst_l;

    dffrl_async rstff(.din (grst_l),

                      .q   (rst_l),

                      .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so(),

                      .rst_l (arst_l));

//=========================================================================================

//      Early Flush Generation

//=========================================================================================

wire    ifu_tlu_flush_w ;

dff_s  #(1) stg_w (

        .din    (ifu_tlu_flush_m),

        .q      (ifu_tlu_flush_w),

        .clk    (clk),

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

) ;

wire    local_flush_w ;

assign  local_flush_w =

        ifu_tlu_flush_w                 |       // ifu flush 

        lsu_mmu_defr_trp_taken_g        |       // defr trp 

        tlu_mmu_early_flush_pipe_w      |       // tlu flush

        lsu_mmu_early_flush_w           ;       // lsu early flush

wire    flush_w_inst_vld_m ;

assign  flush_w_inst_vld_m =

        ifu_tlu_inst_vld_m &

        ~(lsu_mmu_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w

dff_s  stgw_ivld (

        .din    (flush_w_inst_vld_m),

        .q      (inst_vld_g),

        .clk    (clk),

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

        );

// Bug 4183

wire    priority_squash_m, priority_squash_g ;

assign  priority_squash_m =

ifu_mmu_trap_m | ffu_tlu_ill_inst_m | exu_lsu_priority_trap_m |  spu_tlu_rsrv_illgl_m ;

wire    trp_vld_m,trp_vld_g ;

assign  trp_vld_m = flush_w_inst_vld_m & ~priority_squash_m ;

dff_s  #(2) sqshstgw (

        .din    ({priority_squash_m,trp_vld_m}),

        .q      ({priority_squash_g,trp_vld_g}),

        .clk    (clk),

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

) ;

//=========================================================================================

//      Staging

//=========================================================================================

dff_s  #(2) stg_d (

        .din    (ifu_lsu_thrid_s[1:0]),

        .q      (thrid_d[1:0]),

        .clk    (clk),

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

        );

dff_s  #(2) stg_e (

        .din    (thrid_d[1:0]),

        .q      (thrid_e[1:0]),

        .clk    (clk),

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

        );

dff_s  #(5) stg_m (

        .din    ({ifu_lsu_ld_inst_e,ifu_lsu_st_inst_e,

                thrid_e[1:0],ifu_lsu_alt_space_e}),

        .q      ({ld_inst_m,st_inst_m,thrid_m[1:0],alt_space_m}),

        .clk    (clk),

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

        );

dff_s  #(6) stg_g (

        .din    ({ld_inst_m,st_inst_m,thrid_m[1:0],alt_space_m,ifu_tlu_immu_miss_m}),

        .q      ({ld_inst_unflushed,st_inst_unflushed,thrid_g[1:0],alt_space_g,immu_miss_g}),

        .clk    (clk),

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

        );

// reads are terminated for illegal va case.

assign  ld_inst_g = ld_inst_unflushed & inst_vld_g & ~local_flush_w ;

//assign        ld_inst_g = ld_inst_unflushed & inst_vld_g & ~(dmmu_sync_illgl_va_g | immu_sync_illgl_va_g) & ;

// writes are terminated for illegal va case.

assign  st_inst_g = st_inst_unflushed & inst_vld_g & ~local_flush_w &

                        ~(dmmu_sync_illgl_va_g | immu_sync_illgl_va_g) ;

//assign        st_inst_g = st_inst_unflushed & inst_vld_g & ~(dmmu_sync_illgl_va_g | immu_sync_illgl_va_g);

assign  thread0_sel_g =  ~thrid_g[1] & ~thrid_g[0] ;

assign  thread1_sel_g =  ~thrid_g[1] &  thrid_g[0] ;

assign  thread2_sel_g =   thrid_g[1] & ~thrid_g[0] ;

assign  thread3_sel_g =   thrid_g[1] &  thrid_g[0] ;

assign tlu_slxa_thrd_sel[0] = ~thrid_m[1] & ~thrid_m[0] ;

assign tlu_slxa_thrd_sel[1] = ~thrid_m[1] &  thrid_m[0] ;

assign tlu_slxa_thrd_sel[2] =  thrid_m[1] & ~thrid_m[0] ;

assign tlu_slxa_thrd_sel[3] =  thrid_m[1] &  thrid_m[0] ;

/*dff stgivld_g (

        .din    (tlu_inst_vld_m),

        .q      (inst_vld_g),

        .clk    (clk),

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

        ); */

//=========================================================================================

//      ASI RD DP MUX SELECT

//=========================================================================================

// qualification with vld not required as this dp is used by synchronous ops only

// Need to be made non zero-hot in functional mode

// Decode of bits va[5:4] to distinguish reads.  

wire va_54_eq_0,va_54_eq_1,va_54_eq_2,va_54_eq_3 ;

wire    [2:0]    ldxa_l1mx1_sel_d1 ;

assign va_54_eq_0 = (~early_va_m[5] & ~early_va_m[4]) ;

assign va_54_eq_1 = (~early_va_m[5] &  early_va_m[4]) ;

assign va_54_eq_2 = ( early_va_m[5] & ~early_va_m[4]) ;

assign va_54_eq_3 = ( early_va_m[5] &  early_va_m[4]) ;

// i/d tag-target

// Extend for MacroTest Control.

assign  tlu_ldxa_l1mx1_sel[0] =

((((dmmu_decode_asi58_m | immu_decode_asi50_m) & va_54_eq_0) & ~sehold_d1) | rst_tri_en) |

(ldxa_l1mx1_sel_d1[0] & sehold_d1) ;

assign  tlu_ldxa_l1mx1_sel[1] =

((dmmu_zctxt_ps0_tsb_e | dmmu_nzctxt_ps0_tsb_e |

immu_zctxt_ps0_tsb_e | immu_nzctxt_ps0_tsb_e) & ~sehold_d1 & ~rst_tri_en) |

(ldxa_l1mx1_sel_d1[1] & sehold_d1) ;

assign  tlu_ldxa_l1mx1_sel[2] =

((dmmu_zctxt_ps1_tsb_e | dmmu_nzctxt_ps1_tsb_e |

immu_zctxt_ps1_tsb_e | immu_nzctxt_ps1_tsb_e) & ~sehold_d1 & ~rst_tri_en) |

(ldxa_l1mx1_sel_d1[2] & sehold_d1) ;

// Extend flops to hold selects for MacroTest of MRA.

wire [2:0] ldxa_l1mx1_sel_out ;

dff_s #(3)   l1mx1s_stgd1(

        .din    (tlu_ldxa_l1mx1_sel[2:0]),

        .q      (ldxa_l1mx1_sel_out[2:0]),

        .clk    (clk),

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

        );

// scan protection.

assign  ldxa_l1mx1_sel_d1[0] = ldxa_l1mx1_sel_out[0] ;

assign  ldxa_l1mx1_sel_d1[1] = ldxa_l1mx1_sel_out[1] & ~rst_tri_en ;

assign  ldxa_l1mx1_sel_d1[2] = ldxa_l1mx1_sel_out[2] & ~rst_tri_en ;

wire    sehold_out ;

dff_s #(1)   seh_d1 (

        .din    (sehold),

        .q      (sehold_out),

        .clk    (clk),

        .se     (1'b0),         `SIMPLY_RISC_SCANIN,          .so ()

        );

assign  sehold_d1 = sehold_out & ~rst_tri_en ;

// i/d tag-access

assign  tlu_ldxa_l1mx1_sel[3] =  ~|tlu_ldxa_l1mx1_sel[2:1];

wire    ldxa_l1mx1_sel3;

// * read timing change.

assign  ldxa_l1mx1_sel3 =

(dmmu_decode_asi58_m | immu_decode_asi50_m) & va_54_eq_3 & ~rst_tri_en ;

// d sync-fsr

// * read timing change.

wire    dmmu_sync_fsr_m_sel,dmmu_sync_far_m_sel,immu_sync_fsr_m_sel;

assign  dmmu_sync_fsr_m_sel     = (dmmu_decode_asi58_m & va_54_eq_1) | rst_tri_en ;

assign  dmmu_sync_far_m_sel     = (dmmu_decode_asi58_m & va_54_eq_2) & ~rst_tri_en ;

assign  immu_sync_fsr_m_sel     = (immu_decode_asi50_m & va_54_eq_1) & ~rst_tri_en ;

assign  tlu_ldxa_l1mx2_sel[0] = dmmu_sync_fsr_m_sel ;

// d sync-far

// * read timing change.

assign  tlu_ldxa_l1mx2_sel[1] = dmmu_sync_far_m_sel ;

// i sync-fsr

assign  tlu_ldxa_l1mx2_sel[2] = immu_sync_fsr_m_sel ;

assign  tlu_ldxa_l1mx2_sel[3] = ~|tlu_ldxa_l1mx2_sel[2:0];