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[/] [s6soc/] [trunk/] [bench/] [cpp/] [qspiflashsim.cpp] - Blame information for rev 17

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
//
4
// Filename:    spiflashsim.cpp
5
//
6
// Project:     Wishbone Controlled Quad SPI Flash Controller
7
//
8
// Purpose:     This library simulates the operation of a Quad-SPI commanded
9
//              flash, such as the S25FL032P used on the Basys-3 development
10
//              board by Digilent.  As such, it is defined by 32 Mbits of
11
//              memory (4 Mbyte).
12
//
13
//              This simulator is useful for testing in a Verilator/C++
14
//              environment, where this simulator can be used in place of
15
//              the actual hardware.
16
//
17
// Creator:     Dan Gisselquist
18
//              Gisselquist Technology, LLC
19
//
20
///////////////////////////////////////////////////////////////////////////
21
//
22
// Copyright (C) 2015, Gisselquist Technology, LLC
23
//
24
// This program is free software (firmware): you can redistribute it and/or
25
// modify it under the terms of  the GNU General Public License as published
26
// by the Free Software Foundation, either version 3 of the License, or (at
27
// your option) any later version.
28
//
29
// This program is distributed in the hope that it will be useful, but WITHOUT
30
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
31
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
32
// for more details.
33
//
34
// You should have received a copy of the GNU General Public License along
35
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
36
// target there if the PDF file isn't present.)  If not, see
37
// <http://www.gnu.org/licenses/> for a copy.
38
//
39
// License:     GPL, v3, as defined and found on www.gnu.org,
40
//              http://www.gnu.org/licenses/gpl.html
41
//
42
//
43
///////////////////////////////////////////////////////////////////////////
44
#include <stdio.h>
45
#include <string.h>
46
#include <assert.h>
47
#include <stdlib.h>
48
 
49 10 dgisselq
#include "regdefs.h"
50 2 dgisselq
#include "qspiflashsim.h"
51
 
52 10 dgisselq
#define MEMBYTES        (FLASHWORDS<<2)
53 2 dgisselq
 
54
static  const unsigned  DEVID = 0x0115,
55
        DEVESD = 0x014,
56
        MICROSECONDS = 100,
57
        MILLISECONDS = MICROSECONDS * 1000,
58
        SECONDS = MILLISECONDS * 1000,
59
        tW     =   50 * MICROSECONDS, // write config cycle time
60
        tBE    =   32 * SECONDS,
61
        tDP    =   10 * SECONDS,
62
        tRES   =   30 * SECONDS,
63
// Shall we artificially speed up this process?
64
        tPP    = 12 * MICROSECONDS,
65
        tSE    = 15 * MILLISECONDS;
66
// or keep it at the original speed
67
        // tPP    = 1200 * MICROSECONDS,
68
        // tSE    = 1500 * MILLISECONDS;
69
 
70
QSPIFLASHSIM::QSPIFLASHSIM(void) {
71
        m_mem = new char[MEMBYTES];
72
        m_pmem = new char[256];
73
        m_state = QSPIF_IDLE;
74
        m_last_sck = 1;
75
        m_write_count = 0;
76
        m_ireg = m_oreg = 0;
77
        m_sreg = 0x01c;
78
        m_creg = 0x001; // Iinitial creg on delivery
79
        m_quad_mode = false;
80
        m_mode_byte = 0;
81
 
82
        memset(m_mem, 0x0ff, MEMBYTES);
83
}
84
 
85
void    QSPIFLASHSIM::load(const unsigned addr, const char *fname) {
86
        FILE    *fp;
87
        size_t  len;
88
 
89
        if (addr >= MEMBYTES)
90
                return;
91
        len = MEMBYTES-addr*4;
92
 
93
        if (NULL != (fp = fopen(fname, "r"))) {
94
                int     nr = 0;
95
                nr = fread(&m_mem[addr], sizeof(char), len, fp);
96
                fclose(fp);
97
                if (nr == 0) {
98
                        fprintf(stderr, "SPI-FLASH: Could not read %s\n", fname);
99
                        perror("O/S Err:");
100
                }
101
        } else {
102
                fprintf(stderr, "SPI-FLASH: Could not open %s\n", fname);
103
                perror("O/S Err:");
104
        }
105
}
106
 
107 10 dgisselq
void    QSPIFLASHSIM::write(const unsigned addr, const unsigned len, const uint32_t *buf) {
108
        char    *ptr;
109 17 dgisselq
        if ((addr+len < SPIFLASH)||(addr >= SPIFLASH+MEMBYTES/4))
110
                return;
111 10 dgisselq
        printf("FLASH: Copying into memory at S6Add4 %08x, my addr %08x, %d values\n",
112
                addr, (addr-SPIFLASH)<<2, len<<2);
113
        ptr = &m_mem[(addr-SPIFLASH)<<2];
114
        memcpy(ptr, buf, len<<2);
115
        printf("%02x %02x %02x %02x\n", ptr[0]&0x0ff, ptr[1]&0x0ff, ptr[2]&0x0ff, ptr[3]&0x0ff);
116
}
117
 
118 2 dgisselq
#define QOREG(A)        m_oreg = ((m_oreg & (~0x0ff))|(A&0x0ff))
119
 
120
int     QSPIFLASHSIM::operator()(const int csn, const int sck, const int dat) {
121
        // Keep track of a timer to determine when page program and erase
122
        // cycles complete.
123
 
124
        if (m_write_count > 0) {
125
                if (0 == (--m_write_count)) {// When done with erase/page pgm,
126
                        m_sreg &= 0x0fc; // Clear the write in progress bit
127
                        if (m_debug) printf("Write complete, clearing WIP (inside SIM)\n");
128
                }
129
        }
130
 
131
        if (csn) {
132
                m_last_sck = 1;
133
                m_ireg = 0; m_oreg = 0;
134
                m_count= 0;
135
 
136
                if ((QSPIF_PP == m_state)||(QSPIF_QPP == m_state)) {
137
                        // Start a page program
138
                        if (m_debug) printf("QSPI: Page Program write cycle begins\n");
139
                        if (m_debug) printf("CK = %d & 7 = %d\n", m_count, m_count & 0x07);
140
                        if (m_debug) printf("QSPI: pmem = %08lx\n", (unsigned long)m_pmem);
141
                        m_write_count = tPP;
142
                        m_state = QSPIF_IDLE;
143
                        m_sreg &= (~QSPIF_WEL_FLAG);
144
                        m_sreg |= (QSPIF_WIP_FLAG);
145
                        for(int i=0; i<256; i++) {
146
                                /*
147
                                if (m_debug) printf("%02x: m_mem[%02x] = %02x &= %02x = %02x\n",
148
                                        i, (m_addr&(~0x0ff))+i,
149
                                        m_mem[(m_addr&(~0x0ff))+i]&0x0ff, m_pmem[i]&0x0ff,
150
                                        m_mem[(m_addr&(~0x0ff))+i]& m_pmem[i]&0x0ff);
151
                                */
152
                                m_mem[(m_addr&(~0x0ff))+i] &= m_pmem[i];
153
                        }
154
                        m_quad_mode = false;
155
                } else if (m_state == QSPIF_SECTOR_ERASE) {
156
                        if (m_debug) printf("Actually Erasing sector, from %08x\n", m_addr);
157
                        m_write_count = tSE;
158
                        m_state = QSPIF_IDLE;
159
                        m_sreg &= (~QSPIF_WEL_FLAG);
160
                        m_sreg |= (QSPIF_WIP_FLAG);
161
                        m_addr &= (-1<<16);
162
                        for(int i=0; i<(1<<16); i++)
163
                                m_mem[m_addr + i] = 0x0ff;
164
                        if (m_debug) printf("Now waiting %d ticks delay\n", m_write_count);
165
                } else if (QSPIF_WRSR == m_state) {
166
                        if (m_debug) printf("Actually writing status register\n");
167
                        m_write_count = tW;
168
                        m_state = QSPIF_IDLE;
169
                        m_sreg &= (~QSPIF_WEL_FLAG);
170
                        m_sreg |= (QSPIF_WIP_FLAG);
171
                } else if (QSPIF_CLSR == m_state) {
172
                        if (m_debug) printf("Actually clearing the status register bits\n");
173
                        m_state = QSPIF_IDLE;
174
                        m_sreg &= 0x09f;
175
                } else if (m_state == QSPIF_BULK_ERASE) {
176
                        m_write_count = tBE;
177
                        m_state = QSPIF_IDLE;
178
                        m_sreg &= (~QSPIF_WEL_FLAG);
179
                        m_sreg |= (QSPIF_WIP_FLAG);
180
                        for(int i=0; i<MEMBYTES; i++)
181
                                m_mem[i] = 0x0ff;
182
                } else if (m_state == QSPIF_DEEP_POWER_DOWN) {
183
                        m_write_count = tDP;
184
                        m_state = QSPIF_IDLE;
185
                } else if (m_state == QSPIF_RELEASE) {
186
                        m_write_count = tRES;
187
                        m_state = QSPIF_IDLE;
188
                } else if (m_state == QSPIF_QUAD_READ_CMD) {
189
                        if ((m_mode_byte & 0x0f0)!=0x0a0)
190
                                m_quad_mode = false;
191
                        else
192
                                m_state = QSPIF_QUAD_READ_IDLE;
193
                } else if (m_state == QSPIF_QUAD_READ) {
194
                        if ((m_mode_byte & 0x0f0)!=0x0a0)
195
                                m_quad_mode = false;
196
                        else
197
                                m_state = QSPIF_QUAD_READ_IDLE;
198
                } else if (m_state == QSPIF_QUAD_READ_IDLE) {
199
                }
200
 
201
                m_oreg = 0x0fe;
202
                return dat;
203
        } else if ((!m_last_sck)||(sck == m_last_sck)) {
204
                // Only change on the falling clock edge
205
                // printf("SFLASH-SKIP, CLK=%d -> %d\n", m_last_sck, sck);
206
                m_last_sck = sck;
207
                if (m_quad_mode)
208
                        return (m_oreg>>8)&0x0f;
209
                else
210
                        // return ((m_oreg & 0x0100)?2:0) | (dat & 0x0d);
211
                        return (m_oreg & 0x0100)?2:0;
212
        }
213
 
214
        // We'll only get here if ...
215
        //      last_sck = 1, and sck = 0, thus transitioning on the
216
        //      negative edge as with everything else in this interface
217
        if (m_quad_mode) {
218
                m_ireg = (m_ireg << 4) | (dat & 0x0f);
219
                m_count+=4;
220
                m_oreg <<= 4;
221
        } else {
222
                m_ireg = (m_ireg << 1) | (dat & 1);
223
                m_count++;
224
                m_oreg <<= 1;
225
        }
226
 
227
 
228
        // printf("PROCESS, COUNT = %d, IREG = %02x\n", m_count, m_ireg);
229
        if (m_state == QSPIF_QUAD_READ_IDLE) {
230
                assert(m_quad_mode);
231
                if (m_count == 24) {
232
                        if (m_debug) printf("QSPI: Entering from Quad-Read Idle to Quad-Read\n");
233
                        if (m_debug) printf("QSPI: QI/O Idle Addr = %02x\n", m_ireg&0x0ffffff);
234
                        m_addr = (m_ireg) & 0x0ffffff;
235
                        assert((m_addr & 0xfc00000)==0);
236
                        m_state = QSPIF_QUAD_READ;
237
                } m_oreg = 0;
238
        } else if (m_count == 8) {
239
                QOREG(0x0a5);
240
                // printf("SFLASH-CMD = %02x\n", m_ireg & 0x0ff);
241
                // Figure out what command we've been given
242
                if (m_debug) printf("SPI FLASH CMD %02x\n", m_ireg&0x0ff);
243
                switch(m_ireg & 0x0ff) {
244
                case 0x01: // Write status register
245
                        if (2 !=(m_sreg & 0x203)) {
246
                                if (m_debug) printf("QSPI: WEL not set, cannot write status reg\n");
247
                                m_state = QSPIF_INVALID;
248
                        } else
249
                                m_state = QSPIF_WRSR;
250
                        break;
251
                case 0x02: // Page program
252
                        if (2 != (m_sreg & 0x203)) {
253
                                if (m_debug) printf("QSPI: Cannot program at this time, SREG = %x\n", m_sreg);
254
                                m_state = QSPIF_INVALID;
255
                        } else {
256
                                m_state = QSPIF_PP;
257
                                if (m_debug) printf("PAGE-PROGRAM COMMAND ACCEPTED\n");
258
                        }
259
                        break;
260
                case 0x03: // Read data bytes
261
                        // Our clock won't support this command, so go
262
                        // to an invalid state
263
                        if (m_debug) printf("QSPI INVALID: This sim does not support slow reading\n");
264
                        m_state = QSPIF_INVALID;
265
                        break;
266
                case 0x04: // Write disable
267
                        m_state = QSPIF_IDLE;
268
                        m_sreg &= (~QSPIF_WEL_FLAG);
269
                        break;
270
                case 0x05: // Read status register
271
                        m_state = QSPIF_RDSR;
272
                        if (m_debug) printf("QSPI: READING STATUS REGISTER: %02x\n", m_sreg);
273
                        QOREG(m_sreg);
274
                        break;
275
                case 0x06: // Write enable
276
                        m_state = QSPIF_IDLE;
277
                        m_sreg |= QSPIF_WEL_FLAG;
278
                        if (m_debug) printf("QSPI: WRITE-ENABLE COMMAND ACCEPTED\n");
279
                        break;
280
                case 0x0b: // Here's the read that we support
281
                        if (m_debug) printf("QSPI: FAST-READ (single-bit)\n");
282
                        m_state = QSPIF_FAST_READ;
283
                        break;
284
                case 0x30:
285
                        if (m_debug) printf("QSPI: CLEAR STATUS REGISTER COMMAND\n");
286
                        m_state = QSPIF_CLSR;
287
                        break;
288
                case 0x32: // QUAD Page program, 4 bits at a time
289
                        if (2 != (m_sreg & 0x203)) {
290
                                if (m_debug) printf("QSPI: Cannot program at this time, SREG = %x\n", m_sreg);
291
                                m_state = QSPIF_INVALID;
292
                        } else {
293
                                m_state = QSPIF_QPP;
294
                                if (m_debug) printf("QSPI: QUAD-PAGE-PROGRAM COMMAND ACCEPTED\n");
295
                                if (m_debug) printf("QSPI: pmem = %08lx\n", (unsigned long)m_pmem);
296
                        }
297
                        break;
298
                case 0x35: // Read configuration register
299
                        m_state = QSPIF_RDCR;
300
                        if (m_debug) printf("QSPI: READING CONFIGURATION REGISTER: %02x\n", m_creg);
301
                        QOREG(m_creg);
302
                        break;
303
                case 0x9f: // Read ID
304
                        m_state = QSPIF_RDID;
305
                        if (m_debug) printf("QSPI: READING ID, %02x\n", (DEVID>>24)&0x0ff);
306
                        QOREG(0xfe);
307
                        break;
308
                case 0xab: // Release from DEEP POWER DOWN
309
                        if (m_sreg & QSPIF_DEEP_POWER_DOWN_FLAG) {
310
                                if (m_debug) printf("QSPI: Release from deep power down\n");
311
                                m_sreg &= (~QSPIF_DEEP_POWER_DOWN_FLAG);
312
                                m_write_count = tRES;
313
                        } m_state = QSPIF_RELEASE;
314
                        break;
315
                case 0xb9: // DEEP POWER DOWN
316
                        if (0 != (m_sreg & 0x01)) {
317
                                if (m_debug) printf("QSPI: Cannot enter DEEP POWER DOWN, in middle of write/erase\n");
318
                                m_state = QSPIF_INVALID;
319
                        } else {
320
                                m_sreg  |= QSPIF_DEEP_POWER_DOWN_FLAG;
321
                                m_state  = QSPIF_IDLE;
322
                        }
323
                        break;
324
                case 0xc7: // Bulk Erase
325
                        if (2 != (m_sreg & 0x203)) {
326
                                if (m_debug) printf("QSPI: WEL not set, cannot erase device\n");
327
                                m_state = QSPIF_INVALID;
328
                        } else
329
                                m_state = QSPIF_BULK_ERASE;
330
                        break;
331
                case 0xd8: // Sector Erase
332
                        if (2 != (m_sreg & 0x203)) {
333
                                if (m_debug) printf("QSPI: WEL not set, cannot erase sector\n");
334
                                m_state = QSPIF_INVALID;
335
                        } else {
336
                                m_state = QSPIF_SECTOR_ERASE;
337
                                if (m_debug) printf("QSPI: SECTOR_ERASE COMMAND\n");
338
                        }
339
                        break;
340
                case 0x0eb: // Here's the (other) read that we support
341
                        // printf("QSPI: QUAD-I/O-READ\n");
342
                        m_state = QSPIF_QUAD_READ_CMD;
343
                        m_quad_mode = true;
344
                        break;
345
                default:
346
                        printf("QSPI: UNRECOGNIZED SPI FLASH CMD: %02x\n", m_ireg&0x0ff);
347
                        m_state = QSPIF_INVALID;
348
                        assert(0 && "Unrecognized command\n");
349
                        break;
350
                }
351
        } else if ((0 == (m_count&0x07))&&(m_count != 0)) {
352
                QOREG(0);
353
                switch(m_state) {
354
                case QSPIF_IDLE:
355
                        printf("TOO MANY CLOCKS, SPIF in IDLE\n");
356
                        break;
357
                case QSPIF_WRSR:
358
                        if (m_count == 16) {
359
                                m_sreg = (m_sreg & 0x061) | (m_ireg & 0x09c);
360
                                if (m_debug) printf("Request to set sreg to 0x%02x\n",
361
                                        m_ireg&0x0ff);
362
                        } else if (m_count == 24) {
363
                                m_creg = (m_creg & 0x0fd) | (m_ireg & 0x02);
364
                                if (m_debug) printf("Request to set creg to 0x%02x\n",
365
                                        m_ireg&0x0ff);
366
                        } else {
367
                                printf("TOO MANY CLOCKS FOR WRR!!!\n");
368
                                exit(-2);
369
                                m_state = QSPIF_IDLE;
370
                        }
371
                        break;
372
                case QSPIF_CLSR:
373
                        assert(0 && "Too many clocks for CLSR command!!\n");
374
                        break;
375
                case QSPIF_RDID:
376
                        if (m_count == 32) {
377
                                m_addr = m_ireg & 0x0ffffff;
378
                                if (m_debug) printf("READID, ADDR = %08x\n", m_addr);
379
                                QOREG((DEVID>>8));
380
                                if (m_debug) printf("QSPI: READING ID, %02x\n", (DEVID>>8)&0x0ff);
381
                        } else if (m_count > 32) {
382
                                if (((m_count-32)>>3)&1)
383
                                        QOREG((DEVID));
384
                                else
385
                                        QOREG((DEVID>>8));
386
                                if (m_debug) printf("QSPI: READING ID, %02x -- DONE\n", 0x00);
387
                        }
388
                        // m_oreg = (DEVID >> (2-(m_count>>3)-1)) & 0x0ff;
389
                        break;
390
                case QSPIF_RDSR:
391
                        // printf("Read SREG = %02x, wait = %08x\n", m_sreg,
392
                                // m_write_count);
393
                        QOREG(m_sreg);
394
                        break;
395
                case QSPIF_RDCR:
396
                        if (m_debug) printf("Read CREG = %02x\n", m_creg);
397
                        QOREG(m_creg);
398
                        break;
399
                case QSPIF_FAST_READ:
400
                        if (m_count == 32) {
401
                                m_addr = m_ireg & 0x0ffffff;
402
                                if (m_debug) printf("FAST READ, ADDR = %08x\n", m_addr);
403
                                QOREG(0x0c3);
404
                                assert((m_addr & 0xfc00000)==0);
405
                        } else if ((m_count >= 40)&&(0 == (m_sreg&0x01))) {
406
                                //if (m_count == 40)
407
                                        //printf("DUMMY BYTE COMPLETE ...\n");
408
                                QOREG(m_mem[m_addr++]);
409
                                // if (m_debug) printf("SPIF[%08x] = %02x\n", m_addr-1, m_oreg);
410
                        } else m_oreg = 0;
411
                        break;
412
                case QSPIF_QUAD_READ_CMD:
413
                        // The command to go into quad read mode took 8 bits
414
                        // that changes the timings, else we'd use quad_Read
415
                        // below
416
                        if (m_count == 32) {
417
                                m_addr = m_ireg & 0x0ffffff;
418
                                // printf("FAST READ, ADDR = %08x\n", m_addr);
419
                                // printf("QSPI: QUAD READ, ADDR = %06x\n", m_addr);
420
                                assert((m_addr & 0xfc00000)==0);
421
                        } else if (m_count == 32+24) {
422
                                m_mode_byte = (m_ireg>>16) & 0x0ff;
423
                                // printf("QSPI: MODE BYTE = %02x\n", m_mode_byte);
424
                        } else if ((m_count > 32+24)&&(0 == (m_sreg&0x01))) {
425
                                QOREG(m_mem[m_addr++]);
426
                                // printf("QSPIF[%08x]/QR = %02x\n",
427
                                        // m_addr-1, m_oreg);
428
                        } else m_oreg = 0;
429
                        break;
430
                case QSPIF_QUAD_READ:
431
                        if (m_count == 32) {
432
                                m_mode_byte = (m_ireg & 0x0ff);
433
                                // printf("QSPI/QR: MODE BYTE = %02x\n", m_mode_byte);
434
                        } else if ((m_count >= 32+16)&&(0 == (m_sreg&0x01))) {
435
                                QOREG(m_mem[m_addr++]);
436
                                // printf("QSPIF[%08x]/QR = %02x\n", m_addr-1, m_oreg & 0x0ff);
437
                        } else m_oreg = 0;
438
                        break;
439
                case QSPIF_PP:
440
                        if (m_count == 32) {
441
                                m_addr = m_ireg & 0x0ffffff;
442
                                if (m_debug) printf("QSPI: PAGE-PROGRAM ADDR = %06x\n", m_addr);
443
                                assert((m_addr & 0xfc00000)==0);
444
                                // m_page = m_addr >> 8;
445
                                for(int i=0; i<256; i++)
446
                                        m_pmem[i] = 0x0ff;
447
                        } else if (m_count >= 40) {
448
                                m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
449
                                // printf("QSPI: PMEM[%02x] = 0x%02x -> %02x\n", m_addr & 0x0ff, m_ireg & 0x0ff, (m_pmem[(m_addr & 0x0ff)]&0x0ff));
450
                                m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
451
                        } break;
452
                case QSPIF_QPP:
453
                        if (m_count == 32) {
454
                                m_addr = m_ireg & 0x0ffffff;
455
                                m_quad_mode = true;
456
                                if (m_debug) printf("QSPI/QR: PAGE-PROGRAM ADDR = %06x\n", m_addr);
457
                                assert((m_addr & 0xfc00000)==0);
458
                                // m_page = m_addr >> 8;
459
                                for(int i=0; i<256; i++)
460
                                        m_pmem[i] = 0x0ff;
461
                        } else if (m_count >= 40) {
462
                                m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
463
                                // printf("QSPI/QR: PMEM[%02x] = 0x%02x -> %02x\n", m_addr & 0x0ff, m_ireg & 0x0ff, (m_pmem[(m_addr & 0x0ff)]&0x0ff));
464
                                m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
465
                        } break;
466
                case QSPIF_SECTOR_ERASE:
467
                        if (m_count == 32) {
468
                                m_addr = m_ireg & 0x0ffc000;
469
                                if (m_debug) printf("SECTOR_ERASE ADDRESS = %08x\n", m_addr);
470
                                assert((m_addr & 0xfc00000)==0);
471
                        } break;
472
                case QSPIF_RELEASE:
473
                        if (m_count >= 32) {
474
                                QOREG(DEVESD);
475
                        } break;
476
                default:
477
                        break;
478
                }
479
        } // else printf("SFLASH->count = %d\n", m_count);
480
 
481
        m_last_sck = sck;
482
        if (m_quad_mode)
483
                return (m_oreg>>8)&0x0f;
484
        else
485
                // return ((m_oreg & 0x0100)?2:0) | (dat & 0x0d);
486
                return (m_oreg & 0x0100)?2:0;
487
}
488
 

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