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[/] [s6soc/] [trunk/] [rtl/] [Makefile] - Blame information for rev 16

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Line No. Rev Author Line
1 8 dgisselq
################################################################################
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#
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# Filename:     rtl/Makefile
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#
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# Project:      CMod S6 System on a Chip, ZipCPU demonstration project
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#
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# Purpose:      This makefile builds a verilator simulation of the zipsystem.
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#               It does not make the system within Vivado or Quartus.
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#
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# Creator:      Dan Gisselquist, Ph.D.
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#               Gisselquist Technology, LLC
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#
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################################################################################
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#
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# Copyright (C) 2015-2016, Gisselquist Technology, LLC
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#
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# This program is free software (firmware): you can redistribute it and/or
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# modify it under the terms of  the GNU General Public License as published
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# by the Free Software Foundation, either version 3 of the License, or (at
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# your option) any later version.
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#
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# This program is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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# for more details.
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#
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# You should have received a copy of the GNU General Public License along
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# with this program.  (It's in the $(ROOT)/doc directory, run make with no
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# target there if the PDF file isn't present.)  If not, see
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#  for a copy.
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#
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# License:      GPL, v3, as defined and found on www.gnu.org,
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#               http://www.gnu.org/licenses/gpl.html
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#
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#
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################################################################################
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#
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#
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.PHONY: all
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all: busmaster altbusmaster
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CPUD := cpu
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RAWZIP := zipbones.v zipcpu.v cpudefs.v                         \
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                prefetch.v idecode.v cpuops.v memops.v          \
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                wbdblpriarb.v
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ZIPSRC := $(addprefix $(CPUD)/,$(RAWZIP))
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BUSSRC := builddate.v llqspi.v wbicape6.v wbicapesimple.v wbscope.v     \
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        memdev.v rtclight.v spio.v wbgpio.v wbpwmaudio.v
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MAINSRC := busmaster.v builddate.v flash_config.v wbqspiflash.v \
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        $(BUSSRC) $(ZIPSRC)
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# toplevel.v rxuart.v txuart.v
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ALTSRC := altbusmaster.v builddate.v flash_config.v wbqspiflash.v       \
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        $(BUSSRC) wbdeppsimple.v
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# alttop.v rxuart.v txuart.v
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# rtcdate.v wbubus.v
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VOBJ := obj_dir
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$(VOBJ)/Vbusmaster.cpp: $(MAINSRC)
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        verilator -cc -y $(CPUD) busmaster.v
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$(VOBJ)/Vbusmaster.h: $(VOBJ)/Vbusmaster.cpp
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$(VOBJ)/Valtbusmaster.cpp: $(ALTSRC)
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        verilator -cc -y $(CPUD) altbusmaster.v
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$(VOBJ)/Valtbusmaster.h: $(VOBJ)/Valtbusmaster.cpp
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$(VOBJ)/Vbusmaster__ALL.a: $(VOBJ)/Vbusmaster.cpp $(VOBJ)/Vbusmaster.h
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        cd $(VOBJ); make --no-print-directory -f Vbusmaster.mk
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$(VOBJ)/Valtbusmaster__ALL.a: $(VOBJ)/Valtbusmaster.cpp $(VOBJ)/Valtbusmaster.h
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        cd $(VOBJ); make --no-print-directory -f Valtbusmaster.mk
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cpudefs.h: cpudefs.v
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        @echo "Building cpudefs.h"
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        @echo "// " > $@
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        @echo "// Do not edit this file, it is automatically generated!" >> $@
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        @echo "// To generate this file, \"make cpudefs.h\" in the rtl directory." >> $@
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        @echo "// " >> $@
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        @grep "^\`" $^ | sed -e '{ s/^`/#/ }' >> $@
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.PHONY: busmaster
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busmaster: $(VOBJ)/Vbusmaster__ALL.a
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.PHONY: altbusmaster
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altbusmaster: $(VOBJ)/Valtbusmaster__ALL.a
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.PHONY: clean
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clean:
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        rm -rf $(VOBJ) cpudefs.h

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