OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [altbusmaster.v] - Blame information for rev 32

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    altbusmaster.v
4
//
5
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6
//
7
// Purpose:     
8
//
9
// Creator:     Dan Gisselquist, Ph.D.
10
//              Gisselquist Technology, LLC
11
//
12
////////////////////////////////////////////////////////////////////////////////
13
//
14
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
15
//
16
// This program is free software (firmware): you can redistribute it and/or
17
// modify it under the terms of  the GNU General Public License as published
18
// by the Free Software Foundation, either version 3 of the License, or (at
19
// your option) any later version.
20
//
21
// This program is distributed in the hope that it will be useful, but WITHOUT
22
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
23
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
24
// for more details.
25
//
26
// You should have received a copy of the GNU General Public License along
27
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
28
// target there if the PDF file isn't present.)  If not, see
29
// <http://www.gnu.org/licenses/> for a copy.
30
//
31
// License:     GPL, v3, as defined and found on www.gnu.org,
32
//              http://www.gnu.org/licenses/gpl.html
33
//
34
//
35
////////////////////////////////////////////////////////////////////////////////
36
//
37
//
38
//
39
`include "builddate.v"
40
//
41 11 dgisselq
// `define      IMPLEMENT_ONCHIP_RAM
42 5 dgisselq
`ifndef VERILATOR
43
`define FANCY_ICAP_ACCESS
44
`endif
45
`define FLASH_ACCESS
46 8 dgisselq
`define DBG_SCOPE       // About 204 LUTs, at 2^6 addresses
47 25 dgisselq
// `define      COMPRESSED_SCOPE
48
`define INCLUDE_SECOND_TIMER
49
`define SECOND_TIMER_IS_WATCHDOG
50 8 dgisselq
`define INCLUDE_RTC     // About 90 LUTs
51 25 dgisselq
`define FULL_BUSERR_CALCULATION
52 11 dgisselq
`define WBUBUS
53 5 dgisselq
module  altbusmaster(i_clk, i_rst,
54 8 dgisselq
                // DEPP I/O Control
55
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
56
                        i_depp_data, o_depp_data, o_depp_wait,
57
                // External UART interface
58 5 dgisselq
                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
59 13 dgisselq
                        o_uart_cts,
60 5 dgisselq
                // The SPI Flash lines
61
                o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
62
                // The board I/O
63
                i_btn, o_led, o_pwm, o_pwm_aux,
64
                // Keypad connections
65
                i_kp_row, o_kp_col,
66
                // UART control
67
                o_uart_setup,
68
                // GPIO lines
69
                i_gpio, o_gpio);
70 8 dgisselq
        parameter       BUS_ADDRESS_WIDTH=23,
71
                        BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
72 5 dgisselq
        input                   i_clk, i_rst;
73 8 dgisselq
        // The bus commander, via an external DEPP port
74
        input                   i_depp_astb_n, i_depp_dstb_n, i_depp_write_n;
75
        input   wire    [7:0]    i_depp_data;
76
        output  wire    [7:0]    o_depp_data;
77
        output  wire            o_depp_wait;
78
        // Serial inputs
79 5 dgisselq
        input                   i_rx_stb;
80
        input           [7:0]    i_rx_data;
81 8 dgisselq
        output  reg             o_tx_stb;
82
        output  reg     [7:0]    o_tx_data;
83 5 dgisselq
        input                   i_tx_busy;
84 13 dgisselq
        output  wire            o_uart_cts;
85 5 dgisselq
        // SPI flash control
86
        output  wire            o_qspi_cs_n, o_qspi_sck;
87
        output  wire    [3:0]    o_qspi_dat;
88
        input           [3:0]    i_qspi_dat;
89
        output  wire    [1:0]    o_qspi_mod;
90
        // Board I/O
91
        input           [1:0]    i_btn;
92
        output  wire    [3:0]    o_led;
93
        output  wire            o_pwm;
94
        output  wire    [1:0]    o_pwm_aux;
95
        // Keypad
96
        input           [3:0]    i_kp_row;
97
        output  wire    [3:0]    o_kp_col;
98
        // UART control
99
        output  wire    [29:0]   o_uart_setup;
100
        // GPIO liines
101
        input           [15:0]   i_gpio;
102
        output  wire    [15:0]   o_gpio;
103
 
104
 
105
        //
106
        //
107
        // Master wishbone wires
108
        //
109
        //
110
        wire            wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
111 8 dgisselq
        wire    [31:0]   wb_data, wb_idata, w_wbu_addr;
112 5 dgisselq
        wire    [(BAW-1):0]      wb_addr;
113
        wire    [5:0]            io_addr;
114
        assign  io_addr = {
115
                        wb_addr[22],    // Flash
116
                        wb_addr[13],    // RAM
117
                        wb_addr[11],    // RTC
118
                        wb_addr[10],    // CFG
119
                        wb_addr[ 9],    // SCOPE
120
                        wb_addr[ 8] };  // I/O
121
 
122
        // Wires going to devices
123
        // And then headed back home
124
        wire    w_interrupt;
125 8 dgisselq
`ifdef  WBUBUS
126 5 dgisselq
        //
127
        //
128
        // The BUS master (source): The WB to UART conversion bus
129
        //
130
        //
131 11 dgisselq
        wire            dep_rx_stb, dep_tx_stb, dep_tx_busy;
132
        wire    [7:0]    dep_rx_data, dep_tx_data;
133
        deppbyte        deppdrive(i_clk,
134
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
135
                        i_depp_data, o_depp_data, o_depp_wait,
136
                dep_rx_stb, dep_rx_data,
137
                dep_tx_stb, dep_tx_data, dep_tx_busy);
138
 
139
        wbubus busbdriver(i_clk,
140
                        // i_rx_stb, i_rx_data,         // UART control
141
                        dep_rx_stb, dep_rx_data,        // DEPP control
142 5 dgisselq
                        // The wishbone interface
143
                        wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
144
                                wb_ack, wb_stall, wb_err, wb_idata,
145
                        w_interrupt,
146 11 dgisselq
                        // Provide feedback to the DEPP interface
147
                        dep_tx_stb, dep_tx_data, dep_tx_busy);
148
//                      // Provide feedback to the UART
149
//                      o_tx_stb, o_tx_data, i_tx_busy
150
        // assign       o_uart_rts = (~rx_rdy);
151 8 dgisselq
`else
152
        //
153
        //
154
        // Another BUS master (source): A conversion from DEPP to busmaster
155
        //
156
        //
157
        wbdeppsimple    deppdrive(i_clk,
158
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
159
                        i_depp_data, o_depp_data, o_depp_wait,
160
                wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
161
                        wb_ack, wb_stall, wb_err, wb_idata,
162
                        w_interrupt);
163
`endif
164 5 dgisselq
 
165
        generate
166 8 dgisselq
        if (BAW < 32)
167
                assign  wb_addr = w_wbu_addr[(BAW-1):0];
168 5 dgisselq
        else
169 8 dgisselq
                assign  wb_addr = w_wbu_addr;
170 5 dgisselq
        endgenerate
171
 
172
        wire    io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
173
                        rtc_sel, none_sel, many_sel;
174 25 dgisselq
        wire    flash_ack, scop_ack, cfg_ack, mem_ack, many_ack;
175 5 dgisselq
        wire    rtc_ack, rtc_stall;
176
`ifdef  INCLUDE_RTC
177
        assign  rtc_stall = 1'b0;
178
`endif
179
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
180 8 dgisselq
        reg     io_ack;
181 5 dgisselq
 
182
        wire    [31:0]   flash_data, scop_data, cfg_data, mem_data, pwm_data,
183
                        spio_data, gpio_data, uart_data;
184
        reg     [31:0]   io_data;
185
        reg     [(BAW-1):0]      bus_err_addr;
186
 
187
        assign  wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
188
`ifdef  INCLUDE_RTC
189
                                ||(rtc_ack)
190
`endif
191
                                ||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
192
        assign  wb_stall = ((io_sel)&&(io_stall))
193
                        ||((scop_sel)&&(scop_stall))
194
                        ||((cfg_sel)&&(cfg_stall))
195
                        ||((mem_sel)&&(mem_stall))
196
`ifdef  INCLUDE_RTC
197
                        ||((rtc_sel)&&(rtc_stall))
198
`endif
199
                        ||((flash_sel||flctl_sel)&&(flash_stall));
200
                        // (none_sel)&&(1'b0)
201
 
202
        /*
203
        assign  wb_idata = (io_ack)?io_data
204
                        : ((scop_ack)?scop_data
205
                        : ((cfg_ack)?cfg_data
206
                        : ((mem_ack)?mem_data
207
                        : ((flash_ack)?flash_data
208
                        : 32'h00))));
209
        */
210
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
211
                        : ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
212 8 dgisselq
                        : ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
213 5 dgisselq
        assign  wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
214
 
215
        // Addresses ...
216
        //      0000 xxxx       configuration/control registers
217
        //      1 xxxx xxxx xxxx xxxx xxxx      Up-sampler taps
218
        assign  io_sel   =((wb_cyc)&&(io_addr[5:0]==6'h1));
219 8 dgisselq
        assign  scop_sel =((wb_cyc)&&(io_addr[5:0]==6'h2));
220
        assign  flctl_sel=((wb_cyc)&&(io_addr[5:0]==6'h3));
221
        assign  cfg_sel  =((wb_cyc)&&(io_addr[5:1]==5'h2));
222 5 dgisselq
        // zip_sel is not on the bus at this point
223
`ifdef  INCLUDE_RTC
224
        assign  rtc_sel  =((wb_cyc)&&(io_addr[5:3]==3'h1));
225
`endif
226
        assign  mem_sel  =((wb_cyc)&&(io_addr[5:4]==2'h1));
227
        assign  flash_sel=((wb_cyc)&&(io_addr[5]));
228
 
229 25 dgisselq
`ifdef  FULL_BUSERR_CALCULATION
230
        assign  none_sel =((wb_cyc)&&(wb_stb)&&
231
                        ((io_addr==6'h0)
232
                        ||((~io_addr[5])&&(|wb_addr[22:14]))
233
                        ||((io_addr[5:4]==2'b00)&&(|wb_addr[12])))
234
                        );
235 5 dgisselq
        assign  many_sel =((wb_cyc)&&(wb_stb)&&(
236
                         {3'h0, io_sel}
237
                        +{3'h0, flctl_sel}
238 8 dgisselq
                        +{3'h0, scop_sel}
239 5 dgisselq
                        +{3'h0, cfg_sel}
240 8 dgisselq
                        +{3'h0, rtc_sel}
241 5 dgisselq
                        +{3'h0, mem_sel}
242
                        +{3'h0, flash_sel} > 1));
243
 
244
        assign  many_ack =((wb_cyc)&&(
245
                         {3'h0, io_ack}
246
                        +{3'h0, scop_ack}
247
                        +{3'h0, cfg_ack}
248
`ifdef  INCLUDE_RTC
249
                        +{3'h0, rtc_ack}
250
`endif
251
                        +{3'h0, mem_ack}
252
                        +{3'h0, flash_ack} > 1));
253 25 dgisselq
`else
254
        assign  many_ack = 1'b0;
255
        assign  many_sel = 1'b0;
256
        assign  none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
257
`endif
258 5 dgisselq
        wire            flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
259
                        rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
260
 
261
 
262
        //
263
        //
264
        //
265
        reg             rx_rdy;
266 11 dgisselq
        wire    [11:0]   int_vector;
267 25 dgisselq
        assign  int_vector = {
268
                                flash_interrupt, gpio_int, pwm_int, keypad_int,
269 13 dgisselq
                                (~o_tx_stb), rx_rdy,
270
                                tmrb_int, tmra_int,
271 5 dgisselq
                                rtc_interrupt, scop_interrupt,
272
                                wb_err, button_int };
273
 
274
        wire    [31:0]   pic_data;
275 11 dgisselq
        icontrol #(12)  pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
276 5 dgisselq
                                        &&(wb_addr[3:0]==4'h0)&&(wb_we),
277
                        wb_data, pic_data, int_vector, w_interrupt);
278
 
279 8 dgisselq
        initial bus_err_addr = 0; // `DATESTAMP;
280 5 dgisselq
        always @(posedge i_clk)
281
                if (wb_err)
282
                        bus_err_addr <= wb_addr;
283
 
284 11 dgisselq
        wire    [31:0]   timer_a, timer_b;
285 5 dgisselq
        wire            zta_ack, zta_stall, ztb_ack, ztb_stall;
286 25 dgisselq
        ziptimer        #(32,31,1)
287 8 dgisselq
                zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
288 25 dgisselq
`ifdef  INCLUDE_SECOND_TIMER
289 5 dgisselq
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
290 25 dgisselq
`else
291
                                (wb_stb)&&(io_sel)&&(wb_addr[3:1]==3'h1),
292
`endif
293 5 dgisselq
                                wb_we, wb_data, zta_ack, zta_stall, timer_a,
294
                                tmra_int);
295 25 dgisselq
`ifdef  INCLUDE_SECOND_TIMER
296
`ifdef  SECOND_TIMER_IS_WATCHDOG
297
        ziptimer        #(32,31,0)
298 8 dgisselq
                zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
299 5 dgisselq
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
300
                                wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
301
                                tmrb_int);
302 25 dgisselq
`else
303
        ziptimer        #(32,31,1)
304
                zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
305
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
306
                                wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
307
                                tmrb_int);
308
`endif
309
`else
310
        // assign       timer_b = 32'h000;
311
        assign  timer_b = timer_a;
312
        assign  tmrb_int = 1'b0;
313
`endif
314 5 dgisselq
 
315
        wire    [31:0]   rtc_data;
316
`ifdef  INCLUDE_RTC
317
        wire    rtcd_ack, rtcd_stall, ppd;
318
        // rtcdate      thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
319
                        // wb_data, rtcd_ack, rtcd_stall, date_data);
320
        reg     r_rtc_ack;
321
        initial r_rtc_ack = 1'b0;
322
        always @(posedge i_clk)
323
                r_rtc_ack <= ((wb_stb)&&(rtc_sel));
324
        assign  rtc_ack = r_rtc_ack;
325
 
326
        rtclight
327 8 dgisselq
                #(23'h35afe5,23,0,0)      // 80 MHz clock
328 5 dgisselq
                thetime(i_clk, wb_cyc,
329
                        ((wb_stb)&&(rtc_sel)), wb_we,
330
                        { 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
331
                        rtc_interrupt, ppd);
332
`else
333
        assign  rtc_interrupt = 1'b0;
334
        assign  rtc_data = 32'h00;
335
        assign  rtc_ack  = 1'b0;
336
`endif
337
 
338
        always @(posedge i_clk)
339
                case(wb_addr[3:0])
340
                        4'h0: io_data <= pic_data;
341
                        4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr };
342
                        4'h2: io_data <= timer_a;
343
                        4'h3: io_data <= timer_b;
344
                        4'h4: io_data <= pwm_data;
345
                        4'h5: io_data <= spio_data;
346
                        4'h6: io_data <= gpio_data;
347
                        4'h7: io_data <= uart_data;
348
                        default: io_data <= `DATESTAMP;
349
                        // 4'h8: io_data <= `DATESTAMP;
350
                endcase
351
        always @(posedge i_clk)
352
                io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel);
353
        assign  io_stall = 1'b0;
354
 
355
        wire    pwm_ack, pwm_stall;
356 13 dgisselq
        wbpwmaudio      #(14'd10000,2,0,14)
357
                theaudio(i_clk, wb_cyc,
358
                                ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)),
359
                                        wb_we, 1'b0, wb_data,
360
                                pwm_ack, pwm_stall, pwm_data, o_pwm,
361
                                        o_pwm_aux, //={pwm_shutdown_n,pwm_gain}
362
                                        pwm_int);
363 5 dgisselq
 
364
        //
365
        // Special Purpose I/O: Keypad, button, LED status and control
366
        //
367 25 dgisselq
        wire    [3:0]    w_led;
368 5 dgisselq
        spio    thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
369 25 dgisselq
                        wb_data, spio_data, o_kp_col, i_kp_row, i_btn, w_led,
370 5 dgisselq
                        keypad_int, button_int);
371 32 dgisselq
        assign  o_led = { w_led[3]|w_interrupt,w_led[2],w_led[1:0] };
372 5 dgisselq
 
373
        //
374
        // General purpose (sort of) I/O:  (Bottom two bits robbed in each
375
        // direction for an I2C link at the toplevel.v design)
376
        //
377
        wbgpio  #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
378
                        (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
379
                        wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
380
 
381
        //
382
        //
383
        //      Rudimentary serial port control
384
        //
385
        reg     [7:0]    r_rx_data;
386
        // Baud rate is set by clock rate / baud rate.
387
        // Thus, 80MHz / 115200MBau
388
        //      = 694.4, or about 0x2b6. 
389
        // although the CPU might struggle to keep up at this speed without a
390
        // hardware buffer.
391
        //
392
        // We'll add the flag for two stop bits.
393 8 dgisselq
        // assign       o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
394
        assign  o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1
395 5 dgisselq
 
396 8 dgisselq
        initial o_tx_stb = 1'b0;
397
        initial o_tx_data = 8'h00;
398
        always @(posedge i_clk)
399
                if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
400
                begin
401
                        o_tx_data <= wb_data[7:0];
402
                        o_tx_stb <= 1'b1;
403
                end
404
                else if ((o_tx_stb)&&(~i_tx_busy))
405
                        o_tx_stb <= 1'b0;
406
        initial rx_rdy = 1'b0;
407
        always @(posedge i_clk)
408
                if (i_rx_stb)
409
                        r_rx_data <= i_rx_data;
410
        always @(posedge i_clk)
411
        begin
412
                if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
413
                        rx_rdy <= i_rx_stb;
414
                else if (i_rx_stb)
415
                        rx_rdy <= (rx_rdy | i_rx_stb);
416
        end
417 13 dgisselq
        assign  o_uart_cts = (~rx_rdy);
418 8 dgisselq
        assign  uart_data = { 23'h0, ~rx_rdy, r_rx_data };
419
        //
420
        // uart_ack gets returned as part of io_ack, since that happens when
421
        // io_sel and wb_stb are defined
422
        //
423
        // always @(posedge i_clk)
424
                // uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
425 5 dgisselq
 
426
 
427
 
428
        //
429
        //      FLASH MEMORY CONFIGURATION ACCESS
430
        //
431
        wbqspiflashp #(24)      flashmem(i_clk,
432 11 dgisselq
                wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
433 8 dgisselq
                        wb_addr[(24-3):0], wb_data,
434 5 dgisselq
                flash_ack, flash_stall, flash_data,
435
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
436
                flash_interrupt);
437
 
438
        //
439
        //      MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
440
        //
441
        wire    [31:0]   cfg_scope;
442
`ifdef  FANCY_ICAP_ACCESS
443
        wbicape6        fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
444
                                wb_addr[5:0], wb_data,
445
                                cfg_ack, cfg_stall, cfg_data,
446
                                cfg_scope);
447
`else
448
        reg     r_cfg_ack;
449
        always @(posedge i_clk)
450
                r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb);
451
        assign  cfg_ack   = r_cfg_ack;
452
        assign  cfg_stall = 1'b0;
453
        assign  cfg_data  = 32'h00;
454
        assign  cfg_scope = 32'h00;
455
`endif
456
 
457
 
458
        //
459
        //      ON-CHIP RAM MEMORY ACCESS
460
        //
461 8 dgisselq
`ifdef  IMPLEMENT_ONCHIP_RAM
462 5 dgisselq
        memdev  #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
463
                        wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
464 8 dgisselq
`else
465
        assign  mem_data = 32'h00;
466
        assign  mem_stall = 1'b0;
467
        reg     r_mem_ack;
468
        always @(posedge i_clk)
469
                r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
470
        assign  mem_ack = r_mem_ack;
471
`endif
472 5 dgisselq
 
473
        //
474
        //
475
        //      WISHBONE SCOPE
476
        //
477
        //
478
        //
479
        //
480
        wire    [31:0]   scop_cfg_data;
481
        wire            scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
482 8 dgisselq
`ifdef  DBG_SCOPE
483 5 dgisselq
        wire            scop_cfg_trigger;
484
        assign  scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
485 25 dgisselq
        wire    scop_trigger = scop_cfg_trigger;
486
`ifdef  COMPRESSED_SCOPE
487
        wbscopc #(5'ha)
488
`else
489
        wbscope #(5'ha)
490
`endif
491
        wbcfgscope(i_clk, 1'b1, scop_trigger,
492
                cfg_scope,
493 5 dgisselq
                // Wishbone interface
494 8 dgisselq
                i_clk, wb_cyc, (wb_stb)&&(scop_sel),
495 5 dgisselq
                                wb_we, wb_addr[0], wb_data,
496
                        scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
497
                scop_cfg_interrupt);
498 8 dgisselq
`else
499
        reg     r_scop_cfg_ack;
500
        always @(posedge i_clk)
501
                r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
502
        assign  scop_cfg_ack = r_scop_cfg_ack;
503
        assign  scop_cfg_data = 32'h000;
504
        assign  scop_cfg_stall= 1'b0;
505 5 dgisselq
`endif
506
 
507
        assign  scop_interrupt = scop_cfg_interrupt;
508
        assign  scop_ack   = scop_cfg_ack;
509
        assign  scop_stall = scop_cfg_stall;
510
        assign  scop_data  = scop_cfg_data;
511
 
512
endmodule
513
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.