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[/] [s6soc/] [trunk/] [rtl/] [altbusmaster.v] - Blame information for rev 53

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1 5 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    altbusmaster.v
4
//
5
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6
//
7 46 dgisselq
// Purpose:     Because the S6 is *so* small logic-wise, the logic of setting up
8
//              a project/design was separated from the logic of the design
9
//      itself.  Hence, this is the "setup" design.  It allows us to test various
10
//      components from the command line interface, as well as erasing and 
11
//      programming the flash in order to set up the actual device interface.
12 5 dgisselq
//
13
// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
15
//
16
////////////////////////////////////////////////////////////////////////////////
17
//
18 46 dgisselq
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
19 5 dgisselq
//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
29
//
30
// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
33
// <http://www.gnu.org/licenses/> for a copy.
34
//
35
// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
38
//
39
////////////////////////////////////////////////////////////////////////////////
40
//
41
//
42
`include "builddate.v"
43
//
44 11 dgisselq
// `define      IMPLEMENT_ONCHIP_RAM
45 5 dgisselq
`define FLASH_ACCESS
46 51 dgisselq
`define DBG_SCOPE       // About 204 LUTs, at 2^6 addresses
47 25 dgisselq
// `define      COMPRESSED_SCOPE
48 11 dgisselq
`define WBUBUS
49 51 dgisselq
// `define      LOWLOGIC_FLASH
50 5 dgisselq
module  altbusmaster(i_clk, i_rst,
51 8 dgisselq
                // DEPP I/O Control
52
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
53
                        i_depp_data, o_depp_data, o_depp_wait,
54
                // External UART interface
55 5 dgisselq
                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
56 46 dgisselq
                        o_uart_rts_n,
57 5 dgisselq
                // The SPI Flash lines
58
                o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
59
                // The board I/O
60
                i_btn, o_led, o_pwm, o_pwm_aux,
61
                // Keypad connections
62
                i_kp_row, o_kp_col,
63
                // UART control
64
                o_uart_setup,
65
                // GPIO lines
66
                i_gpio, o_gpio);
67 51 dgisselq
        parameter       BUS_ADDRESS_WIDTH=23;
68
        localparam      BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
69 46 dgisselq
        // 2^14 bytes requires a LGMEMSZ of 14, and 12 address bits ranging from
70
        // 0 to 11.  As with many other devices, the wb_cyc line is more for
71
        // form than anything else--it is ignored by the memory itself.
72
        localparam      LGMEMSZ=14;     // Takes 8 BLKRAM16 elements for LGMEMSZ=14
73
        // As with the memory size, the flash size is also measured in log_2 of
74
        // the number of bytes.
75
        localparam      LGFLASHSZ = 24;
76 5 dgisselq
        input                   i_clk, i_rst;
77 8 dgisselq
        // The bus commander, via an external DEPP port
78
        input                   i_depp_astb_n, i_depp_dstb_n, i_depp_write_n;
79
        input   wire    [7:0]    i_depp_data;
80
        output  wire    [7:0]    o_depp_data;
81
        output  wire            o_depp_wait;
82
        // Serial inputs
83 5 dgisselq
        input                   i_rx_stb;
84
        input           [7:0]    i_rx_data;
85 8 dgisselq
        output  reg             o_tx_stb;
86
        output  reg     [7:0]    o_tx_data;
87 5 dgisselq
        input                   i_tx_busy;
88 46 dgisselq
        output  wire            o_uart_rts_n;
89 5 dgisselq
        // SPI flash control
90 51 dgisselq
        output  wire            o_qspi_cs_n;
91
`ifdef  LOWLOGIC_FLASH
92
        output  wire    [1:0]    o_qspi_sck;
93
`else   // LOWLOGIC_FLASH
94
        output  wire            o_qspi_sck;
95
`endif  // LOWLOGIC_FLASH
96 5 dgisselq
        output  wire    [3:0]    o_qspi_dat;
97
        input           [3:0]    i_qspi_dat;
98
        output  wire    [1:0]    o_qspi_mod;
99
        // Board I/O
100
        input           [1:0]    i_btn;
101
        output  wire    [3:0]    o_led;
102
        output  wire            o_pwm;
103
        output  wire    [1:0]    o_pwm_aux;
104
        // Keypad
105
        input           [3:0]    i_kp_row;
106
        output  wire    [3:0]    o_kp_col;
107
        // UART control
108 46 dgisselq
        output  wire    [30:0]   o_uart_setup;
109 5 dgisselq
        // GPIO liines
110
        input           [15:0]   i_gpio;
111
        output  wire    [15:0]   o_gpio;
112
 
113
 
114
        //
115
        //
116
        // Master wishbone wires
117
        //
118
        //
119
        wire            wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
120 8 dgisselq
        wire    [31:0]   wb_data, wb_idata, w_wbu_addr;
121 5 dgisselq
        wire    [(BAW-1):0]      wb_addr;
122
 
123
        // Wires going to devices
124
        // And then headed back home
125
        wire    w_interrupt;
126 8 dgisselq
`ifdef  WBUBUS
127 5 dgisselq
        //
128
        //
129
        // The BUS master (source): The WB to UART conversion bus
130
        //
131
        //
132 11 dgisselq
        wire            dep_rx_stb, dep_tx_stb, dep_tx_busy;
133
        wire    [7:0]    dep_rx_data, dep_tx_data;
134
        deppbyte        deppdrive(i_clk,
135
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
136
                        i_depp_data, o_depp_data, o_depp_wait,
137
                dep_rx_stb, dep_rx_data,
138
                dep_tx_stb, dep_tx_data, dep_tx_busy);
139
 
140 46 dgisselq
        wire    bus_dbg;
141
        wbubus #(22) busbdriver(i_clk,
142 11 dgisselq
                        // i_rx_stb, i_rx_data,         // UART control
143
                        dep_rx_stb, dep_rx_data,        // DEPP control
144 5 dgisselq
                        // The wishbone interface
145
                        wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
146
                                wb_ack, wb_stall, wb_err, wb_idata,
147
                        w_interrupt,
148 11 dgisselq
                        // Provide feedback to the DEPP interface
149 46 dgisselq
                        dep_tx_stb, dep_tx_data, dep_tx_busy,
150
                        bus_dbg);
151 11 dgisselq
//                      // Provide feedback to the UART
152
//                      o_tx_stb, o_tx_data, i_tx_busy
153
        // assign       o_uart_rts = (~rx_rdy);
154 46 dgisselq
 
155
        wire    [30:0]   bus_debug;
156
        assign  bus_debug = {
157
                        wb_cyc, wb_stb, wb_ack, wb_stall,
158
                        wb_addr[7:0],
159
                        dep_rx_stb, (~dep_tx_busy)&&(dep_tx_stb), dep_tx_stb,
160
                        dep_rx_data, dep_tx_data };
161 8 dgisselq
`else
162
        //
163
        //
164
        // Another BUS master (source): A conversion from DEPP to busmaster
165
        //
166
        //
167
        wbdeppsimple    deppdrive(i_clk,
168
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
169
                        i_depp_data, o_depp_data, o_depp_wait,
170
                wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
171
                        wb_ack, wb_stall, wb_err, wb_idata,
172
                        w_interrupt);
173
`endif
174 5 dgisselq
 
175 46 dgisselq
        assign  wb_addr = w_wbu_addr[(BAW-1):0];
176 5 dgisselq
 
177 46 dgisselq
 
178
        // Signals to build/detect bus errors
179
        wire    none_sel, many_sel;
180
 
181
        wire    io_sel, flash_sel, flctl_sel, scop_sel, mem_sel;
182 51 dgisselq
        wire    flash_ack, scop_ack, mem_ack, many_ack;
183
        wire    io_stall, flash_stall, scop_stall, mem_stall;
184 8 dgisselq
        reg     io_ack;
185 5 dgisselq
 
186 51 dgisselq
        wire    [31:0]   flash_data, scop_data, mem_data, pwm_data,
187 5 dgisselq
                        spio_data, gpio_data, uart_data;
188
        reg     [31:0]   io_data;
189
        reg     [(BAW-1):0]      bus_err_addr;
190 46 dgisselq
        //
191
        // wb_ack
192
        //
193
        // The returning wishbone ack is equal to the OR of every component that
194
        // might possibly produce an acknowledgement, gated by the CYC line.  To
195
        // add new components, OR their acknowledgements in here.
196
        //
197
        // Note the reference to none_sel.  If nothing is selected, the result
198
        // is an error.  Here, we do nothing more than insure that the erroneous
199
        // request produces an ACK ... if it was ever made, rather than stalling
200
        // the bus.
201
        //
202 5 dgisselq
 
203 46 dgisselq
 
204
        assign  wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)
205 5 dgisselq
                                ||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
206 46 dgisselq
 
207
        //
208
        // wb_stall
209
        //
210
        // The returning wishbone stall line really depends upon what device
211
        // is requested.  Thus, if a particular device is selected, we return
212
        // the stall line for that device.
213
        //
214
        // To add a new device, simply and that devices select and stall lines
215
        // together, and OR the result with the massive OR logic below.
216
        //
217 5 dgisselq
        assign  wb_stall = ((io_sel)&&(io_stall))
218
                        ||((scop_sel)&&(scop_stall))
219
                        ||((mem_sel)&&(mem_stall))
220
                        ||((flash_sel||flctl_sel)&&(flash_stall));
221
                        // (none_sel)&&(1'b0)
222
 
223 46 dgisselq
        //
224
        // wb_idata
225
        //
226
        // This is the data returned on the bus.  Here, we select between a
227
        // series of bus sources to select what data to return.  The basic
228
        // logic is simply this: the data we return is the data for which the
229
        // ACK line is high.
230
        //
231
        // The last item on the list is chosen by default if no other ACK's are
232
        // true.  Although we might choose to return zeros in that case, by
233
        // returning something we can skimp a touch on the logic.
234
        //
235
        // To add another device, add another ack check, and another closing
236
        // parenthesis.
237
        //
238 5 dgisselq
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
239 46 dgisselq
                        : ((mem_ack)?(mem_data)
240
                        : flash_data);
241 5 dgisselq
 
242 46 dgisselq
        //
243
        // wb_err
244
        //
245
        // This is the bus error signal.  It should never be true, but practice
246
        // teaches us otherwise.  Here, we allow for three basic errors:
247
        //
248
        // 1. STB is true, but no devices are selected
249
        //
250
        //      This is the null pointer reference bug.  If you try to access
251
        //      something on the bus, at an address with no mapping, the bus
252
        //      should produce an error--such as if you try to access something
253
        //      at zero.
254
        //
255
        // 2. STB is true, and more than one device is selected
256
        //
257
        //      (This can be turned off, if you design this file well.  For
258
        //      this line to be true means you have a design flaw.)
259
        //
260
        // 3. If more than one ACK is every true at any given time.
261
        //
262
        //      This is a bug of bus usage, combined with a subtle flaw in the
263
        //      WB pipeline definition.  You can issue bus requests, one per
264
        //      clock, and if you cross device boundaries with your requests,
265
        //      you may have things come back out of order (not detected here)
266
        //      or colliding on return (detected here).  The solution to this
267
        //      problem is to make certain that any burst request does not cross
268
        //      device boundaries.  This is a requirement of whoever (or
269
        //      whatever) drives the bus.
270
        //
271
        assign  wb_err = ((wb_stb)&&(none_sel || many_sel)) || many_ack;
272
 
273 5 dgisselq
        // Addresses ...
274 46 dgisselq
        //
275
        // dev_sel
276
        //
277
        // The device select lines
278
        //
279
        //
280 5 dgisselq
 
281
 
282 46 dgisselq
        //
283
        // The skipaddr bitfield below is our cheaters way of handling
284
        // device selection.  We grab particular wires from the bus to do
285
        // this, and ignore all others.  While this may lead to some
286
        // surprising results for the CPU when it tries to access an
287
        // inappropriate address, it also minimizes our logic while also
288
        // placing every address at the right address.  The only problem is
289
        // ... devices will also be at some unexpected addresses, but ... this
290
        // is still within our spec.
291
        //
292
        wire    [3:0]    skipaddr;
293
        assign  skipaddr = {
294
                        wb_addr[(LGFLASHSZ-2)], // Flash
295
                        wb_addr[(LGMEMSZ-2)],   // RAM
296
                        wb_addr[ 9],            // SCOPE
297
                        wb_addr[ 8] };          // I/O
298
        //
299
        // This might not be the most efficient way in hardware, but it will
300
        // work for our purposes here.  There are two phantom bits for each
301
        // of these ... bits that tell the CPU which byte within the word, and
302
        // another phantom bit because we allocated a minimum of two words to
303
        // every device.
304
        //
305
        wire    idle_n;
306
`ifdef  ZERO_ON_IDLE
307
        assign idle_n = wb_stb;
308
`else
309
        assign idle_n = 1'b1;
310 5 dgisselq
`endif
311 46 dgisselq
 
312
// `define ZERO_ON_IDLE
313
`ifdef  ZERO_ON_IDLE
314
        assign  idle_n = (wb_cyc)&&(wb_stb);
315 25 dgisselq
`else
316 46 dgisselq
        assign  idle_n = 1'b1;
317
`endif
318 51 dgisselq
        assign  io_sel   = ((idle_n)&&(skipaddr[3:0]==4'b00_01));
319
`ifdef  LOWLOGIC_FLASH
320
        assign  scop_sel = ((idle_n)&&(skipaddr[3:1]==3'b00_1)); // = 4'h2
321
        assign  flctl_sel= 1'b0; // The lowlogic flash has no control registers
322
`else   // LOWLOGIC_FLASH
323
        assign  scop_sel = ((idle_n)&&(skipaddr[3:0]==4'b00_10)); // = 4'h2
324
        assign  flctl_sel= ((wb_cyc)&&(skipaddr[3:0]==4'b00_11));
325
`endif  // LOWLOGIC_FLASH
326
        assign  mem_sel  = ((idle_n)&&(skipaddr[3:2]==2'b01));
327
        assign  flash_sel= ((idle_n)&&(skipaddr[3]));
328 46 dgisselq
 
329
        //
330
        // none_sel
331
        //
332
        // This wire is true if wb_stb is true and no device is selected.  This
333
        // is an error condition, but here we present the logic to test for it.
334
        //
335
        //
336
        // If you add another device, add another OR into the select lines
337
        // associated with this term.
338
        //
339
        assign  none_sel =((wb_stb)&&(skipaddr==4'h0));
340
 
341
        //
342
        // many_sel
343
        //
344
        // This should *never* be true .... unless you mess up your address
345
        // decoding logic.  Since I've done that before, I test/check for it
346
        // here.
347
        //
348
        // To add a new device here, simply add it to the list.  Make certain
349
        // that the width of the add, however, is greater than the number
350
        // of devices below.  Hence, for 3 devices, you will need an add
351
        // at least 3 bits in width, for 7 devices you will need at least 4
352
        // bits, etc.
353
        //
354
        // Because this add uses the {} operator, the individual components to
355
        // it are by default unsigned ... just as we would like.
356
        //
357
        // There's probably another easier/better/faster/cheaper way to do this,
358
        // but I haven't found any such that are also easier to adjust with
359
        // new devices.  I'm open to options.
360
        //
361
        assign  many_sel = 1'b0;
362
 
363
        //
364
        // many_ack
365
        //
366
        // Normally this would capture the error when multiple things creates acks
367
        // at the same time.  The S6 is small, though, and doesn't have the logic
368
        // we need to do this right.  Hence we just declare (and hope) that this
369
        // will never be true and work with that.
370
        //
371 25 dgisselq
        assign  many_ack = 1'b0;
372 46 dgisselq
 
373 5 dgisselq
        wire            flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
374 46 dgisselq
                        gpio_int, pwm_int, keypad_int,button_int;
375 5 dgisselq
 
376
 
377
        //
378 46 dgisselq
        // bus_err_addr
379 5 dgisselq
        //
380 46 dgisselq
        // We'd like to know, after the fact, what (if any) address caused a
381
        // bus error.  So ... if we get a bus error, let's record the address
382
        // on the bus for later analysis.
383 5 dgisselq
        //
384 46 dgisselq
        initial bus_err_addr = 0;
385
        always @(posedge i_clk)
386
                if (wb_err)
387
                        bus_err_addr <= wb_addr;
388
        //
389
        // Interrupt processing
390
        //
391
        // The interrupt controller will be used to tell us if any interrupts
392
        // take place.  
393
        //
394
        // To add more interrupts, you can just add more wires to this int_vector
395
        // for the new interrupts.
396
        // 
397 5 dgisselq
        reg             rx_rdy;
398 11 dgisselq
        wire    [11:0]   int_vector;
399 25 dgisselq
        assign  int_vector = {
400
                                flash_interrupt, gpio_int, pwm_int, keypad_int,
401 46 dgisselq
                                (!o_tx_stb), rx_rdy,
402 13 dgisselq
                                tmrb_int, tmra_int,
403 46 dgisselq
                                1'b0, scop_interrupt,
404 5 dgisselq
                                wb_err, button_int };
405
 
406
        wire    [31:0]   pic_data;
407 11 dgisselq
        icontrol #(12)  pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
408 5 dgisselq
                                        &&(wb_addr[3:0]==4'h0)&&(wb_we),
409
                        wb_data, pic_data, int_vector, w_interrupt);
410
 
411 46 dgisselq
        wire    [31:0]   timer_data, timer_b;
412 5 dgisselq
        wire            zta_ack, zta_stall, ztb_ack, ztb_stall;
413 25 dgisselq
        ziptimer        #(32,31,1)
414 46 dgisselq
                thetimer(i_clk, 1'b0, 1'b1, wb_cyc,
415 5 dgisselq
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
416 46 dgisselq
                                wb_we, wb_data, zta_ack, zta_stall, timer_data,
417 5 dgisselq
                                tmra_int);
418 25 dgisselq
        ziptimer        #(32,31,0)
419 8 dgisselq
                zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
420 5 dgisselq
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
421
                                wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
422
                                tmrb_int);
423
 
424
        always @(posedge i_clk)
425
                case(wb_addr[3:0])
426
                        4'h0: io_data <= pic_data;
427 46 dgisselq
                        4'h1: io_data <= { {(30-BAW){1'b0}}, bus_err_addr, 2'b00 };
428
                        4'h2: io_data <= timer_data;
429 5 dgisselq
                        4'h3: io_data <= timer_b;
430
                        4'h4: io_data <= pwm_data;
431
                        4'h5: io_data <= spio_data;
432
                        4'h6: io_data <= gpio_data;
433
                        4'h7: io_data <= uart_data;
434
                        default: io_data <= `DATESTAMP;
435
                        // 4'h8: io_data <= `DATESTAMP;
436
                endcase
437
        always @(posedge i_clk)
438 46 dgisselq
                io_ack <= (wb_stb)&&(io_sel);
439 5 dgisselq
        assign  io_stall = 1'b0;
440
 
441
        wire    pwm_ack, pwm_stall;
442 13 dgisselq
        wbpwmaudio      #(14'd10000,2,0,14)
443
                theaudio(i_clk, wb_cyc,
444
                                ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)),
445
                                        wb_we, 1'b0, wb_data,
446
                                pwm_ack, pwm_stall, pwm_data, o_pwm,
447
                                        o_pwm_aux, //={pwm_shutdown_n,pwm_gain}
448
                                        pwm_int);
449 5 dgisselq
 
450
        //
451
        // Special Purpose I/O: Keypad, button, LED status and control
452
        //
453 25 dgisselq
        wire    [3:0]    w_led;
454 46 dgisselq
        spio    thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),
455
                                wb_we, wb_data, spio_data,
456
                        o_kp_col, i_kp_row, i_btn, w_led,
457 5 dgisselq
                        keypad_int, button_int);
458 32 dgisselq
        assign  o_led = { w_led[3]|w_interrupt,w_led[2],w_led[1:0] };
459 5 dgisselq
 
460
        //
461
        // General purpose (sort of) I/O:  (Bottom two bits robbed in each
462
        // direction for an I2C link at the toplevel.v design)
463
        //
464
        wbgpio  #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
465
                        (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
466
                        wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
467
 
468
        //
469
        //
470
        //      Rudimentary serial port control
471
        //
472
        reg     [7:0]    r_rx_data;
473
        // Baud rate is set by clock rate / baud rate.
474
        // Thus, 80MHz / 115200MBau
475
        //      = 694.4, or about 0x2b6. 
476
        // although the CPU might struggle to keep up at this speed without a
477
        // hardware buffer.
478
        //
479
        // We'll add the flag for two stop bits.
480 8 dgisselq
        // assign       o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
481 46 dgisselq
        assign  o_uart_setup = 31'h4000208d; // 9600 MBaud, 8N1
482 5 dgisselq
 
483 8 dgisselq
        initial o_tx_stb = 1'b0;
484
        initial o_tx_data = 8'h00;
485
        always @(posedge i_clk)
486
                if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
487
                begin
488
                        o_tx_data <= wb_data[7:0];
489
                        o_tx_stb <= 1'b1;
490
                end
491
                else if ((o_tx_stb)&&(~i_tx_busy))
492
                        o_tx_stb <= 1'b0;
493
        initial rx_rdy = 1'b0;
494
        always @(posedge i_clk)
495
                if (i_rx_stb)
496
                        r_rx_data <= i_rx_data;
497
        always @(posedge i_clk)
498
        begin
499
                if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
500
                        rx_rdy <= i_rx_stb;
501
                else if (i_rx_stb)
502
                        rx_rdy <= (rx_rdy | i_rx_stb);
503
        end
504 46 dgisselq
        assign  o_uart_rts_n = (rx_rdy);
505 8 dgisselq
        assign  uart_data = { 23'h0, ~rx_rdy, r_rx_data };
506
        //
507
        // uart_ack gets returned as part of io_ack, since that happens when
508
        // io_sel and wb_stb are defined
509
        //
510
        // always @(posedge i_clk)
511
                // uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
512 5 dgisselq
 
513
 
514
 
515
        //
516
        //      FLASH MEMORY CONFIGURATION ACCESS
517
        //
518 46 dgisselq
`ifdef  FLASH_ACCESS
519 51 dgisselq
`ifdef  LOWLOGIC_FLASH
520
        wire    w_flash_ack;
521
        qflashxpress    flashmem(i_clk,
522
                wb_cyc,(wb_stb)&&(flash_sel),
523
                        wb_addr[(LGFLASHSZ-3):0],
524
                w_flash_ack, flash_stall, flash_data,
525
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat);
526
 
527
        assign  flash_interrupt = 1'b0;
528
        reg     r_flash_ack;
529
        initial r_flash_ack = 1'b0;
530
        always @(posedge i_clk)
531
                r_flash_ack <= (wb_stb)&&(flctl_sel);
532
        assign  flash_ack = (w_flash_ack)||(r_flash_ack);
533
`else   // LOWLOGIC_FLASH
534
        wbqspiflashp #(LGFLASHSZ)       // Use the writable interface
535
                flashmem(i_clk,
536
                  wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
537 46 dgisselq
                        wb_addr[(LGFLASHSZ-3):0], wb_data,
538 5 dgisselq
                flash_ack, flash_stall, flash_data,
539
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
540
                flash_interrupt);
541 51 dgisselq
`endif  // LOWLOGIC_FLASH
542
`else   // FLASH_ACCESS
543 46 dgisselq
        reg     r_flash_ack;
544
        initial r_flash_ack = 1'b0;
545 5 dgisselq
        always @(posedge i_clk)
546 46 dgisselq
                r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
547
 
548
        assign  flash_ack = r_flash_ack;
549
        assign  flash_stall = 1'b0;
550
        assign  flash_data = 32'h0000;
551
        assign  flash_interrupt = 1'b0;
552
 
553
        assign  o_qspi_sck   = 1'b1;
554
        assign  o_qspi_cs_n  = 1'b1;
555
        assign  o_qspi_mod   = 2'b01;
556
        assign  o_qspi_dat   = 4'b1111;
557 51 dgisselq
`endif  // FLASH_ACCESS
558 5 dgisselq
 
559
        //
560
        //      ON-CHIP RAM MEMORY ACCESS
561
        //
562 8 dgisselq
`ifdef  IMPLEMENT_ONCHIP_RAM
563 46 dgisselq
        memdev  #(.LGMEMSZ(LGMEMSZ))
564
                ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
565
                        wb_addr[(LGMEMSZ-3):0], wb_data, wb_sel,
566
                        mem_ack, mem_stall, mem_data);
567 8 dgisselq
`else
568
        assign  mem_data = 32'h00;
569
        assign  mem_stall = 1'b0;
570
        reg     r_mem_ack;
571
        always @(posedge i_clk)
572 46 dgisselq
                r_mem_ack <= (wb_stb)&&(mem_sel);
573 8 dgisselq
        assign  mem_ack = r_mem_ack;
574
`endif
575 5 dgisselq
 
576
        //
577
        //
578
        //      WISHBONE SCOPE
579
        //
580
        //
581
        //
582
        //
583 8 dgisselq
`ifdef  DBG_SCOPE
584 51 dgisselq
        wire    scop_trigger;
585
        // assign scop_trigger = (flash_sel)&&(wb_stb); // bus_dbg;
586
        assign scop_trigger = (wb_stb)&&(wb_we)&&(flctl_sel);
587
        wire    [31:0]   flash_debug;
588
        wire    [1:0]    sck;
589
`ifdef  LOWLOGIC_FLASH
590
        assign  sck = o_qspi_sck;
591
`else   // LOWLOGIC_FLASH
592
        assign  sck = { o_qspi_sck, o_qspi_sck };
593
`endif  // LOWLOGIC_FLASH
594
        assign  flash_debug = {
595
                        wb_cyc, wb_stb,
596
                                flash_sel, flctl_sel, flash_ack, flash_stall,
597
                                o_qspi_cs_n, sck, o_qspi_mod, 1'b0,
598
                        o_qspi_dat, i_qspi_dat, flash_data[11:0]
599
                };
600 25 dgisselq
`ifdef  COMPRESSED_SCOPE
601
        wbscopc #(5'ha)
602
`else
603
        wbscope #(5'ha)
604
`endif
605 51 dgisselq
        thescope(i_clk, 1'b1, scop_trigger, flash_debug,
606 5 dgisselq
                // Wishbone interface
607 8 dgisselq
                i_clk, wb_cyc, (wb_stb)&&(scop_sel),
608 5 dgisselq
                                wb_we, wb_addr[0], wb_data,
609 51 dgisselq
                        scop_ack, scop_stall, scop_data,
610
                scop_interrupt);
611 8 dgisselq
`else
612 51 dgisselq
        reg     r_scop_ack;
613 8 dgisselq
        always @(posedge i_clk)
614 51 dgisselq
                r_scop_ack <= (wb_stb)&&(scop_sel);
615
        assign  scop_ack = r_scop_ack;
616
        assign  scop_data = 32'h000;
617
        assign  scop_stall= 1'b0;
618 5 dgisselq
`endif
619
 
620
endmodule
621
 

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