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[/] [s6soc/] [trunk/] [rtl/] [alttop.v] - Blame information for rev 51

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1 5 dgisselq
`timescale 10ns / 100ps
2
////////////////////////////////////////////////////////////////////////////////
3
//
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// Filename:    alttop.v
5
//
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// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
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//
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// Purpose:     This is an alternate toplevel configuration for the CMod S6
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//              project.  Basically, the CMod S6 has so little logic within
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//      it, that there's no logic available for in situ reprogramming.  This
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//      toplevel file serves that purpose: It provides full configuration
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//      access, via the UART port, for the flash (read and write), and full
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//      test level access for all of the devices on the board.  What it
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//      doesn't have, however, is the ZipCPU.  (I had to give up something to
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//      get the logic back for this purpose!)
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
46 51 dgisselq
// `define      LOWLOGIC_FLASH
47 5 dgisselq
module alttop(i_clk_8mhz,
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                o_qspi_cs_n, o_qspi_sck, io_qspi_dat,
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                i_btn, o_led, o_pwm, o_pwm_shutdown_n, o_pwm_gain,
50 46 dgisselq
                        i_uart, o_uart, o_uart_rts_n, i_uart_cts_n,
51 5 dgisselq
                i_kp_row, o_kp_col,
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                i_gpio, o_gpio,
53 8 dgisselq
                io_scl, io_sda,
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                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n, io_depp_data,
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                        o_depp_wait
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                );
57 5 dgisselq
        input           i_clk_8mhz;
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        //
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        // Quad SPI Flash
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        output  wire            o_qspi_cs_n;
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        output  wire            o_qspi_sck;
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        inout   wire    [3:0]    io_qspi_dat;
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        //
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        // General purpose I/O
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        input           [1:0]    i_btn;
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        output  wire    [3:0]    o_led;
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        output  wire            o_pwm, o_pwm_shutdown_n, o_pwm_gain;
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        //
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        // and our serial port
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        input           i_uart;
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        output  wire    o_uart;
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        //      and it's associated control wires
73 46 dgisselq
        output  wire    o_uart_rts_n;
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        input           i_uart_cts_n;
75 5 dgisselq
        // Our keypad
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        input           [3:0]    i_kp_row;
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        output  wire    [3:0]    o_kp_col;
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        // and our GPIO
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        input           [15:2]  i_gpio;
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        output  wire    [15:2]  o_gpio;
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        // and our I2C port
82
        inout                   io_scl, io_sda;
83 8 dgisselq
        // Finally, the DEPP interface ... if so enabled
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        input                   i_depp_astb_n, i_depp_dstb_n, i_depp_write_n;
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        inout           [7:0]    io_depp_data;
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        output  wire    o_depp_wait;
87 5 dgisselq
 
88
        //
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        // Clock management
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        //
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        //      Generate a usable clock for the rest of the board to run at.
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        //
93 51 dgisselq
        wire    ck_zero_0, clk_s, clk_sn;
94 5 dgisselq
 
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        // Clock frequency = (20 / 2) * 8Mhz = 80 MHz
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        // Clock period = 12.5 ns
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        DCM_SP #(
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                .CLKDV_DIVIDE(2.0),
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                .CLKFX_DIVIDE(2),               // Here's the divide by two
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                .CLKFX_MULTIPLY(20),            // and here's the multiply by 20
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                .CLKIN_DIVIDE_BY_2("FALSE"),
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                .CLKIN_PERIOD(125.0),
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                .CLKOUT_PHASE_SHIFT("NONE"),
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                .CLK_FEEDBACK("1X"),
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                .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
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                .DLL_FREQUENCY_MODE("LOW"),
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                .DUTY_CYCLE_CORRECTION("TRUE"),
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                .PHASE_SHIFT(0),
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                .STARTUP_WAIT("TRUE")
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        ) u0(   .CLKIN(i_clk_8mhz),
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                .CLK0(ck_zero_0),
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                .CLKFB(ck_zero_0),
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                .CLKFX(clk_s),
114 51 dgisselq
                .CLKFX180(clk_sn),
115 5 dgisselq
                .PSEN(1'b0),
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                .RST(1'b0));
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        //
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        // The UART serial interface
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        //
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        //      Perhaps this should be part of our simulation model as well.
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        //      For historical reasons, internal to Gisselquist Technology,
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        //      this has remained separate from the simulation, allowing the
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        //      simulation to bypass whether or not these two functions work.
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        //
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        wire            rx_stb, tx_stb;
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        wire    [7:0]    rx_data, tx_data;
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        wire            tx_busy;
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        wire    [29:0]   uart_setup;
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131 51 dgisselq
        // Baud rate is set by clock rate / baud rate desired.  Thus,
132 46 dgisselq
        // 80 MHz / 9600 Baud = 8333, or about 0x208d.  We choose a slow
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        // speed such as 9600 Baud to help the CPU keep up with the serial
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        // port rate.
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        localparam [30:0]        UART_SETUP = 31'h4000208d;
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        assign  uart_setup = UART_SETUP;
137
 
138
        wire            reset_s;
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        assign  reset_s = 1'b0;
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141 5 dgisselq
        wire    rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, tx_break;
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        assign  tx_break = 1'b0;
143 46 dgisselq
        rxuart  #(UART_SETUP)
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                rcvuart(clk_s, 1'b0, uart_setup,
145 5 dgisselq
                        i_uart, rx_stb, rx_data,
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                        rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
147 46 dgisselq
        txuart  #(UART_SETUP)
148
                tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data,
149
                        i_uart_cts_n, o_uart, tx_busy);
150 5 dgisselq
 
151
 
152
        //
153
        // ALT-BUSMASTER
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        //
155
        //      Busmaster is so named because it contains the wishbone
156
        //      interconnect that all of the internal devices are hung off of.
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        //      To reconfigure this device for another purpose, usually
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        //      the busmaster module (i.e. the interconnect) is all that needs
159
        //      to be changed: either to add more devices, or to remove them.
160
        //
161
        //      This is an alternate version of the busmaster interface,
162
        //      offering no ZipCPU and access to reprogramming via the flash.
163
        //
164 51 dgisselq
`ifdef  LOWLOGIC_FLASH
165
        wire    [1:0]    qspi_sck;
166
`else
167
        wire            qspi_sck;
168
`endif
169
        wire            qspi_cs_n;
170 5 dgisselq
        wire    [3:0]    qspi_dat;
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        wire    [1:0]    qspi_bmod;
172
        wire    [15:0]   w_gpio;
173 8 dgisselq
        wire    [7:0]    w_depp_data;
174 5 dgisselq
 
175 46 dgisselq
        wire    w_uart_rts_n;
176 8 dgisselq
`ifndef BYPASS_LOGIC
177 13 dgisselq
        altbusmaster    slavedbus(clk_s, 1'b0,
178 5 dgisselq
                // External ... bus control (if enabled)
179 8 dgisselq
                // DEPP I/O Control
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                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
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                        io_depp_data, w_depp_data, o_depp_wait,
182
                // External UART interface
183 46 dgisselq
                rx_stb, rx_data, tx_stb, tx_data, tx_busy, w_uart_rts_n,
184 5 dgisselq
                // SPI/SD-card flash
185 51 dgisselq
                qspi_cs_n, qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
186 5 dgisselq
                // Board lights and switches
187
                i_btn, o_led, o_pwm, { o_pwm_shutdown_n, o_pwm_gain },
188
                // Keypad connections
189
                i_kp_row, o_kp_col,
190
                // UART control
191
                uart_setup,
192
                // GPIO lines
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                { i_gpio, io_scl, io_sda }, w_gpio
194
                );
195 46 dgisselq
        assign  o_uart_rts_n = (w_uart_rts_n);
196 5 dgisselq
 
197
        //
198
        // Quad SPI support
199
        //
200
        //      Supporting a Quad SPI port requires knowing which direction the
201
        //      wires are going at each instant, whether the device is in full
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        //      Quad mode in, full quad mode out, or simply the normal SPI
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        //      port with one wire in and one wire out.  This utilizes our
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        //      control wires (qspi_bmod) to set the output lines appropriately.
205
        //
206 51 dgisselq
        //
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        //      2'b0?   -- Normal SPI
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        //      2'b10   -- Quad Output
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        //      2'b11   -- Quad Input
210
`ifdef  LOWLOGIC_FLASH
211
        reg             r_qspi_cs_n;
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        reg     [1:0]    r_qspi_bmod;
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        reg     [3:0]    r_qspi_dat, r_qspi_z;
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        reg     [1:0]    r_qspi_sck;
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        always @(posedge clk_s)
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                r_qspi_sck <= qspi_sck;
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        xoddr   xqspi_sck({clk_s, clk_sn}, r_qspi_sck, o_qspi_sck);
218
        initial r_qspi_cs_n = 1'b1;
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        initial r_qspi_z = 4'b1101;
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        always @(posedge clk_s)
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        begin
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                r_qspi_dat  <= (qspi_bmod[1]) ? qspi_dat:{ 3'b111, qspi_dat[0]};
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                r_qspi_z    <= (!qspi_bmod[1])? 4'b1101
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                                : ((qspi_bmod[0]) ? 4'h0 : 4'hf);
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                r_qspi_cs_n <= qspi_cs_n;
226
        end
227
 
228
        assign  o_qspi_cs_n    = r_qspi_cs_n;
229
        assign  io_qspi_dat[0] = (r_qspi_z[0]) ? r_qspi_dat[0] : 1'bz;
230
        assign  io_qspi_dat[1] = (r_qspi_z[1]) ? r_qspi_dat[1] : 1'bz;
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        assign  io_qspi_dat[2] = (r_qspi_z[2]) ? r_qspi_dat[2] : 1'bz;
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        assign  io_qspi_dat[3] = (r_qspi_z[3]) ? r_qspi_dat[3] : 1'bz;
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`else
234
        assign io_qspi_dat = (!qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
235 5 dgisselq
                                :((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
236
 
237 51 dgisselq
        assign  o_qspi_cs_n = qspi_cs_n;
238
        assign  o_qspi_sck  = qspi_sck;
239
`endif  // LOWLOGIC_FLASH
240
 
241
`else   // BYPASS_LOGIC
242 8 dgisselq
        reg     [26:0]   r_counter;
243
        always @(posedge clk_s)
244
                r_counter <= r_counter+1;
245
        assign  o_led[0] = r_counter[26];
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        assign  o_led[1] = r_counter[25];
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        assign  o_led[2] = r_counter[24];
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        assign  o_led[3] = r_counter[23];
249
        // assign       o_led[0] = 1'b1;
250
        // assign       o_led[1] = 1'b0;
251
        // assign       o_led[2] = 1'b1;
252
        // assign       o_led[3] = 1'b0;
253
 
254
        assign  w_gpio = 16'h3;
255
        assign  o_pwm = 1'b0;
256
        assign  o_pwm_shutdown_n = 1'b0;
257
        assign  o_pwm_gain = 1'b0;
258
 
259
        assign  o_depp_wait = (~i_depp_astb_n);
260
        assign  w_depp_data = 8'h00;
261
        assign  io_qspi_dat = 4'bzzzz;
262
        assign  o_qspi_cs_n = 1'b1;
263
        assign  o_qspi_sck = 1'b1;
264
 
265
        assign  uart_setup = 30'h080002b6;
266
 
267 46 dgisselq
        assign  o_uart_rts_n = 1'b0;
268 51 dgisselq
`endif  // BYPASS_LOGIC
269 5 dgisselq
        //
270
        // I2C support
271
        //
272
        //      Supporting I2C requires a couple quick adjustments to our
273
        //      GPIO lines.  Specifically, we'll allow that when the output
274
        //      (i.e. w_gpio) pins are high, then the I2C lines float.  They
275 51 dgisselq
        //      will be (need to be) pulled up by a resistor in order to
276 5 dgisselq
        //      match the I2C protocol, but this change makes them look/act
277
        //      more like GPIO pins.
278
        //
279
        assign  io_sda = (w_gpio[0]) ? 1'bz : 1'b0;
280
        assign  io_scl = (w_gpio[1]) ? 1'bz : 1'b0;
281
        assign  o_gpio[15:2] = w_gpio[15:2];
282
 
283 8 dgisselq
        //
284
        // DEPP return data support
285
        //
286
        assign io_depp_data = (~i_depp_write_n)? 8'bzzzz_zzzz : w_depp_data;
287
 
288 5 dgisselq
endmodule

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