OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [busmaster.v] - Blame information for rev 12

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 2 dgisselq
//
3 4 dgisselq
// Filename:    busmaster.v
4 2 dgisselq
//
5 4 dgisselq
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6 2 dgisselq
//
7 4 dgisselq
// Purpose:     
8 2 dgisselq
//
9 4 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
10 2 dgisselq
//              Gisselquist Technology, LLC
11
//
12 4 dgisselq
////////////////////////////////////////////////////////////////////////////////
13 2 dgisselq
//
14 4 dgisselq
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
15 2 dgisselq
//
16 4 dgisselq
// This program is free software (firmware): you can redistribute it and/or
17
// modify it under the terms of  the GNU General Public License as published
18
// by the Free Software Foundation, either version 3 of the License, or (at
19
// your option) any later version.
20
//
21
// This program is distributed in the hope that it will be useful, but WITHOUT
22
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
23
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
24
// for more details.
25
//
26
// You should have received a copy of the GNU General Public License along
27
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
28
// target there if the PDF file isn't present.)  If not, see
29
// <http://www.gnu.org/licenses/> for a copy.
30
//
31
// License:     GPL, v3, as defined and found on www.gnu.org,
32
//              http://www.gnu.org/licenses/gpl.html
33
//
34
//
35
////////////////////////////////////////////////////////////////////////////////
36
//
37
//
38
//
39 2 dgisselq
`include "builddate.v"
40
//
41
`define INCLUDE_ZIPPY
42 4 dgisselq
`define IMPLEMENT_ONCHIP_RAM    // 2804 w/o after synthesis
43 2 dgisselq
`ifndef VERILATOR
44
`define FANCY_ICAP_ACCESS
45
`endif
46
`define FLASH_ACCESS
47 7 dgisselq
`define DBG_SCOPE       // About 204 LUTs, at 2^6 addresses
48
// `define      INCLUDE_RTC     // About 90 LUTs
49 2 dgisselq
module  busmaster(i_clk, i_rst,
50
                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
51 12 dgisselq
                        o_uart_cts,
52 2 dgisselq
                // The SPI Flash lines
53
                o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
54
                // The board I/O
55
                i_btn, o_led, o_pwm, o_pwm_aux,
56
                // Keypad connections
57
                i_kp_row, o_kp_col,
58
                // UART control
59
                o_uart_setup,
60
                // GPIO lines
61
                i_gpio, o_gpio);
62 8 dgisselq
        parameter       BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
63 11 dgisselq
                        CMOD_ZIPCPU_RESET_ADDRESS=23'h480000,
64 8 dgisselq
                        ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
65 2 dgisselq
        input                   i_clk, i_rst;
66
        input                   i_rx_stb;
67
        input           [7:0]    i_rx_data;
68
        output  reg             o_tx_stb;
69
        output  reg     [7:0]    o_tx_data;
70
        input                   i_tx_busy;
71 12 dgisselq
        output  wire            o_uart_cts;
72 2 dgisselq
        // SPI flash control
73
        output  wire            o_qspi_cs_n, o_qspi_sck;
74
        output  wire    [3:0]    o_qspi_dat;
75
        input           [3:0]    i_qspi_dat;
76
        output  wire    [1:0]    o_qspi_mod;
77
        // Board I/O
78
        input           [1:0]    i_btn;
79
        output  wire    [3:0]    o_led;
80
        output  wire            o_pwm;
81
        output  wire    [1:0]    o_pwm_aux;
82
        // Keypad
83
        input           [3:0]    i_kp_row;
84
        output  wire    [3:0]    o_kp_col;
85
        // UART control
86
        output  wire    [29:0]   o_uart_setup;
87
        // GPIO liines
88
        input           [15:0]   i_gpio;
89
        output  wire    [15:0]   o_gpio;
90
 
91
 
92
        //
93
        //
94
        // Master wishbone wires
95
        //
96
        //
97
        wire            wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
98
        wire    [31:0]   wb_data, wb_idata;
99
        wire    [(BAW-1):0]      wb_addr;
100
        wire    [5:0]            io_addr;
101
        assign  io_addr = {
102
                        wb_addr[22],    // Flash
103
                        wb_addr[13],    // RAM
104
                        wb_addr[11],    // RTC
105
                        wb_addr[10],    // CFG
106
                        wb_addr[ 9],    // SCOPE
107
                        wb_addr[ 8] };  // I/O
108
 
109
        // Wires going to devices
110
        // And then headed back home
111
        wire    w_interrupt;
112
        // Oh, and the debug control for the ZIP CPU
113
        wire            zip_dbg_ack, zip_dbg_stall;
114
        wire    [31:0]   zip_dbg_data;
115
 
116
 
117
        //
118
        //
119
        // The BUS master (source): The ZipCPU
120
        //
121
        //
122
        wire            zip_cyc, zip_stb, zip_we, zip_cpu_int;
123
        wire    [(ZA-1):0]       w_zip_addr;
124
        wire    [(BAW-1):0]      zip_addr;
125
        wire    [31:0]           zip_data;
126
        // and then coming from devices
127
        wire            zip_ack, zip_stall, zip_err;
128
        wire    dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
129
        wire    [(BAW-1):0]      dwb_addr;
130
        wire    [31:0]           dwb_odata;
131
 
132
        // wire [31:0]  zip_debug;
133
//
134
// We'll define our RESET_ADDRESS to be halfway through our flash memory.
135
//      `define CMOD_ZIPCPU_RESET_ADDRESS       23'h600000
136
//
137
// Ahm, No.  We can actually do much better than that.  Our toplevel *.bit file
138
// only takes up only 335kB.  Let's give it some room to grow to 1024 kB.  Then
139
// 23 can start our ROM at 23'h400100
140
//
141
// Not so fast.  In hindsight, we really want to be  able to adjust the load and
142
// the program separately.  So, instead, let's place our RESET address at the
143
// second flash erase block.  That way, we can change our program code found
144
// in the flash without needing to change our FPGA load and vice versa.
145
//
146
// 23'h404000
147
        zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
148
                thecpu(i_clk, 1'b0,
149
                        // Zippys wishbone interface
150
                        wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data,
151
                                wb_ack, wb_stall, wb_idata, wb_err,
152
                        w_interrupt, zip_cpu_int,
153
                        // Debug wishbone interface
154
                        1'b0, 1'b0,1'b0, 1'b0, 32'h00,
155
                                zip_dbg_ack, zip_dbg_stall, zip_dbg_data);
156
        generate
157
        if (ZA < BAW)
158
                assign  wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
159
        else
160
                assign  wb_addr = w_zip_addr;
161
        endgenerate
162
 
163
        wire    io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
164
                        rtc_sel, none_sel, many_sel;
165
        wire    flash_ack, scop_ack, cfg_ack, mem_ack;
166
        wire    rtc_ack, rtc_stall;
167
`ifdef  INCLUDE_RTC
168
        assign  rtc_stall = 1'b0;
169
`endif
170
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
171 4 dgisselq
        reg     io_ack;
172 2 dgisselq
 
173
        wire    [31:0]   flash_data, scop_data, cfg_data, mem_data, pwm_data,
174
                        spio_data, gpio_data, uart_data;
175
        reg     [31:0]   io_data;
176
        reg     [(BAW-1):0]      bus_err_addr;
177
 
178
        assign  wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
179
`ifdef  INCLUDE_RTC
180
                                ||(rtc_ack)
181
`endif
182
                                ||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
183
        assign  wb_stall = ((io_sel)&&(io_stall))
184
                        ||((scop_sel)&&(scop_stall))
185
                        ||((cfg_sel)&&(cfg_stall))
186
                        ||((mem_sel)&&(mem_stall))
187
`ifdef  INCLUDE_RTC
188
                        ||((rtc_sel)&&(rtc_stall))
189
`endif
190
                        ||((flash_sel||flctl_sel)&&(flash_stall));
191
                        // (none_sel)&&(1'b0)
192
 
193
        /*
194
        assign  wb_idata = (io_ack)?io_data
195
                        : ((scop_ack)?scop_data
196
                        : ((cfg_ack)?cfg_data
197
                        : ((mem_ack)?mem_data
198
                        : ((flash_ack)?flash_data
199
                        : 32'h00))));
200
        */
201
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
202
                        : ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
203 4 dgisselq
                        : ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
204 2 dgisselq
        assign  wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
205
 
206
        // Addresses ...
207
        //      0000 xxxx       configuration/control registers
208
        //      1 xxxx xxxx xxxx xxxx xxxx      Up-sampler taps
209
        assign  io_sel   =((wb_cyc)&&(io_addr[5:0]==6'h1));
210
        assign  flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
211
        assign  scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
212
        assign  cfg_sel  =((wb_cyc)&&(io_addr[5:2]==4'h1));
213
        // zip_sel is not on the bus at this point
214
`ifdef  INCLUDE_RTC
215
        assign  rtc_sel  =((wb_cyc)&&(io_addr[5:3]==3'h1));
216
`endif
217
        assign  mem_sel  =((wb_cyc)&&(io_addr[5:4]==2'h1));
218
        assign  flash_sel=((wb_cyc)&&(io_addr[5]));
219
 
220
        assign  none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
221
        /*
222
        assign  many_sel =((wb_cyc)&&(wb_stb)&&(
223
                         {3'h0, io_sel}
224
                        +{3'h0, flctl_sel}
225 11 dgisselq
                        +{3'h0, scop_sel}
226 2 dgisselq
                        +{3'h0, cfg_sel}
227 11 dgisselq
                        +{3'h0, rtc_sel}
228 2 dgisselq
                        +{3'h0, mem_sel}
229
                        +{3'h0, flash_sel} > 1));
230
        */
231
        assign  many_sel = 1'b0;
232
 
233
        wire    many_ack;
234
        assign  many_ack =((wb_cyc)&&(
235
                         {3'h0, io_ack}
236
                        +{3'h0, scop_ack}
237
                        +{3'h0, cfg_ack}
238
`ifdef  INCLUDE_RTC
239
                        +{3'h0, rtc_ack}
240
`endif
241
                        +{3'h0, mem_ack}
242
                        +{3'h0, flash_ack} > 1));
243
 
244
        wire            flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
245
                        rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
246
 
247
 
248
        //
249
        //
250
        //
251
        reg             rx_rdy;
252
        wire    [10:0]   int_vector;
253
        assign  int_vector = { gpio_int, pwm_int, keypad_int,
254
                                ~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
255
                                rtc_interrupt, scop_interrupt,
256
                                wb_err, button_int };
257
 
258
        wire    [31:0]   pic_data;
259 4 dgisselq
        icontrol #(11)  pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
260 2 dgisselq
                                        &&(wb_addr[3:0]==4'h0)&&(wb_we),
261
                        wb_data, pic_data, int_vector, w_interrupt);
262
 
263 8 dgisselq
        initial bus_err_addr = 0; // `DATESTAMP;
264 2 dgisselq
        always @(posedge i_clk)
265
                if (wb_err)
266
                        bus_err_addr <= wb_addr;
267
 
268 11 dgisselq
        wire    [31:0]   timer_a, timer_b;
269 2 dgisselq
        wire            zta_ack, zta_stall, ztb_ack, ztb_stall;
270 11 dgisselq
        ziptimer        #(32,31)
271 4 dgisselq
                zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
272 2 dgisselq
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
273
                                wb_we, wb_data, zta_ack, zta_stall, timer_a,
274
                                tmra_int);
275 11 dgisselq
        ziptimer        #(32,31)
276 4 dgisselq
                zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
277 2 dgisselq
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
278
                                wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
279
                                tmrb_int);
280
 
281
        wire    [31:0]   rtc_data;
282
`ifdef  INCLUDE_RTC
283
        wire    rtcd_ack, rtcd_stall, ppd;
284
        // rtcdate      thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
285
                        // wb_data, rtcd_ack, rtcd_stall, date_data);
286
        reg     r_rtc_ack;
287
        initial r_rtc_ack = 1'b0;
288
        always @(posedge i_clk)
289
                r_rtc_ack <= ((wb_stb)&&(rtc_sel));
290
        assign  rtc_ack = r_rtc_ack;
291
 
292
        rtclight
293 8 dgisselq
                #(23'h35afe5,23,0,0)      // 80 MHz clock
294 2 dgisselq
                thetime(i_clk, wb_cyc,
295
                        ((wb_stb)&&(rtc_sel)), wb_we,
296
                        { 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
297
                        rtc_interrupt, ppd);
298
`else
299
        assign  rtc_interrupt = 1'b0;
300
        assign  rtc_data = 32'h00;
301
        assign  rtc_ack  = 1'b0;
302
`endif
303
 
304
        always @(posedge i_clk)
305
                case(wb_addr[3:0])
306
                        4'h0: io_data <= pic_data;
307
                        4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr };
308
                        4'h2: io_data <= timer_a;
309
                        4'h3: io_data <= timer_b;
310
                        4'h4: io_data <= pwm_data;
311
                        4'h5: io_data <= spio_data;
312
                        4'h6: io_data <= gpio_data;
313
                        4'h7: io_data <= uart_data;
314
                        default: io_data <= `DATESTAMP;
315
                        // 4'h8: io_data <= `DATESTAMP;
316
                endcase
317
        always @(posedge i_clk)
318
                io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel);
319
        assign  io_stall = 1'b0;
320
 
321
        wire    pwm_ack, pwm_stall;
322 12 dgisselq
        wbpwmaudio      #(14'd10000,2,0,14)
323
                theaudio(i_clk, wb_cyc,
324
                                ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)),
325
                                        wb_we, 1'b0, wb_data,
326
                                pwm_ack, pwm_stall, pwm_data, o_pwm,
327
                                        o_pwm_aux, //={pwm_shutdown_n,pwm_gain}
328
                                        pwm_int);
329 2 dgisselq
 
330
        //
331
        // Special Purpose I/O: Keypad, button, LED status and control
332
        //
333
        spio    thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
334
                        wb_data, spio_data, o_kp_col, i_kp_row, i_btn, o_led,
335
                        keypad_int, button_int);
336
 
337
        //
338
        // General purpose (sort of) I/O:  (Bottom two bits robbed in each
339
        // direction for an I2C link at the toplevel.v design)
340
        //
341
        wbgpio  #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
342
                        (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
343
                        wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
344
 
345
        //
346
        //
347
        //      Rudimentary serial port control
348
        //
349
        reg     [7:0]    r_rx_data;
350
        // Baud rate is set by clock rate / baud rate.
351
        // Thus, 80MHz / 115200MBau
352
        //      = 694.4, or about 0x2b6. 
353
        // although the CPU might struggle to keep up at this speed without a
354
        // hardware buffer.
355
        //
356
        // We'll add the flag for two stop bits.
357 7 dgisselq
        // assign       o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
358
        assign  o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1
359 2 dgisselq
 
360
        initial o_tx_stb = 1'b0;
361
        initial o_tx_data = 8'h00;
362
        always @(posedge i_clk)
363 4 dgisselq
                if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
364 2 dgisselq
                begin
365
                        o_tx_data <= wb_data[7:0];
366
                        o_tx_stb <= 1'b1;
367
                end
368
                else if ((o_tx_stb)&&(~i_tx_busy))
369
                        o_tx_stb <= 1'b0;
370
        initial rx_rdy = 1'b0;
371
        always @(posedge i_clk)
372
                if (i_rx_stb)
373
                        r_rx_data <= i_rx_data;
374
        always @(posedge i_clk)
375
        begin
376 4 dgisselq
                if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
377 2 dgisselq
                        rx_rdy <= i_rx_stb;
378
                else if (i_rx_stb)
379
                        rx_rdy <= (rx_rdy | i_rx_stb);
380
        end
381 12 dgisselq
        assign  o_uart_cts = (~rx_rdy);
382 2 dgisselq
        assign  uart_data = { 23'h0, ~rx_rdy, r_rx_data };
383 4 dgisselq
        //
384
        // uart_ack gets returned as part of io_ack, since that happens when
385
        // io_sel and wb_stb are defined
386
        //
387
        // always @(posedge i_clk)
388
                // uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
389 2 dgisselq
 
390
 
391
 
392
        //
393
        //      FLASH MEMORY CONFIGURATION ACCESS
394
        //
395
        wbqspiflash #(24)       flashmem(i_clk,
396 11 dgisselq
                wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
397 4 dgisselq
                        wb_addr[(24-3):0], wb_data,
398 2 dgisselq
                flash_ack, flash_stall, flash_data,
399
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
400
                flash_interrupt);
401
 
402
        //
403
        //      MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
404
        //
405
        wire    [31:0]   cfg_scope;
406
`ifdef  FANCY_ICAP_ACCESS
407
        wbicape6        fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
408
                                wb_addr[5:0], wb_data,
409
                                cfg_ack, cfg_stall, cfg_data,
410
                                cfg_scope);
411
`else
412
        reg     r_cfg_ack;
413
        always @(posedge i_clk)
414
                r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb);
415
        assign  cfg_ack   = r_cfg_ack;
416
        assign  cfg_stall = 1'b0;
417
        assign  cfg_data  = 32'h00;
418
        assign  cfg_scope = 32'h00;
419
`endif
420
 
421
 
422
        //
423
        //      ON-CHIP RAM MEMORY ACCESS
424
        //
425 4 dgisselq
`ifdef  IMPLEMENT_ONCHIP_RAM
426 2 dgisselq
        memdev  #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
427
                        wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
428 4 dgisselq
`else
429
        assign  mem_data = 32'h00;
430
        assign  mem_stall = 1'b0;
431
        reg     r_mem_ack;
432
        always @(posedge i_clk)
433
                r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
434
        assign  mem_ack = r_mem_ack;
435
`endif
436 2 dgisselq
 
437
        //
438
        //
439
        //      WISHBONE SCOPE
440
        //
441
        //
442
        //
443
        //
444
        wire    [31:0]   scop_cfg_data;
445
        wire            scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
446 7 dgisselq
`ifdef  DBG_SCOPE
447 2 dgisselq
        wire            scop_cfg_trigger;
448
        assign  scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
449 7 dgisselq
        wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
450 2 dgisselq
                // Wishbone interface
451 4 dgisselq
                i_clk, wb_cyc, (wb_stb)&&(scop_sel),
452 2 dgisselq
                                wb_we, wb_addr[0], wb_data,
453
                        scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
454
                scop_cfg_interrupt);
455 4 dgisselq
`else
456
        reg     r_scop_cfg_ack;
457
        always @(posedge i_clk)
458
                r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
459
        assign  scop_cfg_ack = r_scop_cfg_ack;
460
        assign  scop_cfg_data = 32'h000;
461
        assign  scop_cfg_stall= 1'b0;
462 2 dgisselq
`endif
463
 
464
        assign  scop_interrupt = scop_cfg_interrupt;
465
        assign  scop_ack   = scop_cfg_ack;
466
        assign  scop_stall = scop_cfg_stall;
467
        assign  scop_data  = scop_cfg_data;
468
 
469
endmodule
470
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.