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[/] [s6soc/] [trunk/] [rtl/] [busmaster.v] - Blame information for rev 28

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1 4 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 2 dgisselq
//
3 4 dgisselq
// Filename:    busmaster.v
4 2 dgisselq
//
5 4 dgisselq
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6 2 dgisselq
//
7 4 dgisselq
// Purpose:     
8 2 dgisselq
//
9 4 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
10 2 dgisselq
//              Gisselquist Technology, LLC
11
//
12 4 dgisselq
////////////////////////////////////////////////////////////////////////////////
13 2 dgisselq
//
14 4 dgisselq
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
15 2 dgisselq
//
16 4 dgisselq
// This program is free software (firmware): you can redistribute it and/or
17
// modify it under the terms of  the GNU General Public License as published
18
// by the Free Software Foundation, either version 3 of the License, or (at
19
// your option) any later version.
20
//
21
// This program is distributed in the hope that it will be useful, but WITHOUT
22
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
23
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
24
// for more details.
25
//
26
// You should have received a copy of the GNU General Public License along
27
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
28
// target there if the PDF file isn't present.)  If not, see
29
// <http://www.gnu.org/licenses/> for a copy.
30
//
31
// License:     GPL, v3, as defined and found on www.gnu.org,
32
//              http://www.gnu.org/licenses/gpl.html
33
//
34
//
35
////////////////////////////////////////////////////////////////////////////////
36
//
37
//
38
//
39 2 dgisselq
`include "builddate.v"
40
//
41
`define INCLUDE_ZIPPY
42 16 dgisselq
`define IMPLEMENT_ONCHIP_RAM
43 2 dgisselq
`ifndef VERILATOR
44
`define FANCY_ICAP_ACCESS
45
`endif
46
`define FLASH_ACCESS
47 7 dgisselq
`define DBG_SCOPE       // About 204 LUTs, at 2^6 addresses
48 16 dgisselq
// `define      COMPRESSED_SCOPE
49
`define INCLUDE_SECOND_TIMER
50 25 dgisselq
`define SECOND_TIMER_IS_WATCHDOG
51
// `define      INCLUDE_RTC     // About 90 LUTs
52
// `define      FULL_BUSERR_CALCULATION
53 16 dgisselq
`define INCLUDE_CPU_RESET_LOGIC
54 2 dgisselq
module  busmaster(i_clk, i_rst,
55
                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
56 12 dgisselq
                        o_uart_cts,
57 2 dgisselq
                // The SPI Flash lines
58
                o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
59
                // The board I/O
60
                i_btn, o_led, o_pwm, o_pwm_aux,
61
                // Keypad connections
62
                i_kp_row, o_kp_col,
63
                // UART control
64
                o_uart_setup,
65
                // GPIO lines
66
                i_gpio, o_gpio);
67 8 dgisselq
        parameter       BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
68 11 dgisselq
                        CMOD_ZIPCPU_RESET_ADDRESS=23'h480000,
69 8 dgisselq
                        ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
70 2 dgisselq
        input                   i_clk, i_rst;
71
        input                   i_rx_stb;
72
        input           [7:0]    i_rx_data;
73
        output  reg             o_tx_stb;
74
        output  reg     [7:0]    o_tx_data;
75
        input                   i_tx_busy;
76 12 dgisselq
        output  wire            o_uart_cts;
77 2 dgisselq
        // SPI flash control
78
        output  wire            o_qspi_cs_n, o_qspi_sck;
79
        output  wire    [3:0]    o_qspi_dat;
80
        input           [3:0]    i_qspi_dat;
81
        output  wire    [1:0]    o_qspi_mod;
82
        // Board I/O
83
        input           [1:0]    i_btn;
84
        output  wire    [3:0]    o_led;
85
        output  wire            o_pwm;
86
        output  wire    [1:0]    o_pwm_aux;
87
        // Keypad
88
        input           [3:0]    i_kp_row;
89
        output  wire    [3:0]    o_kp_col;
90
        // UART control
91
        output  wire    [29:0]   o_uart_setup;
92
        // GPIO liines
93
        input           [15:0]   i_gpio;
94
        output  wire    [15:0]   o_gpio;
95
 
96
 
97
        //
98
        //
99
        // Master wishbone wires
100
        //
101
        //
102
        wire            wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
103
        wire    [31:0]   wb_data, wb_idata;
104
        wire    [(BAW-1):0]      wb_addr;
105
        wire    [5:0]            io_addr;
106
        assign  io_addr = {
107
                        wb_addr[22],    // Flash
108
                        wb_addr[13],    // RAM
109
                        wb_addr[11],    // RTC
110
                        wb_addr[10],    // CFG
111
                        wb_addr[ 9],    // SCOPE
112
                        wb_addr[ 8] };  // I/O
113
 
114
        // Wires going to devices
115
        // And then headed back home
116
        wire    w_interrupt;
117
        // Oh, and the debug control for the ZIP CPU
118
        wire            zip_dbg_ack, zip_dbg_stall;
119
        wire    [31:0]   zip_dbg_data;
120
 
121
 
122
        //
123
        //
124
        // The BUS master (source): The ZipCPU
125
        //
126
        //
127
        wire            zip_cyc, zip_stb, zip_we, zip_cpu_int;
128
        wire    [(ZA-1):0]       w_zip_addr;
129
        wire    [(BAW-1):0]      zip_addr;
130 16 dgisselq
        wire    [31:0]           zip_data, zip_scope_data;
131 2 dgisselq
        // and then coming from devices
132
        wire            zip_ack, zip_stall, zip_err;
133
        wire    dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
134
        wire    [(BAW-1):0]      dwb_addr;
135
        wire    [31:0]           dwb_odata;
136
 
137
        // wire [31:0]  zip_debug;
138
//
139
// We'll define our RESET_ADDRESS to be halfway through our flash memory.
140
//      `define CMOD_ZIPCPU_RESET_ADDRESS       23'h600000
141
//
142
// Ahm, No.  We can actually do much better than that.  Our toplevel *.bit file
143
// only takes up only 335kB.  Let's give it some room to grow to 1024 kB.  Then
144
// 23 can start our ROM at 23'h400100
145
//
146
// Not so fast.  In hindsight, we really want to be  able to adjust the load and
147
// the program separately.  So, instead, let's place our RESET address at the
148
// second flash erase block.  That way, we can change our program code found
149
// in the flash without needing to change our FPGA load and vice versa.
150
//
151
// 23'h404000
152 25 dgisselq
        wire    cpu_reset, tmrb_int;
153 16 dgisselq
`ifdef  INCLUDE_CPU_RESET_LOGIC
154
        reg     btn_reset, x_button, r_button;
155
        initial btn_reset = 1'b0;
156
        initial x_button = 1'b0;
157
        initial r_button = 1'b0;
158
        always @(posedge i_clk)
159
        begin
160
                x_button <= i_btn[1];
161
                r_button <= x_button;
162 25 dgisselq
`ifdef  SECOND_TIMER_IS_WATCHDOG
163 16 dgisselq
                btn_reset <= ((r_button)&&(zip_cpu_int))||(tmrb_int);
164 25 dgisselq
`else
165
                btn_reset <= ((r_button)&&(zip_cpu_int));
166
`endif
167 16 dgisselq
        end
168
        assign  cpu_reset = btn_reset;
169
`else
170
        assign  cpu_reset = 1'b0;
171
`endif
172
 
173 2 dgisselq
        zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
174 16 dgisselq
                thecpu(i_clk, btn_reset, // 1'b0,
175 2 dgisselq
                        // Zippys wishbone interface
176
                        wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data,
177
                                wb_ack, wb_stall, wb_idata, wb_err,
178
                        w_interrupt, zip_cpu_int,
179 16 dgisselq
                        // Debug wishbone interface -- not really used
180 2 dgisselq
                        1'b0, 1'b0,1'b0, 1'b0, 32'h00,
181 16 dgisselq
                                zip_dbg_ack, zip_dbg_stall, zip_dbg_data,
182
                        zip_scope_data);
183 2 dgisselq
        generate
184
        if (ZA < BAW)
185
                assign  wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
186
        else
187
                assign  wb_addr = w_zip_addr;
188
        endgenerate
189
 
190
        wire    io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
191
                        rtc_sel, none_sel, many_sel;
192 25 dgisselq
        wire    flash_ack, scop_ack, cfg_ack, mem_ack, many_ack;
193 2 dgisselq
        wire    rtc_ack, rtc_stall;
194
`ifdef  INCLUDE_RTC
195
        assign  rtc_stall = 1'b0;
196
`endif
197
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
198 4 dgisselq
        reg     io_ack;
199 2 dgisselq
 
200
        wire    [31:0]   flash_data, scop_data, cfg_data, mem_data, pwm_data,
201
                        spio_data, gpio_data, uart_data;
202
        reg     [31:0]   io_data;
203
        reg     [(BAW-1):0]      bus_err_addr;
204
 
205
        assign  wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
206
`ifdef  INCLUDE_RTC
207
                                ||(rtc_ack)
208
`endif
209
                                ||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
210
        assign  wb_stall = ((io_sel)&&(io_stall))
211
                        ||((scop_sel)&&(scop_stall))
212
                        ||((cfg_sel)&&(cfg_stall))
213
                        ||((mem_sel)&&(mem_stall))
214
`ifdef  INCLUDE_RTC
215
                        ||((rtc_sel)&&(rtc_stall))
216
`endif
217
                        ||((flash_sel||flctl_sel)&&(flash_stall));
218
                        // (none_sel)&&(1'b0)
219
 
220
        /*
221
        assign  wb_idata = (io_ack)?io_data
222
                        : ((scop_ack)?scop_data
223
                        : ((cfg_ack)?cfg_data
224
                        : ((mem_ack)?mem_data
225
                        : ((flash_ack)?flash_data
226
                        : 32'h00))));
227
        */
228
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
229
                        : ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
230 4 dgisselq
                        : ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
231 2 dgisselq
        assign  wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
232
 
233
        // Addresses ...
234
        //      0000 xxxx       configuration/control registers
235
        //      1 xxxx xxxx xxxx xxxx xxxx      Up-sampler taps
236
        assign  io_sel   =((wb_cyc)&&(io_addr[5:0]==6'h1));
237 25 dgisselq
        assign  scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
238 2 dgisselq
        assign  flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
239
        assign  cfg_sel  =((wb_cyc)&&(io_addr[5:2]==4'h1));
240
        // zip_sel is not on the bus at this point
241
`ifdef  INCLUDE_RTC
242
        assign  rtc_sel  =((wb_cyc)&&(io_addr[5:3]==3'h1));
243
`endif
244
        assign  mem_sel  =((wb_cyc)&&(io_addr[5:4]==2'h1));
245
        assign  flash_sel=((wb_cyc)&&(io_addr[5]));
246
 
247 25 dgisselq
`ifdef  FULL_BUSERR_CALCULATION
248 16 dgisselq
        assign  none_sel =((wb_cyc)&&(wb_stb)&&
249
                        ((io_addr==6'h0)
250 25 dgisselq
                        ||((~io_addr[5])&&(|wb_addr[22:14]))
251
                        ||((io_addr[5:4]==2'b00)&&(|wb_addr[12])))
252 16 dgisselq
                        );
253 2 dgisselq
        assign  many_sel =((wb_cyc)&&(wb_stb)&&(
254
                         {3'h0, io_sel}
255
                        +{3'h0, flctl_sel}
256 11 dgisselq
                        +{3'h0, scop_sel}
257 2 dgisselq
                        +{3'h0, cfg_sel}
258 11 dgisselq
                        +{3'h0, rtc_sel}
259 2 dgisselq
                        +{3'h0, mem_sel}
260
                        +{3'h0, flash_sel} > 1));
261
 
262
        assign  many_ack =((wb_cyc)&&(
263
                         {3'h0, io_ack}
264
                        +{3'h0, scop_ack}
265
                        +{3'h0, cfg_ack}
266
`ifdef  INCLUDE_RTC
267
                        +{3'h0, rtc_ack}
268
`endif
269
                        +{3'h0, mem_ack}
270
                        +{3'h0, flash_ack} > 1));
271 25 dgisselq
`else
272
        assign  many_ack = 1'b0;
273
        assign  many_sel = 1'b0;
274
        assign  none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
275
`endif
276
        wire            flash_interrupt, scop_interrupt, tmra_int,
277 2 dgisselq
                        rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
278
 
279
 
280
        //
281
        //
282
        //
283
        reg             rx_rdy;
284
        wire    [10:0]   int_vector;
285 25 dgisselq
        assign  int_vector = {
286
                                        gpio_int, pwm_int, keypad_int,
287 13 dgisselq
                                (~o_tx_stb), rx_rdy,
288 25 dgisselq
`ifdef  SECOND_TIMER_IS_WATCHDOG
289
                                1'b0,
290
`else
291
                                tmrb_int,
292
`endif
293
                                tmra_int,
294 2 dgisselq
                                rtc_interrupt, scop_interrupt,
295
                                wb_err, button_int };
296
 
297
        wire    [31:0]   pic_data;
298 4 dgisselq
        icontrol #(11)  pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
299 2 dgisselq
                                        &&(wb_addr[3:0]==4'h0)&&(wb_we),
300
                        wb_data, pic_data, int_vector, w_interrupt);
301
 
302 8 dgisselq
        initial bus_err_addr = 0; // `DATESTAMP;
303 2 dgisselq
        always @(posedge i_clk)
304
                if (wb_err)
305
                        bus_err_addr <= wb_addr;
306
 
307 11 dgisselq
        wire    [31:0]   timer_a, timer_b;
308 2 dgisselq
        wire            zta_ack, zta_stall, ztb_ack, ztb_stall;
309 25 dgisselq
        ziptimer        #(32,31,1)
310 4 dgisselq
                zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
311 16 dgisselq
`ifdef  INCLUDE_SECOND_TIMER
312 2 dgisselq
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
313 16 dgisselq
`else
314
                                (wb_stb)&&(io_sel)&&(wb_addr[3:1]==3'h1),
315
`endif
316 2 dgisselq
                                wb_we, wb_data, zta_ack, zta_stall, timer_a,
317
                                tmra_int);
318 16 dgisselq
`ifdef  INCLUDE_SECOND_TIMER
319 25 dgisselq
`ifdef  SECOND_TIMER_IS_WATCHDOG
320
        ziptimer        #(32,31,0)
321 16 dgisselq
                zipt_b(i_clk, cpu_reset, 1'b1, wb_cyc,
322 2 dgisselq
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
323
                                wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
324
                                tmrb_int);
325 16 dgisselq
`else
326 25 dgisselq
        ziptimer        #(32,31,1)
327
                zipt_b(i_clk, cpu_reset, 1'b1, wb_cyc,
328
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
329
                                wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
330
                                tmrb_int);
331
`endif
332
`else
333 16 dgisselq
        // assign       timer_b = 32'h000;
334
        assign  timer_b = timer_a;
335
        assign  tmrb_int = 1'b0;
336
`endif
337 2 dgisselq
 
338
        wire    [31:0]   rtc_data;
339
`ifdef  INCLUDE_RTC
340
        wire    rtcd_ack, rtcd_stall, ppd;
341
        // rtcdate      thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
342
                        // wb_data, rtcd_ack, rtcd_stall, date_data);
343
        reg     r_rtc_ack;
344
        initial r_rtc_ack = 1'b0;
345
        always @(posedge i_clk)
346
                r_rtc_ack <= ((wb_stb)&&(rtc_sel));
347
        assign  rtc_ack = r_rtc_ack;
348
 
349
        rtclight
350 8 dgisselq
                #(23'h35afe5,23,0,0)      // 80 MHz clock
351 2 dgisselq
                thetime(i_clk, wb_cyc,
352
                        ((wb_stb)&&(rtc_sel)), wb_we,
353
                        { 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
354
                        rtc_interrupt, ppd);
355
`else
356
        assign  rtc_interrupt = 1'b0;
357
        assign  rtc_data = 32'h00;
358
        assign  rtc_ack  = 1'b0;
359
`endif
360
 
361
        always @(posedge i_clk)
362
                case(wb_addr[3:0])
363
                        4'h0: io_data <= pic_data;
364
                        4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr };
365
                        4'h2: io_data <= timer_a;
366
                        4'h3: io_data <= timer_b;
367
                        4'h4: io_data <= pwm_data;
368
                        4'h5: io_data <= spio_data;
369
                        4'h6: io_data <= gpio_data;
370
                        4'h7: io_data <= uart_data;
371
                        default: io_data <= `DATESTAMP;
372
                        // 4'h8: io_data <= `DATESTAMP;
373
                endcase
374
        always @(posedge i_clk)
375
                io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel);
376
        assign  io_stall = 1'b0;
377
 
378
        wire    pwm_ack, pwm_stall;
379 12 dgisselq
        wbpwmaudio      #(14'd10000,2,0,14)
380
                theaudio(i_clk, wb_cyc,
381
                                ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)),
382
                                        wb_we, 1'b0, wb_data,
383
                                pwm_ack, pwm_stall, pwm_data, o_pwm,
384
                                        o_pwm_aux, //={pwm_shutdown_n,pwm_gain}
385
                                        pwm_int);
386 2 dgisselq
 
387
        //
388
        // Special Purpose I/O: Keypad, button, LED status and control
389
        //
390 16 dgisselq
        wire    [3:0]    w_led;
391 2 dgisselq
        spio    thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
392 16 dgisselq
                        wb_data, spio_data, o_kp_col, i_kp_row, i_btn, w_led,
393 2 dgisselq
                        keypad_int, button_int);
394 16 dgisselq
        assign  o_led = { w_led[3]|w_interrupt,w_led[2]|zip_cpu_int,w_led[1:0] };
395 2 dgisselq
 
396
        //
397
        // General purpose (sort of) I/O:  (Bottom two bits robbed in each
398
        // direction for an I2C link at the toplevel.v design)
399
        //
400
        wbgpio  #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
401
                        (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
402
                        wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
403
 
404
        //
405
        //
406
        //      Rudimentary serial port control
407
        //
408
        reg     [7:0]    r_rx_data;
409
        // Baud rate is set by clock rate / baud rate.
410
        // Thus, 80MHz / 115200MBau
411
        //      = 694.4, or about 0x2b6. 
412
        // although the CPU might struggle to keep up at this speed without a
413
        // hardware buffer.
414
        //
415
        // We'll add the flag for two stop bits.
416 7 dgisselq
        // assign       o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
417
        assign  o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1
418 2 dgisselq
 
419
        initial o_tx_stb = 1'b0;
420
        initial o_tx_data = 8'h00;
421
        always @(posedge i_clk)
422 4 dgisselq
                if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
423 2 dgisselq
                begin
424
                        o_tx_data <= wb_data[7:0];
425
                        o_tx_stb <= 1'b1;
426
                end
427
                else if ((o_tx_stb)&&(~i_tx_busy))
428
                        o_tx_stb <= 1'b0;
429
        initial rx_rdy = 1'b0;
430
        always @(posedge i_clk)
431
                if (i_rx_stb)
432
                        r_rx_data <= i_rx_data;
433
        always @(posedge i_clk)
434
        begin
435 4 dgisselq
                if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
436 2 dgisselq
                        rx_rdy <= i_rx_stb;
437
                else if (i_rx_stb)
438
                        rx_rdy <= (rx_rdy | i_rx_stb);
439
        end
440 12 dgisselq
        assign  o_uart_cts = (~rx_rdy);
441 2 dgisselq
        assign  uart_data = { 23'h0, ~rx_rdy, r_rx_data };
442 4 dgisselq
        //
443
        // uart_ack gets returned as part of io_ack, since that happens when
444
        // io_sel and wb_stb are defined
445
        //
446
        // always @(posedge i_clk)
447
                // uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
448 2 dgisselq
 
449
 
450
 
451
        //
452
        //      FLASH MEMORY CONFIGURATION ACCESS
453
        //
454
        wbqspiflash #(24)       flashmem(i_clk,
455 11 dgisselq
                wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
456 4 dgisselq
                        wb_addr[(24-3):0], wb_data,
457 2 dgisselq
                flash_ack, flash_stall, flash_data,
458
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
459
                flash_interrupt);
460
 
461
        //
462
        //      MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
463
        //
464
        wire    [31:0]   cfg_scope;
465
`ifdef  FANCY_ICAP_ACCESS
466
        wbicape6        fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
467
                                wb_addr[5:0], wb_data,
468
                                cfg_ack, cfg_stall, cfg_data,
469
                                cfg_scope);
470
`else
471
        reg     r_cfg_ack;
472
        always @(posedge i_clk)
473
                r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb);
474
        assign  cfg_ack   = r_cfg_ack;
475
        assign  cfg_stall = 1'b0;
476
        assign  cfg_data  = 32'h00;
477
        assign  cfg_scope = 32'h00;
478
`endif
479
 
480
 
481
        //
482
        //      ON-CHIP RAM MEMORY ACCESS
483
        //
484 4 dgisselq
`ifdef  IMPLEMENT_ONCHIP_RAM
485 2 dgisselq
        memdev  #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
486
                        wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
487 4 dgisselq
`else
488
        assign  mem_data = 32'h00;
489
        assign  mem_stall = 1'b0;
490
        reg     r_mem_ack;
491
        always @(posedge i_clk)
492
                r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
493
        assign  mem_ack = r_mem_ack;
494
`endif
495 2 dgisselq
 
496
        //
497
        //
498
        //      WISHBONE SCOPE
499
        //
500
        //
501
        //
502
        //
503
        wire    [31:0]   scop_cfg_data;
504
        wire            scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
505 7 dgisselq
`ifdef  DBG_SCOPE
506 2 dgisselq
        wire            scop_cfg_trigger;
507
        assign  scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
508 16 dgisselq
        // wire scop_trigger = scop_cfg_trigger;
509
        wire    scop_trigger = (zip_cpu_int) || (cpu_reset);
510
`ifdef  COMPRESSED_SCOPE
511
        wbscopc #(5'ha)
512
`else
513
        wbscope #(5'ha)
514
`endif
515
        wbcfgscope(i_clk, 1'b1, scop_trigger,
516 28 dgisselq
`ifdef  COMPRESSED_SCOPE
517
                // cfg_scope[30:0],
518 16 dgisselq
                zip_scope_data[30:0],
519 28 dgisselq
`else
520
                // cfg_scope[31:0],
521
                zip_scope_data[31:0],
522
`endif
523 2 dgisselq
                // Wishbone interface
524 4 dgisselq
                i_clk, wb_cyc, (wb_stb)&&(scop_sel),
525 2 dgisselq
                                wb_we, wb_addr[0], wb_data,
526
                        scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
527
                scop_cfg_interrupt);
528 4 dgisselq
`else
529
        reg     r_scop_cfg_ack;
530
        always @(posedge i_clk)
531
                r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
532
        assign  scop_cfg_ack = r_scop_cfg_ack;
533
        assign  scop_cfg_data = 32'h000;
534
        assign  scop_cfg_stall= 1'b0;
535 2 dgisselq
`endif
536
 
537
        assign  scop_interrupt = scop_cfg_interrupt;
538
        assign  scop_ack   = scop_cfg_ack;
539
        assign  scop_stall = scop_cfg_stall;
540
        assign  scop_data  = scop_cfg_data;
541
 
542
endmodule
543
 

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