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[/] [s6soc/] [trunk/] [rtl/] [cpu/] [idecode.v] - Blame information for rev 30

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    idecode.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This RTL file specifies how instructions are to be decoded
8
//              into their underlying meanings.  This is specifically a version
9
//      designed to support a "Next Generation", or "Version 2" instruction
10
//      set as (currently) activated by the OPT_NEW_INSTRUCTION_SET option
11
//      in cpudefs.v.
12
//
13
//      I expect to (eventually) retire the old instruction set, at which point
14
//      this will become the default instruction set decoder.
15
//
16
//
17
// Creator:     Dan Gisselquist, Ph.D.
18
//              Gisselquist Technology, LLC
19
//
20
///////////////////////////////////////////////////////////////////////////////
21
//
22
// Copyright (C) 2015, Gisselquist Technology, LLC
23
//
24
// This program is free software (firmware): you can redistribute it and/or
25
// modify it under the terms of  the GNU General Public License as published
26
// by the Free Software Foundation, either version 3 of the License, or (at
27
// your option) any later version.
28
//
29
// This program is distributed in the hope that it will be useful, but WITHOUT
30
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
31
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
32
// for more details.
33
//
34
// License:     GPL, v3, as defined and found on www.gnu.org,
35
//              http://www.gnu.org/licenses/gpl.html
36
//
37
//
38
///////////////////////////////////////////////////////////////////////////////
39
//
40
//
41
//
42
`define CPU_CC_REG      4'he
43
`define CPU_PC_REG      4'hf
44
//
45
`include "cpudefs.v"
46
//
47
//
48
//
49
module  idecode(i_clk, i_rst, i_ce, i_stalled,
50
                i_instruction, i_gie, i_pc, i_pf_valid,
51
                        i_illegal,
52
                o_phase, o_illegal,
53
                o_pc, o_gie,
54
                o_dcdR, o_dcdA, o_dcdB, o_I, o_zI,
55
                o_cond, o_wF,
56
                o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
57
                o_wR, o_rA, o_rB,
58
                o_early_branch, o_branch_pc, o_ljmp,
59
                o_pipe
60
                );
61
        parameter       ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1,
62
                        IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH;
63
        input                   i_clk, i_rst, i_ce, i_stalled;
64
        input   [31:0]           i_instruction;
65
        input                   i_gie;
66
        input   [(AW-1):0]       i_pc;
67
        input                   i_pf_valid, i_illegal;
68
        output  wire            o_phase;
69
        output  reg             o_illegal;
70
        output  reg     [(AW-1):0]       o_pc;
71
        output  reg             o_gie;
72
        output  reg     [6:0]    o_dcdR, o_dcdA, o_dcdB;
73
        output  wire    [31:0]   o_I;
74 30 dgisselq
        output  wire            o_zI;
75 2 dgisselq
        output  reg     [3:0]    o_cond;
76
        output  reg             o_wF;
77
        output  reg     [3:0]    o_op;
78 11 dgisselq
        output  reg             o_ALU, o_M, o_DV, o_FP, o_break;
79
        output  wire            o_lock;
80 2 dgisselq
        output  reg             o_wR, o_rA, o_rB;
81
        output  wire            o_early_branch;
82
        output  wire    [(AW-1):0]       o_branch_pc;
83
        output  wire            o_ljmp;
84 11 dgisselq
        output  wire            o_pipe;
85 2 dgisselq
 
86
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
87
        wire                    o_dcd_early_branch;
88
        wire    [(AW-1):0]       o_dcd_branch_pc;
89 11 dgisselq
`ifdef  OPT_PIPELINED
90 30 dgisselq
        reg     r_lock, r_pipe, r_zI;
91 11 dgisselq
`endif
92 2 dgisselq
 
93
 
94
        wire    [4:0]    w_op;
95 11 dgisselq
        wire            w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop;
96 2 dgisselq
        wire    [4:0]    w_dcdR, w_dcdB, w_dcdA;
97
        wire            w_dcdR_pc, w_dcdR_cc;
98
        wire            w_dcdA_pc, w_dcdA_cc;
99
        wire            w_dcdB_pc, w_dcdB_cc;
100
        wire    [3:0]    w_cond;
101
        wire            w_wF, w_dcdM, w_dcdDV, w_dcdFP;
102
        wire            w_wR, w_rA, w_rB, w_wR_n;
103
        wire            w_ljmp;
104 11 dgisselq
        wire    [31:0]   iword;
105 2 dgisselq
 
106
 
107
`ifdef  OPT_VLIW
108
        reg     [16:0]   r_nxt_half;
109
        assign  iword = (o_phase)
110
                                // set second half as a NOOP ... but really 
111
                                // shouldn't matter
112
                        ? { r_nxt_half[16:7], 1'b0, r_nxt_half[6:0], 5'b11000, 3'h7, 6'h00 }
113
                        : i_instruction;
114
`else
115
        assign  iword = { 1'b0, i_instruction[30:0] };
116
`endif
117
 
118 11 dgisselq
        generate
119
        if (EARLY_BRANCHING != 0)
120
                assign  w_ljmp = (iword == 32'h7c87c000);
121
        else
122
                assign  w_ljmp = 1'b0;
123
        endgenerate
124
 
125
 
126 2 dgisselq
        assign  w_op= iword[26:22];
127
        assign  w_mov    = (w_op      == 5'h0f);
128
        assign  w_ldi    = (w_op[4:1] == 4'hb);
129 11 dgisselq
        assign  w_brev   = (w_op      == 5'hc);
130 2 dgisselq
        assign  w_cmptst = (w_op[4:1] == 4'h8);
131 11 dgisselq
        assign  w_ldilo  = (w_op[4:0] == 5'h9);
132 2 dgisselq
        assign  w_ALU    = (~w_op[4]);
133
 
134
        // 4 LUTs
135 11 dgisselq
        //
136
        // Two parts to the result register: the register set, given for
137
        // moves in i_word[18] but only for the supervisor, and the other
138
        // four bits encoded in the instruction.
139
        //
140 2 dgisselq
        assign  w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
141
                                iword[30:27] };
142 11 dgisselq
        // 2 LUTs
143
        //
144
        // If the result register is either CC or PC, and this would otherwise
145
        // be a floating point instruction with floating point opcode of 0,
146
        // then this is a NOOP.
147
        assign  w_noop   = (w_op[4:0] == 5'h18)&&(w_dcdR[3:1] == 3'h7);
148
 
149 2 dgisselq
        // 4 LUTs
150
        assign  w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
151
                                iword[17:14] };
152
 
153
        // 0 LUTs
154
        assign  w_dcdA = w_dcdR;
155
        // 2 LUTs, 1 delay each
156
        assign  w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
157
        assign  w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
158
        // 0 LUTs
159
        assign  w_dcdA_pc = w_dcdR_pc;
160
        assign  w_dcdA_cc = w_dcdR_cc;
161
        // 2 LUTs, 1 delays each
162
        assign  w_dcdB_pc = (w_dcdB[3:0] == `CPU_PC_REG);
163
        assign  w_dcdB_cc = (w_dcdB[3:0] == `CPU_CC_REG);
164
 
165
        // Under what condition will we execute this
166
        // instruction?  Only the load immediate instruction
167
        // is completely unconditional.
168
        //
169
        // 3+4 LUTs
170
        assign  w_cond = (w_ldi) ? 4'h8 :
171
                        (iword[31])?{(iword[20:19]==2'b00),
172
                                        1'b0,iword[20:19]}
173
                        : { (iword[21:19]==3'h0), iword[21:19] };
174
 
175
        // 1 LUT
176
        assign  w_dcdM    = (w_op[4:1] == 4'h9);
177
        // 1 LUT
178
        assign  w_dcdDV   = (w_op[4:1] == 4'ha);
179
        // 1 LUT
180
        assign  w_dcdFP   = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7);
181
        // 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before)
182
        //      Everything reads A but ... NOOP/BREAK/LOCK, LDI, LOD, MOV
183
        assign  w_rA     = (w_dcdFP)
184
                                // Divide's read A
185
                                ||(w_dcdDV)
186
                                // ALU read's A, unless it's a MOV to A
187
                                // This includes LDIHI/LDILO
188
                                ||((~w_op[4])&&(w_op[3:0]!=4'hf))
189
                                // STO's read A
190
                                ||((w_dcdM)&&(w_op[0]))
191
                                // Test/compares
192
                                ||(w_op[4:1]== 4'h8);
193
        // 1 LUTs -- do we read a register for operand B?  Specifically, do
194
        // we need to stall if the register is not (yet) ready?
195 11 dgisselq
        assign  w_rB     = (w_mov)||((iword[18])&&(~w_ldi));
196 2 dgisselq
        // 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
197
        assign  w_wR_n   = ((w_dcdM)&&(w_op[0]))
198
                                ||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
199
                                ||(w_cmptst);
200
        assign  w_wR     = ~w_wR_n;
201
        //
202
        // 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits)
203
        //      
204
        //      This'd be 4 LUTs, save that we have the carve out for NOOPs
205
        //      and writes to the PC/CC register(s).
206
        assign  w_wF     = (w_cmptst)
207
                        ||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
208 11 dgisselq
                                ||((w_ALU)&&(~w_mov)&&(~w_ldilo)&&(~w_brev)
209 2 dgisselq
                                        &&(iword[30:28] != 3'h7))));
210
 
211
        // Bottom 13 bits: no LUT's
212
        // w_dcd[12: 0] -- no LUTs
213
        // w_dcd[   13] -- 2 LUTs
214
        // w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay
215
        // w_dcd[22:18] : 5 LUTs, 1 delay (assuming high bit is o/w determined)
216
        reg     [22:0]   r_I;
217
        wire    [22:0]   w_I, w_fullI;
218
        wire            w_Iz;
219
 
220
        assign  w_fullI = (w_ldi) ? { iword[22:0] } // LDI
221
                        :((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } // Move
222
                        :((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] }
223
                        : { {(23-14){iword[13]}}, iword[13:0] }
224
                        ));
225
 
226
`ifdef  OPT_VLIW
227
        wire    [5:0]    w_halfI;
228
        assign  w_halfI = (w_ldi) ? iword[5:0]
229
                                :((iword[5]) ? 6'h00 : {iword[4],iword[4:0]});
230
        assign  w_I  = (iword[31])? {{(23-6){w_halfI[5]}}, w_halfI }:w_fullI;
231
`else
232
        assign  w_I  = w_fullI;
233
`endif
234
        assign  w_Iz = (w_I == 0);
235
 
236
 
237
`ifdef  OPT_VLIW
238
        //
239
        // The o_phase parameter is special.  It needs to let the software
240
        // following know that it cannot break/interrupt on an o_phase asserted
241
        // instruction, lest the break take place between the first and second
242
        // half of a VLIW instruction.  To do this, o_phase must be asserted
243
        // when the first instruction half is valid, but not asserted on either
244
        // a 32-bit instruction or the second half of a 2x16-bit instruction.
245
        reg     r_phase;
246
        initial r_phase = 1'b0;
247
        always @(posedge i_clk)
248
                if (i_rst) // When no instruction is in the pipe, phase is zero
249
                        r_phase <= 1'b0;
250
                else if (i_ce)
251
                        r_phase <= (o_phase)? 1'b0:(i_instruction[31]);
252
        // Phase is '1' on the first instruction of a two-part set
253
        // But, due to the delay in processing, it's '1' when our output is
254
        // valid for that first part, but that'll be the same time we
255
        // are processing the second part ... so it may look to us like a '1'
256
        // on the second half of processing.
257
 
258
        assign  o_phase = r_phase;
259
`else
260
        assign  o_phase = 1'b0;
261
`endif
262
 
263
 
264
        initial o_illegal = 1'b0;
265
        always @(posedge i_clk)
266
                if (i_rst)
267
                        o_illegal <= 1'b0;
268
                else if (i_ce)
269
                begin
270
`ifdef  OPT_VLIW
271
                        o_illegal <= (i_illegal);
272
`else
273
                        o_illegal <= ((i_illegal) || (i_instruction[31]));
274
`endif
275
                        if ((IMPLEMENT_MPY!=1)&&(w_op[4:1]==4'h5))
276
                                o_illegal <= 1'b1;
277
 
278
                        if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV))
279
                                o_illegal <= 1'b1;
280
                        else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7))
281
                                o_illegal <= 1'b1;
282
 
283
 
284
                        if ((IMPLEMENT_FPU!=0)&&(w_dcdFP)&&(w_dcdR[3:1]==3'h7))
285
                                o_illegal <= 1'b1;
286
                        else if ((IMPLEMENT_FPU==0)&&(w_dcdFP))
287
                                o_illegal <= 1'b1;
288
 
289
                        if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)
290
                                &&(
291 11 dgisselq
                                        (w_op[2:0] != 3'h1)      // BREAK
292
`ifdef  OPT_PIPELINED
293
                                        &&(w_op[2:0] != 3'h2)    // LOCK
294
`endif
295 2 dgisselq
                                        &&(w_op[2:0] != 3'h0)))  // NOOP
296
                                o_illegal <= 1'b1;
297
                end
298
 
299
 
300
        always @(posedge i_clk)
301
                if (i_ce)
302
                begin
303
`ifdef  OPT_VLIW
304
                        if (~o_phase)
305
                        begin
306
                                o_gie<= i_gie;
307
                                // i.e. dcd_pc+1
308
                                o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
309
                        end
310
`else
311
                        o_gie<= i_gie;
312
                        o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
313
`endif
314
 
315
                        // Under what condition will we execute this
316
                        // instruction?  Only the load immediate instruction
317
                        // is completely unconditional.
318
                        o_cond <= w_cond;
319
                        // Don't change the flags on conditional instructions,
320
                        // UNLESS: the conditional instruction was a CMP
321
                        // or TST instruction.
322
                        o_wF <= w_wF;
323
 
324
                        // Record what operation/op-code (4-bits) we are doing
325
                        //      Note that LDI magically becomes a MOV
326
                        //      instruction here.  That way it's a pass through
327
                        //      the ALU.  Likewise, the two compare instructions
328
                        //      CMP and TST becomes SUB and AND here as well.
329
                        // We keep only the bottom four bits, since we've
330
                        // already done the rest of the decode necessary to 
331
                        // settle between the other instructions.  For example,
332
                        // o_FP plus these four bits uniquely defines the FP
333
                        // instruction, o_DV plus the bottom of these defines
334
                        // the divide, etc.
335 11 dgisselq
                        o_op <= (w_ldi)||(w_noop)? 4'hf:w_op[3:0];
336 2 dgisselq
 
337
                        // Default values
338
                        o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR};
339
                        o_dcdA <= { w_dcdA_cc, w_dcdA_pc, w_dcdA};
340
                        o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
341
                        o_wR  <= w_wR;
342
                        o_rA  <= w_rA;
343
                        o_rB  <= w_rB;
344
                        r_I    <= w_I;
345 30 dgisselq
`ifdef  OPT_PIPELINED
346
                        r_zI   <= w_Iz;
347
`endif
348 2 dgisselq
 
349 11 dgisselq
                        // Turn a NOOP into an ALU operation--subtract in 
350
                        // particular, although it doesn't really matter as long
351
                        // as it doesn't take longer than one clock.  Note
352
                        // also that this depends upon not setting any registers
353
                        // or flags, which should already be true.
354
                        o_ALU  <=  (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); // 2 LUT
355 2 dgisselq
                        o_M    <=  w_dcdM;
356
                        o_DV   <=  w_dcdDV;
357
                        o_FP   <=  w_dcdFP;
358
 
359
                        o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001);
360 11 dgisselq
`ifdef  OPT_PIPELINED
361
                        r_lock  <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010);
362
`endif
363 2 dgisselq
`ifdef  OPT_VLIW
364
                        r_nxt_half <= { iword[31], iword[13:5],
365
                                ((iword[21])? iword[20:19] : 2'h0),
366
                                iword[4:0] };
367
`endif
368
                end
369
 
370 11 dgisselq
`ifdef  OPT_PIPELINED
371
        assign  o_lock = r_lock;
372 30 dgisselq
        assign  o_zI = r_zI;
373 11 dgisselq
`else
374
        assign  o_lock = 1'b0;
375 30 dgisselq
        assign  o_zI = 1'b0;
376 11 dgisselq
`endif
377
 
378 2 dgisselq
        generate
379
        if (EARLY_BRANCHING!=0)
380
        begin
381
                reg                     r_early_branch, r_ljmp;
382
                reg     [(AW-1):0]       r_branch_pc;
383
 
384
                initial r_ljmp = 1'b0;
385
                always @(posedge i_clk)
386
                        if (i_rst)
387
                                r_ljmp <= 1'b0;
388
                        else if ((i_ce)&&(i_pf_valid))
389
                                r_ljmp <= (w_ljmp);
390
                assign  o_ljmp = r_ljmp;
391
 
392
                always @(posedge i_clk)
393
                if (i_rst)
394
                        r_early_branch <= 1'b0;
395
                else if ((i_ce)&&(i_pf_valid))
396
                begin
397
                        if (r_ljmp)
398
                                // LOD (PC),PC
399
                                r_early_branch <= 1'b1;
400
                        else if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3]))
401
                        begin
402
                                if (w_op[4:1] == 4'hb) // LDI to PC
403
                                        // LDI x,PC
404
                                        r_early_branch     <= 1'b1;
405
                                else if ((w_op[4:0]==5'h02)&&(~iword[18]))
406
                                        // Add x,PC
407
                                        r_early_branch     <= 1'b1;
408
                                else begin
409
                                        r_early_branch     <= 1'b0;
410
                                end
411
                        end else
412
                                r_early_branch <= 1'b0;
413
                end else if (i_ce)
414
                        r_early_branch <= 1'b0;
415
 
416
                always @(posedge i_clk)
417
                        if (i_ce)
418
                        begin
419
                                if (r_ljmp)
420
                                        r_branch_pc <= iword[(AW-1):0];
421
                                else if (w_op[4:1] == 4'hb) // LDI
422
                                        r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]};
423
                                else // Add x,PC
424
                                r_branch_pc <= i_pc
425
                                        + {{(AW-17){iword[17]}},iword[16:0]}
426
                                        + {{(AW-1){1'b0}},1'b1};
427
                        end
428
 
429
                assign  o_early_branch     = r_early_branch;
430
                assign  o_branch_pc        = r_branch_pc;
431
        end else begin
432
                assign  o_early_branch = 1'b0;
433
                assign  o_branch_pc = {(AW){1'b0}};
434
                assign  o_ljmp = 1'b0;
435
        end endgenerate
436
 
437
 
438
        // To be a pipeable operation there must be ...
439
        //      1. Two valid adjacent instructions
440
        //      2. Both must be memory operations, of the same time (both lods
441
        //              or both stos)
442
        //      3. Both must use the same register base address
443
        //      4. Both must be to the same address, or the address incremented
444
        //              by one
445
        // Note that we're not using iword here ... there's a lot of logic
446
        // taking place, and it's only valid if the new word is not compressed.
447
        //
448 30 dgisselq
`ifdef  OPT_PIPELINED
449 2 dgisselq
        reg     r_valid;
450 11 dgisselq
        reg     r_pipe;
451
        initial r_pipe = 1'b0;
452 2 dgisselq
        always @(posedge i_clk)
453
                if (i_ce)
454 11 dgisselq
                        r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
455 2 dgisselq
                                &&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])
456
                                &&(i_instruction[17:14] == o_dcdB[3:0])
457 11 dgisselq
                                &&(i_instruction[17:14] != o_dcdA[3:0])
458 2 dgisselq
                                &&(i_gie == o_gie)
459
                                &&((i_instruction[21:19]==o_cond[2:0])
460
                                        ||(o_cond[2:0] == 3'h0))
461
                                &&((i_instruction[13:0]==r_I[13:0])
462
                                        ||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
463 11 dgisselq
        assign o_pipe = r_pipe;
464
 
465 2 dgisselq
        always @(posedge i_clk)
466
                if (i_rst)
467
                        r_valid <= 1'b0;
468
                else if ((i_ce)&&(o_ljmp))
469
                        r_valid <= 1'b0;
470
                else if ((i_ce)&&(i_pf_valid))
471
                        r_valid <= 1'b1;
472
                else if (~i_stalled)
473
                        r_valid <= 1'b0;
474 30 dgisselq
`else
475
        assign o_pipe = 1'b0;
476
`endif
477 2 dgisselq
 
478
 
479
        assign  o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
480
 
481
endmodule

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