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[/] [s6soc/] [trunk/] [rtl/] [deppbyte.v] - Blame information for rev 16

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1 11 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    deppbyte.v
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//
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// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
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//
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// Purpose:     This is a very simple DEPP to synchronous byte transfer.  It
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//              is used in place of a serial port.
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//
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//      This approach uses address zero *only*.
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module deppbyte(i_clk,
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        i_astb_n, i_dstb_n, i_write_n,i_depp, o_depp, o_wait,
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        o_rx_stb, o_rx_data,
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        i_tx_stb, i_tx_data, o_tx_busy);
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        input   i_clk;
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        // DEPP interface
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        input                   i_astb_n, i_dstb_n, i_write_n;
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        input           [7:0]    i_depp;
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        output  reg     [7:0]    o_depp;
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        output  wire            o_wait;
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        // Byte-wise interface to the rest of the world
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        output  reg             o_rx_stb;
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        output  reg     [7:0]    o_rx_data;
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        input                   i_tx_stb;
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        input           [7:0]    i_tx_data;
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        output  reg             o_tx_busy;
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        // Synchronize the incoming signals
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        reg     x_dstb_n, x_astb_n, x_write_n,
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                r_dstb_n, r_astb_n, r_write_n,
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                l_dstb_n, l_astb_n, l_write_n;
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        reg     [7:0]    x_depp, r_depp;
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        initial x_dstb_n = 1'b1;
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        initial r_dstb_n = 1'b1;
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        initial l_dstb_n = 1'b1;
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        initial x_astb_n = 1'b1;
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        initial r_astb_n = 1'b1;
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        initial l_astb_n = 1'b1;
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        always @(posedge i_clk)
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        begin
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                { x_dstb_n, x_astb_n, x_write_n, x_depp }
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                        <= { i_dstb_n, i_astb_n, i_write_n, i_depp };
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                { r_dstb_n, r_astb_n, r_write_n, r_depp }
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                        <= { x_dstb_n, x_astb_n, x_write_n, x_depp };
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                { l_dstb_n, l_astb_n, l_write_n } <= { r_dstb_n, r_astb_n, r_write_n };
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        end
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        reg     [7:0]    addr;
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        wire    astb, dstb, w_write;
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        assign  astb = (~r_astb_n)&&(l_astb_n);
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        assign  dstb = (~r_dstb_n)&&(l_dstb_n);
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        assign  w_write= (~r_write_n);
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        initial addr = 8'h00;
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        initial o_rx_stb = 1'b0;
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        always @(posedge i_clk)
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        begin
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                if ((w_write)&&(astb))
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                        addr <= r_depp;
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                if ((w_write)&&(dstb)&&(addr==0))
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                begin
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                        o_rx_stb  <= 1'b1;
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                        o_rx_data <= r_depp;
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                end else
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                        o_rx_stb <= 1'b0;
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        end
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        // Much as I hate to use signals that have not been synchronized with a 
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        // two clock transfer, this line needs to be brought low within 10ms
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        // (less than one clock) of when the strobe lines are brought low, and
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        // raised high again within 10 ms of when the strobe lines are raised
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        // again.
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        assign  o_wait = ((~i_dstb_n)||(~i_astb_n));
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        // For one clock, following any read from address zero, we allow the
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        // port to write one new byte into our interface.  This works because
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        // the interface will guarantee that the strobe signals are inactive
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        // (high) for at least 40ns before attempting a new transaction.
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        //
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        // Just about nothing else works.  'cause we can't allow changes
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        // in the middle of a transaction, and we won't know if the clock
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        // involved is in the middle of a transaction until after the time
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        // has passed.  Therefore, we're going to be busy most of the time
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        // and just allow a byte to pass through on the one (and only) clock
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        // following a transaction.
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        always @(posedge i_clk)
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                o_tx_busy <= ((~l_dstb_n)&&(r_dstb_n)&&(l_write_n)&&(addr == 0))
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                                ? 1'b0 : 1'b1;
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        // If we don't have a byte to write, stuff it with all ones.  The high
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        // bit will then indicate that there's nothing available to the 
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        // interface when it next reads.
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        //
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        // Okay, new philosophy.  Stuff the high bit with ones, allow the other
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        // bits to contain status level information --- should any one wish to
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        // send such.
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        initial o_depp = 8'hff;
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        always @(posedge i_clk)
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                if (~o_tx_busy)
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                        o_depp <= {((i_tx_stb)? i_tx_data[7] : 1'b1),
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                                        i_tx_data[6:0] };
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endmodule

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