OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [txuart.v] - Blame information for rev 16

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 2 dgisselq
//
3
// Filename:    txuart.v
4
//
5 4 dgisselq
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6 2 dgisselq
//
7
// Purpose:     Transmit outputs over a single UART line.
8
//
9
//      To interface with this module, connect it to your system clock,
10
//      pass it the 32 bit setup register (defined below) and the byte
11
//      of data you wish to transmit.  Strobe the i_wr line high for one
12
//      clock cycle, and your data will be off.  Wait until the 'o_busy'
13
//      line is low before strobing the i_wr line again--this implementation
14
//      has NO BUFFER, so strobing i_wr while the core is busy will just
15
//      cause your data to be lost.  The output will be placed on the o_txuart
16
//      output line.  If you wish to set/send a break condition, assert the
17
//      i_break line otherwise leave it low.
18
//
19
//      There is a synchronous reset line, logic high.
20
//
21
//      Now for the setup register.  The register is 32 bits, so that this
22
//      UART may be set up over a 32-bit bus.
23
//
24
//      i_setup[29:28]  Indicates the number of data bits per word.  This will
25
//      either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
26
//      for a six bit word, or 2'b11 for a five bit word.
27
//
28
//      i_setup[27]     Indicates whether or not to use one or two stop bits.
29
//              Set this to one to expect two stop bits, zero for one.
30
//
31
//      i_setup[26]     Indicates whether or not a parity bit exists.  Set this
32
//              to 1'b1 to include parity.
33
//
34
//      i_setup[25]     Indicates whether or not the parity bit is fixed.  Set
35
//              to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
36
//              parity to be set based upon data.  (Both assume the parity
37
//              enable value is set.)
38
//
39
//      i_setup[24]     This bit is ignored if parity is not used.  Otherwise,
40
//              in the case of a fixed parity bit, this bit indicates whether
41
//              mark (1'b1) or space (1'b0) parity is used.  Likewise if the
42
//              parity is not fixed, a 1'b1 selects even parity, and 1'b0
43
//              selects odd.
44
//
45
//      i_setup[23:0]   Indicates the speed of the UART in terms of clocks.
46
//              So, for example, if you have a 200 MHz clock and wish to
47
//              run your UART at 9600 baud, you would take 200 MHz and divide
48
//              by 9600 to set this value to 24'd20834.  Likewise if you wished
49
//              to run this serial port at 115200 baud from a 200 MHz clock,
50
//              you would set the value to 24'd1736
51
//
52
//      Thus, to set the UART for the common setting of an 8-bit word, 
53
//      one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
54
//      would want to set the setup value to:
55
//
56
//      32'h0006c8              // For 115,200 baud, 8 bit, no parity
57
//      32'h005161              // For 9600 baud, 8 bit, no parity
58
//      
59
// Creator:     Dan Gisselquist
60
//              Gisselquist Technology, LLC
61
//
62 4 dgisselq
////////////////////////////////////////////////////////////////////////////////
63 2 dgisselq
//
64 4 dgisselq
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
65 2 dgisselq
//
66 4 dgisselq
// This program is free software (firmware): you can redistribute it and/or
67
// modify it under the terms of  the GNU General Public License as published
68
// by the Free Software Foundation, either version 3 of the License, or (at
69
// your option) any later version.
70 2 dgisselq
//
71 4 dgisselq
// This program is distributed in the hope that it will be useful, but WITHOUT
72
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
73
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
74
// for more details.
75 2 dgisselq
//
76 4 dgisselq
// You should have received a copy of the GNU General Public License along
77
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
78
// target there if the PDF file isn't present.)  If not, see
79
// <http://www.gnu.org/licenses/> for a copy.
80 2 dgisselq
//
81 4 dgisselq
// License:     GPL, v3, as defined and found on www.gnu.org,
82
//              http://www.gnu.org/licenses/gpl.html
83
//
84
//
85
////////////////////////////////////////////////////////////////////////////////
86
//
87
//
88
//
89 2 dgisselq
`define TXU_BIT_ZERO    4'h0
90
`define TXU_BIT_ONE     4'h1
91
`define TXU_BIT_TWO     4'h2
92
`define TXU_BIT_THREE   4'h3
93
`define TXU_BIT_FOUR    4'h4
94
`define TXU_BIT_FIVE    4'h5
95
`define TXU_BIT_SIX     4'h6
96
`define TXU_BIT_SEVEN   4'h7
97
`define TXU_PARITY      4'h8    // Constant 1
98
`define TXU_STOP        4'h9    // Constant 1
99
`define TXU_SECOND_STOP 4'ha
100
// 4'hb // Unused
101
// 4'hc // Unused
102
// `define      TXU_START       4'hd    // An unused state
103
`define TXU_BREAK       4'he
104
`define TXU_IDLE        4'hf
105 4 dgisselq
//
106
//
107 13 dgisselq
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, o_busy);
108 2 dgisselq
        input                   i_clk, i_reset;
109
        input           [29:0]   i_setup;
110
        input                   i_break;
111
        input                   i_wr;
112
        input           [7:0]    i_data;
113 4 dgisselq
        output  reg             o_uart;
114
        output  wire            o_busy;
115 2 dgisselq
 
116
        wire    [27:0]   clocks_per_baud, break_condition;
117
        wire    [1:0]    data_bits;
118
        wire            use_parity, parity_even, dblstop, fixd_parity;
119
        reg     [29:0]   r_setup;
120
        assign  clocks_per_baud = { 4'h0, r_setup[23:0] };
121
        assign  break_condition = { r_setup[23:0], 4'h0 };
122
        assign  data_bits   = r_setup[29:28];
123
        assign  dblstop     = r_setup[27];
124
        assign  use_parity  = r_setup[26];
125
        assign  fixd_parity = r_setup[25];
126
        assign  parity_even = r_setup[24];
127
 
128
        reg     [27:0]   baud_counter;
129
        reg     [3:0]    state;
130
        reg     [7:0]    lcl_data;
131
        reg             calc_parity;
132 4 dgisselq
        reg             r_busy;
133 2 dgisselq
 
134
        initial o_uart = 1'b1;
135 4 dgisselq
        initial r_busy = 1'b1;
136 2 dgisselq
        initial state  = `TXU_IDLE;
137
        // initial      baud_counter = clocks_per_baud;
138
        always @(posedge i_clk)
139
        begin
140
                if (i_reset)
141
                begin
142
                        baud_counter <= clocks_per_baud;
143
                        o_uart <= 1'b1;
144 4 dgisselq
                        r_busy <= 1'b1;
145 2 dgisselq
                        state <= `TXU_IDLE;
146
                        lcl_data <= 8'h0;
147
                        calc_parity <= 1'b0;
148
                end else if (i_break)
149
                begin
150
                        baud_counter <= break_condition;
151
                        o_uart <= 1'b0;
152
                        state <= `TXU_BREAK;
153
                        calc_parity <= 1'b0;
154 4 dgisselq
                        r_busy <= 1'b1;
155 2 dgisselq
                end else if (baud_counter != 0)
156 4 dgisselq
                begin // r_busy needs to be set coming into here
157 2 dgisselq
                        baud_counter <= baud_counter - 28'h01;
158 4 dgisselq
                        r_busy <= 1'b1;
159 2 dgisselq
                end else if (state == `TXU_BREAK)
160
                begin
161
                        state <= `TXU_IDLE;
162 4 dgisselq
                        r_busy <= 1'b1;
163 2 dgisselq
                        o_uart <= 1'b1;
164
                        calc_parity <= 1'b0;
165
                        // Give us two stop bits before becoming available
166
                        baud_counter <= clocks_per_baud<<2;
167
                end else if (state == `TXU_IDLE)        // STATE_IDLE
168
                begin
169
                        // baud_counter <= 0;
170
                        r_setup <= i_setup;
171
                        calc_parity <= 1'b0;
172 4 dgisselq
                        if ((i_wr)&&(~r_busy))
173 2 dgisselq
                        begin   // Immediately start us off with a start bit
174
                                o_uart <= 1'b0;
175 4 dgisselq
                                r_busy <= 1'b1;
176 2 dgisselq
                                case(data_bits)
177
                                2'b00: state <= `TXU_BIT_ZERO;
178
                                2'b01: state <= `TXU_BIT_ONE;
179
                                2'b10: state <= `TXU_BIT_TWO;
180
                                2'b11: state <= `TXU_BIT_THREE;
181
                                endcase
182
                                lcl_data <= i_data;
183
                                baud_counter <= clocks_per_baud-28'h01;
184
                        end else begin // Stay in idle
185
                                o_uart <= 1'b1;
186 4 dgisselq
                                r_busy <= 0;
187 2 dgisselq
                                // lcl_data is irrelevant
188
                                // state <= state;
189
                        end
190
                end else begin
191
                        // One clock tick in each of these states ...
192
                        baud_counter <= clocks_per_baud - 28'h01;
193 4 dgisselq
                        r_busy <= 1'b1;
194 2 dgisselq
                        if (state[3] == 0) // First 8 bits
195
                        begin
196
                                o_uart <= lcl_data[0];
197
                                calc_parity <= calc_parity ^ lcl_data[0];
198
                                if (state == `TXU_BIT_SEVEN)
199
                                        state <= (use_parity)?`TXU_PARITY:`TXU_STOP;
200
                                else
201
                                        state <= state + 1;
202
                                lcl_data <= { 1'b0, lcl_data[7:1] };
203
                        end else if (state == `TXU_PARITY)
204
                        begin
205
                                state <= `TXU_STOP;
206
                                if (fixd_parity)
207
                                        o_uart <= parity_even;
208
                                else
209
                                        o_uart <= calc_parity^((parity_even)? 1'b1:1'b0);
210
                        end else if (state == `TXU_STOP)
211
                        begin // two stop bit(s)
212
                                o_uart <= 1'b1;
213
                                if (dblstop)
214
                                        state <= `TXU_SECOND_STOP;
215
                                else
216
                                        state <= `TXU_IDLE;
217
                                calc_parity <= 1'b0;
218
                        end else // `TXU_SECOND_STOP and default:
219
                        begin
220
                                state <= `TXU_IDLE; // Go back to idle
221
                                o_uart <= 1'b1;
222 4 dgisselq
                                // Still r_busy, since we need to wait
223 2 dgisselq
                                // for the baud clock to finish counting
224
                                // out this last bit.
225
                        end
226
                end
227
        end
228
 
229 4 dgisselq
        assign  o_busy = (r_busy);
230 2 dgisselq
endmodule
231
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.