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[/] [s6soc/] [trunk/] [rtl/] [wbqspiflash.v] - Blame information for rev 16

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    wbspiflash.v
4
//
5
// Project:     Wishbone Controlled Quad SPI Flash Controller
6
//
7
// Purpose:     Access a Quad SPI flash via a WISHBONE interface.  This
8
//              includes both read and write (and erase) commands to the SPI
9
//              flash.  All read/write commands are accomplished using the
10
//              high speed (4-bit) interface.  Further, the device will be
11
//              left/kept in the 4-bit read interface mode between accesses,
12
//              for a minimum read latency.
13
//
14
//      Wishbone Registers (See spec sheet for more detail):
15
//      0: local config(r) / erase commands(w) / deep power down cmds / etc.
16
//      R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
17
//              { last_erased_sector, 14'h00 } if (WIP)
18
//              else { current_sector_being_erased, 14'h00 }
19
//              current if write in progress, last if written
20
//      W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
21
//      1: Configuration register
22
//      2: Status register (R/w)
23
//      3: Read ID (read only)
24
//      (19 bits): Data (R/w, but expect writes to take a while)
25
//              
26
//
27
// Creator:     Dan Gisselquist
28
//              Gisselquist Technology, LLC
29
//
30
///////////////////////////////////////////////////////////////////////////
31
//
32
// Copyright (C) 2015, Gisselquist Technology, LLC
33
//
34
// This program is free software (firmware): you can redistribute it and/or
35
// modify it under the terms of  the GNU General Public License as published
36
// by the Free Software Foundation, either version 3 of the License, or (at
37
// your option) any later version.
38
//
39
// This program is distributed in the hope that it will be useful, but WITHOUT
40
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
41
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
42
// for more details.
43
//
44
// You should have received a copy of the GNU General Public License along
45
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
46
// target there if the PDF file isn't present.)  If not, see
47
// <http://www.gnu.org/licenses/> for a copy.
48
//
49
// License:     GPL, v3, as defined and found on www.gnu.org,
50
//              http://www.gnu.org/licenses/gpl.html
51
//
52
//
53
///////////////////////////////////////////////////////////////////////////
54
//
55 8 dgisselq
`include "flashconfig.v"
56 2 dgisselq
//
57
`define WBQSPI_RESET            0
58
`define WBQSPI_RESET_QUADMODE   1
59
`define WBQSPI_IDLE             2
60
`define WBQSPI_RDIDLE           3       // Idle, but in fast read mode
61
`define WBQSPI_WBDECODE         4
62
`define WBQSPI_RD_DUMMY         5
63
`define WBQSPI_QRD_ADDRESS      6
64
`define WBQSPI_QRD_DUMMY        7
65
`define WBQSPI_READ_CMD         8
66
`define WBQSPI_READ_DATA        9
67
`define WBQSPI_WAIT_TIL_RDIDLE  10
68 11 dgisselq
`define WBQSPI_READ_ID_CMD      11      //
69
`define WBQSPI_READ_ID          12      //
70
`define WBQSPI_READ_STATUS      13      //
71
`define WBQSPI_READ_CONFIG      14      //
72 2 dgisselq
`define WBQSPI_WAIT_TIL_IDLE    15
73
//
74
//
75
`ifndef READ_ONLY
76
//
77
`define WBQSPI_WAIT_WIP_CLEAR   16
78
`define WBQSPI_CHECK_WIP_CLEAR  17
79
`define WBQSPI_CHECK_WIP_DONE   18
80
`define WBQSPI_WEN              19
81
`define WBQSPI_PP               20      // Program page
82
`define WBQSPI_QPP              21      // Program page, 4 bit mode
83
`define WBQSPI_WR_DATA          22
84
`define WBQSPI_WR_BUS_CYCLE     23
85
`define WBQSPI_WRITE_STATUS     24
86
`define WBQSPI_WRITE_CONFIG     25
87
`define WBQSPI_ERASE_WEN        26
88
`define WBQSPI_ERASE_CMD        27
89
`define WBQSPI_ERASE_BLOCK      28
90
`define WBQSPI_CLEAR_STATUS     29
91
`define WBQSPI_IDLE_CHECK_WIP   30
92
//
93
`endif
94
 
95
module  wbqspiflash(i_clk_100mhz,
96
                // Internal wishbone connections
97
                i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
98
                i_wb_addr, i_wb_data,
99
                // Wishbone return values
100
                o_wb_ack, o_wb_stall, o_wb_data,
101
                // Quad Spi connections to the external device
102
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
103
                o_interrupt);
104
        parameter       ADDRESS_WIDTH=22;
105
        input                   i_clk_100mhz;
106
        // Wishbone, inputs first
107
        input                   i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
108
        input           [(ADDRESS_WIDTH-3):0]    i_wb_addr;
109
        input           [31:0]   i_wb_data;
110
        // then outputs
111
        output  reg             o_wb_ack;
112
        output  reg             o_wb_stall;
113
        output  reg     [31:0]   o_wb_data;
114
        // Quad SPI control wires
115
        output  wire            o_qspi_sck, o_qspi_cs_n;
116
        output  wire    [1:0]    o_qspi_mod;
117
        output  wire    [3:0]    o_qspi_dat;
118
        input           [3:0]    i_qspi_dat;
119
        // Interrupt line
120
        output  reg             o_interrupt;
121
        // output       wire    [31:0]  o_debug;
122
 
123
        reg             spi_wr, spi_hold, spi_spd, spi_dir;
124
        reg     [31:0]   spi_in;
125
        reg     [1:0]    spi_len;
126
        wire    [31:0]   spi_out;
127
        wire            spi_valid, spi_busy;
128
        wire            w_qspi_sck, w_qspi_cs_n;
129
        wire    [3:0]    w_qspi_dat;
130
        wire    [1:0]    w_qspi_mod;
131
        // wire [22:0]  spi_dbg;
132
        llqspi  lldriver(i_clk_100mhz,
133
                        spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
134
                                spi_out, spi_valid, spi_busy,
135
                        w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
136
                                i_qspi_dat);
137
 
138
        // Erase status tracking
139
        reg             write_in_progress, write_protect;
140
        reg     [(ADDRESS_WIDTH-17):0]   erased_sector;
141
        reg             dirty_sector;
142
        initial begin
143
                write_in_progress = 1'b0;
144
                erased_sector = 0;
145
                dirty_sector  = 1'b1;
146
                write_protect = 1'b1;
147
        end
148
 
149
        reg     [7:0]    last_status;
150 11 dgisselq
        reg     [9:0]    reset_counter;
151 2 dgisselq
        reg             quad_mode_enabled;
152
        reg             spif_cmd, spif_override;
153
        reg     [(ADDRESS_WIDTH-3):0]    spif_addr;
154
        reg     [31:0]   spif_data;
155
        reg     [5:0]    state;
156
        reg             spif_ctrl, spif_req;
157 11 dgisselq
        reg             alt_cmd, alt_ctrl;
158 2 dgisselq
        wire    [(ADDRESS_WIDTH-17):0]   spif_sector;
159
        assign  spif_sector = spif_addr[(ADDRESS_WIDTH-3):14];
160
 
161
        // assign       o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
162
 
163
        initial state = `WBQSPI_RESET;
164
        initial o_wb_ack   = 1'b0;
165
        initial o_wb_stall = 1'b1;
166
        initial spi_wr     = 1'b0;
167
        initial spi_len    = 2'b00;
168
        initial quad_mode_enabled = 1'b0;
169
        initial o_interrupt = 1'b0;
170 11 dgisselq
        initial spif_override = 1'b1;
171 2 dgisselq
        always @(posedge i_clk_100mhz)
172
        begin
173
        spif_override <= 1'b0;
174 11 dgisselq
        alt_cmd  <= (reset_counter[9:8]==2'b10)?reset_counter[3]:1'b1; // Toggle CS_n
175
        alt_ctrl <= (reset_counter[9:8]==2'b10)?reset_counter[0]:1'b1; // Toggle clock too
176 2 dgisselq
        if (state == `WBQSPI_RESET)
177
        begin
178
                // From a reset, we should
179
                //      Enable the Quad I/O mode
180
                //      Disable the Write protection bits in the status register
181
                //      Chip should already be up and running, so we can start
182
                //      immediately ....
183
                o_wb_ack <= 1'b0;
184
                o_wb_stall <= 1'b1;
185
                spi_wr   <= 1'b0;
186
                spi_hold <= 1'b0;
187
                spi_spd  <= 1'b0;
188
                spi_dir  <= 1'b0;
189
                last_status <= 8'h00;
190
                state <= `WBQSPI_RESET_QUADMODE;
191
                spif_req <= 1'b0;
192
                spif_override <= 1'b1;
193 11 dgisselq
                last_status   <= 8'h00; //
194
                reset_counter <= 10'h3fc; //
195 2 dgisselq
                        // This guarantees that we aren't starting in quad
196
                        // I/O mode, where the FPGA configuration scripts may
197
                        // have left us.
198
        end else if (state == `WBQSPI_RESET_QUADMODE)
199
        begin
200
                // Okay, so here's the problem: we don't know whether or not
201
                // the Xilinx loader started us up in Quad Read I/O idle mode.
202 11 dgisselq
                // So, thus we need to toggle the clock and CS_n, with fewer
203
                // clocks than are necessary to transmit a word.
204
                //
205 2 dgisselq
                // Not ready to handle the bus yet, so stall any requests
206
                o_wb_ack   <= 1'b0;
207
                o_wb_stall <= 1'b1;
208
 
209
                // Do something ...
210 11 dgisselq
                if (reset_counter == 10'h00)
211 2 dgisselq
                begin
212
                        spif_override <= 1'b0;
213
                        state <= `WBQSPI_IDLE;
214 11 dgisselq
 
215
                        // Find out if we can use Quad I/O mode ...
216
                        state <= `WBQSPI_READ_CONFIG;
217
                        spi_wr <= 1'b1;
218
                        spi_len <= 2'b01;
219
                        spi_in <= { 8'h35, 24'h00};
220
 
221 2 dgisselq
                end else begin
222 11 dgisselq
                        reset_counter <= reset_counter - 10'h1;
223 2 dgisselq
                        spif_override <= 1'b1;
224
                end
225
        end else if (state == `WBQSPI_IDLE)
226
        begin
227
                o_interrupt <= 1'b0;
228
                o_wb_stall <= 1'b0;
229
                o_wb_ack <= 1'b0;
230
                spif_cmd   <= i_wb_we;
231
                spif_addr  <= i_wb_addr;
232
                spif_data  <= i_wb_data;
233
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
234
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
235
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
236
                spi_hold <= 1'b0;
237
                spi_spd  <= 1'b0;
238
                spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
239
                // Data register access
240
                if ((i_wb_data_stb)&&(i_wb_cyc))
241
                begin
242
 
243
                        if (i_wb_we) // Request to write a page
244
                        begin
245
`ifdef  READ_ONLY
246
                                o_wb_ack <= 1'b1;
247
                                o_wb_stall <= 1'b0;
248
                        end else
249
`else
250
                                if((~write_protect)&&(~write_in_progress))
251
                                begin // 00
252
                                        spi_wr <= 1'b1;
253
                                        spi_len <= 2'b00; // 8 bits
254
                                        // Send a write enable command
255
                                        spi_in <= { 8'h06, 24'h00 };
256
                                        state <= `WBQSPI_WEN;
257
 
258
                                        o_wb_ack <= 1'b0;
259
                                        o_wb_stall <= 1'b1;
260
                                end else if (write_protect)
261
                                begin // whether or not write-in_progress ...
262
                                        // Do nothing on a write protect
263
                                        // violation
264
                                        //
265
                                        o_wb_ack <= 1'b1;
266
                                        o_wb_stall <= 1'b0;
267
                                end else begin // write is in progress, wait
268
                                        // for it to complete
269
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
270
                                        o_wb_ack <= 1'b0;
271
                                        o_wb_stall <= 1'b1;
272
                                end
273
                        end else if (~write_in_progress)
274
`endif
275
                        begin // Read access, normal mode(s)
276
                                o_wb_ack   <= 1'b0;
277
                                o_wb_stall <= 1'b1;
278
                                spi_wr     <= 1'b1;     // Write cmd to device
279
                                if (quad_mode_enabled)
280
                                begin
281
                                        spi_in <= { 8'heb,
282
                                                {(24-ADDRESS_WIDTH){1'b0}},
283
                                                i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
284
                                        state <= `WBQSPI_QRD_ADDRESS;
285
                                        spi_len    <= 2'b00; // single byte, cmd only
286
                                end else begin
287
                                        spi_in <= { 8'h0b,
288
                                                {(24-ADDRESS_WIDTH){1'b0}},
289
                                                i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
290
                                        state <= `WBQSPI_RD_DUMMY;
291
                                        spi_len    <= 2'b11; // cmd+addr,32bits
292
                                end
293
`ifndef READ_ONLY
294
                        end else begin
295
                                // A write is in progress ... need to stall
296
                                // the bus until the write is complete.
297
                                state <= `WBQSPI_WAIT_WIP_CLEAR;
298
                                o_wb_ack   <= 1'b0;
299
                                o_wb_stall <= 1'b1;
300
`endif
301
                        end
302
                end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we))
303
                begin
304
`ifdef  READ_ONLY
305
                        o_wb_ack   <= 1'b1;
306
                        o_wb_stall <= 1'b0;
307
`else
308
                        o_wb_stall <= 1'b1;
309
                        case(i_wb_addr[1:0])
310
                        2'b00: begin // Erase command register
311
                                write_protect <= ~i_wb_data[28];
312
                                o_wb_stall <= 1'b0;
313
 
314
                                if((i_wb_data[31])&&(~write_in_progress))
315
                                begin
316
                                        // Command an erase--ack it immediately
317
 
318
                                        o_wb_ack <= 1'b1;
319
                                        o_wb_stall <= 1'b0;
320
 
321
                                        if ((i_wb_data[31])&&(~write_protect))
322
                                        begin
323
                                                spi_wr <= 1'b1;
324
                                                spi_len <= 2'b00;
325
                                                // Send a write enable command
326
                                                spi_in <= { 8'h06, 24'h00 };
327
                                                state <= `WBQSPI_ERASE_CMD;
328
                                                o_wb_stall <= 1'b1;
329
                                        end
330
                                end else if (i_wb_data[31])
331
                                begin
332
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
333
                                        o_wb_ack   <= 1'b1;
334
                                        o_wb_stall <= 1'b1;
335
                                end else
336
                                        o_wb_ack   <= 1'b1;
337
                                        o_wb_stall <= 1'b0;
338
                                end
339
                        2'b01: begin
340
                                // Write the configuration register
341
                                o_wb_ack <= 1'b1;
342
                                o_wb_stall <= 1'b1;
343
 
344
                                // Need to send a write enable command first
345
                                spi_wr <= 1'b1;
346
                                spi_len <= 2'b00; // 8 bits
347
                                // Send a write enable command
348
                                spi_in <= { 8'h06, 24'h00 };
349
                                state <= `WBQSPI_WRITE_CONFIG;
350
                                end
351
                        2'b10: begin
352
                                // Write the status register
353
                                o_wb_ack <= 1'b1; // Ack immediately
354
                                o_wb_stall <= 1'b1; // Stall other cmds
355
                                // Need to send a write enable command first
356
                                spi_wr <= 1'b1;
357
                                spi_len <= 2'b00; // 8 bits
358
                                // Send a write enable command
359
                                spi_in <= { 8'h06, 24'h00 };
360
                                state <= `WBQSPI_WRITE_STATUS;
361
                                end
362
                        2'b11: begin // Write the ID register??? makes no sense
363
                                o_wb_ack <= 1'b1;
364
                                o_wb_stall <= 1'b0;
365
                                end
366
                        endcase
367
`endif
368
                end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we))
369
                begin
370
                        case(i_wb_addr[1:0])
371
                        2'b00: begin // Read local register
372
                                if (write_in_progress) // Read status
373
                                begin// register, is write still in progress?
374
                                        state <= `WBQSPI_READ_STATUS;
375
                                        spi_wr <= 1'b1;
376
                                        spi_len <= 2'b01;// 8 bits out, 8 bits in
377
                                        spi_in <= { 8'h05, 24'h00};
378
 
379
                                        o_wb_ack <= 1'b0;
380
                                        o_wb_stall <= 1'b1;
381
                                end else begin // Return w/o talking to device
382
                                        o_wb_ack <= 1'b1;
383
                                        o_wb_stall <= 1'b0;
384
                                        o_wb_data <= { write_in_progress,
385
                                                dirty_sector, spi_busy,
386
                                                ~write_protect,
387
                                                quad_mode_enabled,
388
                                                {(29-ADDRESS_WIDTH){1'b0}},
389
                                                erased_sector, 14'h000 };
390
                                end end
391
                        2'b01: begin // Read configuration register
392
                                state <= `WBQSPI_READ_CONFIG;
393
                                spi_wr <= 1'b1;
394
                                spi_len <= 2'b01;
395
                                spi_in <= { 8'h35, 24'h00};
396
 
397
                                o_wb_ack <= 1'b0;
398
                                o_wb_stall <= 1'b1;
399
                                end
400
                        2'b10: begin // Read status register
401
                                state <= `WBQSPI_READ_STATUS;
402
                                spi_wr <= 1'b1;
403
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
404
                                spi_in <= { 8'h05, 24'h00};
405
 
406
                                o_wb_ack <= 1'b0;
407
                                o_wb_stall <= 1'b1;
408
                                end
409
                        2'b11: begin // Read ID register
410
                                state <= `WBQSPI_READ_ID_CMD;
411
                                spi_wr <= 1'b1;
412
                                spi_len <= 2'b00;
413
                                spi_in <= { 8'h9f, 24'h00};
414
 
415
                                o_wb_ack <= 1'b0;
416
                                o_wb_stall <= 1'b1;
417
                                end
418
                        endcase
419
`ifndef READ_ONLY
420
                end else if ((~i_wb_cyc)&&(write_in_progress))
421
                begin
422
                        state <= `WBQSPI_IDLE_CHECK_WIP;
423
                        spi_wr <= 1'b1;
424
                        spi_len <= 2'b01; // 8 bits out, 8 bits in
425
                        spi_in <= { 8'h05, 24'h00};
426
 
427
                        o_wb_ack <= 1'b0;
428
                        o_wb_stall <= 1'b1;
429
`endif
430
                end
431
        end else if (state == `WBQSPI_RDIDLE)
432
        begin
433
                spi_wr <= 1'b0;
434
                o_wb_stall <= 1'b0;
435
                o_wb_ack <= 1'b0;
436
                spif_cmd   <= i_wb_we;
437
                spif_addr  <= i_wb_addr;
438
                spif_data  <= i_wb_data;
439
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
440
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
441
                spi_hold <= 1'b0;
442
                spi_spd<= 1'b1;
443
                spi_dir <= 1'b0; // Write (for now)
444
                if ((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we))
445
                begin // Continue our read ... send the new address / mode
446
                        o_wb_stall <= 1'b1;
447
                        spi_wr <= 1'b1;
448
                        spi_len <= 2'b10; // Write address, but not mode byte
449
                        spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},
450
                                        i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 };
451
                        state <= `WBQSPI_QRD_DUMMY;
452
                end else if((i_wb_cyc)&&(i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
453
                begin
454
                        // A local read that doesn't touch the device, so leave
455
                        // the device in its current state
456
                        o_wb_stall <= 1'b0;
457
                        o_wb_ack <= 1'b1;
458
                        o_wb_data <= { write_in_progress,
459
                                        dirty_sector, spi_busy,
460
                                        ~write_protect,
461
                                        quad_mode_enabled,
462
                                        {(29-ADDRESS_WIDTH){1'b0}},
463
                                        erased_sector, 14'h000 };
464
                end else if((i_wb_cyc)&&((i_wb_ctrl_stb)||(i_wb_data_stb)))
465
                begin // Need to release the device from quad mode for all else
466
                        o_wb_ack   <= 1'b0;
467
                        o_wb_stall <= 1'b1;
468
                        spi_wr <= 1'b1;
469
                        spi_len <= 2'b11;
470
                        spi_in <= 32'h00;
471
                        state <= `WBQSPI_WBDECODE;
472
                end
473
        end else if (state == `WBQSPI_WBDECODE)
474
        begin
475
                // We were in quad SPI read mode, and had to get out.
476
                // Now we've got a command (not data read) to read and
477
                // execute.  Accomplish what we would've done while in the
478
                // IDLE state here, save only that we don't have to worry
479
                // about data reads, and we need to operate on a stored
480
                // version of the bus command
481
                o_wb_stall <= 1'b1;
482
                o_wb_ack <= 1'b0;
483
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
484
                spi_hold <= 1'b0;
485
                spi_spd <= 1'b0;
486
                spi_dir <= 1'b0;
487
                spif_req<= (spif_req) && (i_wb_cyc);
488
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...
489
                begin
490
                        // Data register access
491
                        if (~spif_ctrl)
492
                        begin
493
                                if (spif_cmd) // Request to write a page
494
                                begin
495
`ifdef  READ_ONLY
496
                                        o_wb_ack <= spif_req;
497
                                        o_wb_stall <= 1'b0;
498
                                        state <= `WBQSPI_IDLE;
499
`else
500
                                        if((~write_protect)&&(~write_in_progress))
501
                                        begin // 00
502
                                                spi_wr <= 1'b1;
503
                                                spi_len <= 2'b00; // 8 bits
504
                                                // Send a write enable command
505
                                                spi_in <= { 8'h06, 24'h00 };
506
                                                state <= `WBQSPI_WEN;
507
 
508
                                                o_wb_ack <= 1'b0;
509
                                                o_wb_stall <= 1'b1;
510
                                        end else if (write_protect)
511
                                        begin // whether or not write-in_progress ...
512
                                                // Do nothing on a write protect
513
                                                // violation
514
                                                //
515
                                                o_wb_ack <= spif_req;
516
                                                o_wb_stall <= 1'b0;
517
                                                state <= `WBQSPI_IDLE;
518
                                        end else begin // write is in progress, wait
519
                                                // for it to complete
520
                                                state <= `WBQSPI_WAIT_WIP_CLEAR;
521
                                                o_wb_ack <= 1'b0;
522
                                                o_wb_stall <= 1'b1;
523
                                        end
524
                                // end else if (~write_in_progress) // always true
525
                                // but ... we wouldn't get here on a normal read access
526
`endif
527
                                end else begin
528
                                        // Something's wrong, we should never
529
                                        //   get here
530
                                        // Attempt to go to idle to recover
531
                                        state <= `WBQSPI_IDLE;
532
                                end
533
                        end else if ((spif_ctrl)&&(spif_cmd))
534
                        begin
535
`ifdef  READ_ONLY
536
                                o_wb_ack   <= spif_req;
537
                                o_wb_stall <= 1'b0;
538
                                state <= `WBQSPI_IDLE;
539
`else
540
                                o_wb_stall <= 1'b1;
541
                                case(spif_addr[1:0])
542
                                2'b00: begin // Erase command register
543
                                        o_wb_ack   <= spif_req;
544
                                        o_wb_stall <= 1'b0;
545
                                        state <= `WBQSPI_IDLE;
546
                                        write_protect <= ~spif_data[28];
547
                                        // Are we commanding an erase?
548
                                        // We're in read mode, writes cannot
549
                                        // be in progress, so ...
550
                                        if (spif_data[31]) // Command an erase
551
                                        begin
552
                                                // Since we're not going back
553
                                                // to IDLE, we must stall the
554
                                                // bus here
555
                                                o_wb_stall <= 1'b1;
556
                                                spi_wr <= 1'b1;
557
                                                spi_len <= 2'b00;
558
                                                // Send a write enable command
559
                                                spi_in <= { 8'h06, 24'h00 };
560
                                                state <= `WBQSPI_ERASE_CMD;
561
                                        end end
562
                                2'b01: begin
563
                                        // Write the configuration register
564
                                        o_wb_ack <= spif_req;
565
                                        o_wb_stall <= 1'b1;
566
 
567
                                        // Need to send a write enable command first
568
                                        spi_wr <= 1'b1;
569
                                        spi_len <= 2'b00; // 8 bits
570
                                        // Send a write enable command
571
                                        spi_in <= { 8'h06, 24'h00 };
572
                                        state <= `WBQSPI_WRITE_CONFIG;
573
                                        end
574
                                2'b10: begin
575
                                        // Write the status register
576
                                        o_wb_ack <= spif_req; // Ack immediately
577
                                        o_wb_stall <= 1'b1; // Stall other cmds
578
                                        // Need to send a write enable command first
579
                                        spi_wr <= 1'b1;
580
                                        spi_len <= 2'b00; // 8 bits
581
                                        // Send a write enable command
582
                                        spi_in <= { 8'h06, 24'h00 };
583
                                        state <= `WBQSPI_WRITE_STATUS;
584
                                        end
585
                                2'b11: begin // Write the ID register??? makes no sense
586
                                        o_wb_ack <= spif_req;
587
                                        o_wb_stall <= 1'b0;
588
                                        state <= `WBQSPI_IDLE;
589
                                        end
590
                                endcase
591
`endif
592
                        end else begin // on (~spif_we)
593
                                case(spif_addr[1:0])
594
                                2'b00: begin // Read local register
595
                                        // Nonsense case--would've done this
596
                                        // already
597
                                        state <= `WBQSPI_IDLE;
598
                                        o_wb_ack <= spif_req;
599
                                        o_wb_stall <= 1'b0;
600
                                        end
601
                                2'b01: begin // Read configuration register
602
                                        state <= `WBQSPI_READ_CONFIG;
603
                                        spi_wr <= 1'b1;
604
                                        spi_len <= 2'b01;
605
                                        spi_in <= { 8'h35, 24'h00};
606
 
607
                                        o_wb_ack <= 1'b0;
608
                                        o_wb_stall <= 1'b1;
609
                                        end
610
                                2'b10: begin // Read status register
611
                                        state <= `WBQSPI_READ_STATUS;
612
                                        spi_wr <= 1'b1;
613
                                        spi_len <= 2'b01; // 8 bits out, 8 bits in
614
                                        spi_in <= { 8'h05, 24'h00};
615
 
616
                                        o_wb_ack <= 1'b0;
617
                                        o_wb_stall <= 1'b1;
618
                                        end
619
                                2'b11: begin // Read ID register
620
                                        state <= `WBQSPI_READ_ID_CMD;
621
                                        spi_wr <= 1'b1;
622
                                        spi_len <= 2'b00;
623
                                        spi_in <= { 8'h9f, 24'h00};
624
 
625
                                        o_wb_ack <= 1'b0;
626
                                        o_wb_stall <= 1'b1;
627
                                        end
628
                                endcase
629
                        end
630
                end
631
//
632
//
633
//      READ DATA section: for both data and commands
634
//
635
        end else if (state == `WBQSPI_RD_DUMMY)
636
        begin
637
                o_wb_ack   <= 1'b0;
638
                o_wb_stall <= 1'b1;
639
 
640
                spi_wr <= 1'b1; // Non-stop
641
                // Need to read one byte of dummy data,
642
                // just to consume 8 clocks
643
                spi_in <= { 8'h00, 24'h00 };
644
                spi_len <= 2'b00; // Read 8 bits
645
                spi_spd <= 1'b0;
646
                spi_hold <= 1'b0;
647
                spif_req<= (spif_req) && (i_wb_cyc);
648
 
649
                if ((~spi_busy)&&(~o_qspi_cs_n))
650
                        // Our command was accepted
651
                        state <= `WBQSPI_READ_CMD;
652
        end else if (state == `WBQSPI_QRD_ADDRESS)
653
        begin
654
                // We come in here immediately upon issuing a QRD read
655
                // command (8-bits), but we have to pause to give the
656
                // address (24-bits) and mode (8-bits) in quad speed.
657
                o_wb_ack   <= 1'b0;
658
                o_wb_stall <= 1'b1;
659
 
660
                spi_wr <= 1'b1; // Non-stop
661
                spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},
662
                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 };
663
                spi_len <= 2'b10; // Write address, not mode byte
664
                spi_spd <= 1'b1;
665
                spi_dir <= 1'b0; // Still writing
666
                spi_hold <= 1'b0;
667
                spif_req<= (spif_req) && (i_wb_cyc);
668
 
669
                if ((~spi_busy)&&(spi_spd))
670
                        // Our command was accepted
671
                        state <= `WBQSPI_QRD_DUMMY;
672
        end else if (state == `WBQSPI_QRD_DUMMY)
673
        begin
674
                o_wb_ack   <= 1'b0;
675
                o_wb_stall <= 1'b1;
676
 
677
                spi_wr <= 1'b1; // Non-stop
678
                spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
679
                spi_len <= 2'b10; // Write 8 bits
680
                spi_spd <= 1'b1;
681
                spi_dir <= 1'b0; // Still writing
682
                spi_hold <= 1'b0;
683
                spif_req<= (spif_req) && (i_wb_cyc);
684
 
685
                if ((~spi_busy)&&(spi_in[31:28] == 4'ha))
686
                        // Our command was accepted
687
                        state <= `WBQSPI_READ_CMD;
688
        end else if (state == `WBQSPI_READ_CMD)
689
        begin // Issue our first command to read 32 bits.
690
                o_wb_ack   <= 1'b0;
691
                o_wb_stall <= 1'b1;
692
 
693
                spi_wr <= 1'b1;
694
                spi_in <= { 8'hff, 24'h00 }; // Empty
695
                spi_len <= 2'b11; // Read 32 bits
696
                spi_dir <= 1'b1; // Now reading
697
                spi_hold <= 1'b0;
698
                spif_req<= (spif_req) && (i_wb_cyc);
699
                if ((spi_valid)&&(spi_len == 2'b11))
700
                        state <= `WBQSPI_READ_DATA;
701
        end else if (state == `WBQSPI_READ_DATA)
702
        begin
703
                // Pipelined read support
704
                spi_wr <=((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
705
                spi_in <= 32'h00;
706
                spi_len <= 2'b11;
707
                // Don't adjust the speed here, it was set in the setup
708
                spi_dir <= 1'b1;        // Now we get to read
709
                // Don't let the device go to idle until the bus cycle ends.
710
                //      This actually prevents a *really* nasty race condition,
711
                //      where the strobe comes in after the lower level device
712
                //      has decided to stop waiting.  The write is then issued,
713
                //      but no one is listening.  By leaving the device open,
714
                //      the device is kept in a state where a valid strobe
715
                //      here will be useful.  Of course, we don't accept
716
                //      all commands, just reads.  Further, the strobe needs
717
                //      to be high for two clocks cycles without changing
718
                //      anything on the bus--one for us to notice it and pull
719
                //      our head out of the sand, and a second for whoever
720
                //      owns the bus to realize their command went through.
721
                spi_hold <= 1'b1;
722
                spif_req<= (spif_req) && (i_wb_cyc);
723
                if ((spi_valid)&&(~spi_in[31]))
724
                begin // Single pulse acknowledge and write data out
725
                        o_wb_ack <= spif_req;
726
                        o_wb_stall <= (~spi_wr);
727
                        // adjust endian-ness to match the PC
728
                        o_wb_data <= { spi_out[7:0], spi_out[15:8],
729
                                spi_out[23:16], spi_out[31:24] };
730
                        state <= (spi_wr)?`WBQSPI_READ_DATA
731
                                : ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
732
                        spif_req <= spi_wr;
733
                        spi_hold <= (~spi_wr);
734
                        if (spi_wr)
735
                                spif_addr <= i_wb_addr;
736
                end else if (~i_wb_cyc)
737
                begin // FAIL SAFE: If the bus cycle ends, forget why we're
738
                        // here, just go back to idle
739
                        state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
740
                        spi_hold <= 1'b0;
741
                        o_wb_ack <= 1'b0;
742
                        o_wb_stall <= 1'b1;
743
                end else begin
744
                        o_wb_ack <= 1'b0;
745
                        o_wb_stall <= 1'b1;
746
                end
747
        end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
748
        begin // Wait 'til idle, but then go to fast read idle instead of full
749
                spi_wr     <= 1'b0;     // idle
750
                spi_hold   <= 1'b0;
751
                o_wb_stall <= 1'b1;
752
                o_wb_ack   <= 1'b0;
753
                spif_req   <= 1'b0;
754
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
755
                begin // clearing of the SPI port before moving on
756
                        state <= `WBQSPI_RDIDLE;
757
                        o_wb_stall <= 1'b0;
758
                        o_wb_ack   <= 1'b0;// Shouldn't be acking anything here
759
                end
760
        end else if (state == `WBQSPI_READ_ID_CMD)
761
        begin // We came into here immediately after issuing a 0x9f command
762
                // Now we need to read 32 bits of data.  Result should be
763
                // 0x0102154d (8'h manufacture ID, 16'h device ID, followed
764
                // by the number of extended bytes available 8'h4d).
765
                o_wb_ack <= 1'b0;
766
                o_wb_stall<= 1'b1;
767
 
768
                spi_wr <= 1'b1; // No data to send, but need four bytes, since
769
                spi_len <= 2'b11; // 32 bits of data are ... useful
770
                spi_in <= 32'h00; // Irrelevant
771
                spi_spd <= 1'b0; // Slow speed
772
                spi_dir <= 1'b1; // Reading
773
                spi_hold <= 1'b0;
774
                spif_req <= (spif_req) && (i_wb_cyc);
775
                if ((~spi_busy)&&(~o_qspi_cs_n)&&(spi_len == 2'b11))
776
                        // Our command was accepted, now go read the result
777
                        state <= `WBQSPI_READ_ID;
778
        end else if (state == `WBQSPI_READ_ID)
779
        begin
780
                o_wb_ack <= 1'b0; // Assuming we're still waiting
781
                o_wb_stall <= 1'b1;
782
 
783
                spi_wr <= 1'b0; // No more writes, we've already written the cmd
784
                spi_hold <= 1'b0;
785
                spif_req <= (spif_req) && (i_wb_cyc);
786
 
787
                // Here, we just wait until the result comes back
788
                // The problem is, the result may be the previous result.
789
                // So we use spi_len as an indicator
790
                spi_len <= 2'b00;
791
                if((spi_valid)&&(spi_len==2'b00))
792
                begin // Put the results out as soon as possible
793
                        o_wb_data <= spi_out[31:0];
794
                        o_wb_ack <= spif_req;
795
                        spif_req <= 1'b0;
796
                end else if ((~spi_busy)&&(o_qspi_cs_n))
797
                begin
798
                        state <= `WBQSPI_IDLE;
799
                        o_wb_stall <= 1'b0;
800
                end
801
        end else if (state == `WBQSPI_READ_STATUS)
802
        begin // We enter after the command has been given, for now just
803
                // read and return
804
                spi_wr <= 1'b0;
805
                o_wb_ack <= 1'b0;
806
                spi_hold <= 1'b0;
807
                spif_req <= (spif_req) && (i_wb_cyc);
808
                if (spi_valid)
809
                begin
810
                        o_wb_ack <= spif_req;
811
                        o_wb_stall <= 1'b1;
812
                        spif_req <= 1'b0;
813
                        last_status <= spi_out[7:0];
814
                        write_in_progress <= spi_out[0];
815
                        if (spif_addr[1:0] == 2'b00) // Local read, checking
816
                        begin // status, 'cause we're writing
817
                                o_wb_data <= { spi_out[0],
818
                                        dirty_sector, spi_busy,
819
                                        ~write_protect,
820
                                        quad_mode_enabled,
821
                                        {(29-ADDRESS_WIDTH){1'b0}},
822
                                        erased_sector, 14'h000 };
823
                        end else begin
824
                                o_wb_data <= { 24'h00, spi_out[7:0] };
825
                        end
826
                end
827
 
828
                if ((~spi_busy)&&(~spi_wr))
829
                        state <= `WBQSPI_IDLE;
830
        end else if (state == `WBQSPI_READ_CONFIG)
831
        begin // We enter after the command has been given, for now just
832
                // read and return
833
                spi_wr <= 1'b0;
834
                o_wb_ack <= 1'b0;
835
                o_wb_stall <= 1'b1;
836
                spi_hold <= 1'b0;
837
                spif_req <= (spif_req) && (i_wb_cyc);
838
 
839
                if (spi_valid)
840
                begin
841
                        o_wb_data <= { 24'h00, spi_out[7:0] };
842
                        quad_mode_enabled <= spi_out[1];
843
                end
844
 
845
                if ((~spi_busy)&&(~spi_wr))
846
                begin
847
                        state <= `WBQSPI_IDLE;
848
                        o_wb_ack   <= spif_req;
849
                        o_wb_stall <= 1'b0;
850
                        spif_req <= 1'b0;
851
                end
852
 
853
//
854
//
855
//      Write/erase data section
856
//
857
`ifndef READ_ONLY
858
        end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
859
        begin
860
                o_wb_stall <= 1'b1;
861
                o_wb_ack   <= 1'b0;
862
                spi_wr <= 1'b0;
863
                spif_req<= (spif_req) && (i_wb_cyc);
864
                if (~spi_busy)
865
                begin
866
                        spi_wr   <= 1'b1;
867
                        spi_in   <= { 8'h05, 24'h0000 };
868
                        spi_hold <= 1'b1;
869
                        spi_len  <= 2'b01; // 16 bits write, so we can read 8
870
                        state <= `WBQSPI_CHECK_WIP_CLEAR;
871
                        spi_spd  <= 1'b0; // Slow speed
872
                        spi_dir  <= 1'b0;
873
                end
874
        end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
875
        begin
876
                o_wb_stall <= 1'b1;
877
                o_wb_ack   <= 1'b0;
878
                // Repeat as often as necessary until we are clear
879
                spi_wr <= 1'b1;
880
                spi_in <= 32'h0000; // Values here are actually irrelevant
881
                spi_hold <= 1'b1;
882
                spi_len <= 2'b00; // One byte at a time
883
                spi_spd  <= 1'b0; // Slow speed
884
                spi_dir  <= 1'b0;
885
                spif_req<= (spif_req) && (i_wb_cyc);
886
                if ((spi_valid)&&(~spi_out[0]))
887
                begin
888
                        state <= `WBQSPI_CHECK_WIP_DONE;
889
                        spi_wr   <= 1'b0;
890
                        spi_hold <= 1'b0;
891
                        write_in_progress <= 1'b0;
892
                        last_status <= spi_out[7:0];
893
                end
894
        end else if (state == `WBQSPI_CHECK_WIP_DONE)
895
        begin
896
                o_wb_stall <= 1'b1;
897
                o_wb_ack   <= 1'b0;
898
                // Let's let the SPI port come back to a full idle,
899
                // and the chip select line go low before continuing
900
                spi_wr   <= 1'b0;
901
                spi_len  <= 2'b00;
902
                spi_hold <= 1'b0;
903
                spi_spd  <= 1'b0; // Slow speed
904
                spi_dir  <= 1'b0;
905
                spif_req<= (spif_req) && (i_wb_cyc);
906
                if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
907
                begin
908
                        spi_wr   <= 1'b0;
909
                        spi_hold <= 1'b0;
910
 
911
                        casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
912
                        4'b00??: begin // Read data from ... somewhere
913
                                spi_wr     <= 1'b1;     // Write cmd to device
914
                                if (quad_mode_enabled)
915
                                begin
916
                                        spi_in <= { 8'heb,
917
                                                {(24-ADDRESS_WIDTH){1'b0}},
918
                                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
919
                                        state <= `WBQSPI_QRD_ADDRESS;
920
                                        // spi_len    <= 2'b00; // single byte, cmd only
921
                                end else begin
922
                                        spi_in <= { 8'h0b,
923
                                                {(24-ADDRESS_WIDTH){1'b0}},
924
                                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
925
                                        state <= `WBQSPI_RD_DUMMY;
926
                                        spi_len    <= 2'b11; // Send cmd and addr
927
                                end end
928
                        4'b10??: begin // Write data to ... anywhere
929
                                spi_wr <= 1'b1;
930
                                spi_len <= 2'b00; // 8 bits
931
                                // Send a write enable command
932
                                spi_in <= { 8'h06, 24'h00 };
933
                                state <= `WBQSPI_WEN;
934
                                end
935
                        4'b0110: begin // Read status register
936
                                state <= `WBQSPI_READ_STATUS;
937
                                spi_wr <= 1'b1;
938
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
939
                                spi_in <= { 8'h05, 24'h00};
940
                                end
941
                        4'b0111: begin
942
                                state <= `WBQSPI_READ_ID_CMD;
943
                                spi_wr <= 1'b1;
944
                                spi_len <= 2'b00;
945
                                spi_in <= { 8'h9f, 24'h00};
946
                                end
947
                        default: begin //
948
                                o_wb_stall <= 1'b1;
949
                                o_wb_ack <= spif_req;
950
                                state <= `WBQSPI_WAIT_TIL_IDLE;
951
                                end
952
                        endcase
953
                // spif_cmd   <= i_wb_we;
954
                // spif_addr  <= i_wb_addr;
955
                // spif_data  <= i_wb_data;
956
                // spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
957
                // spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
958
                end
959
        end else if (state == `WBQSPI_WEN)
960
        begin // We came here after issuing a write enable command
961
                spi_wr <= 1'b0;
962
                o_wb_ack <= 1'b0;
963
                o_wb_stall <= 1'b1;
964
                spif_req<= (spif_req) && (i_wb_cyc);
965
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
966
                        state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
967
                        // state <= `WBQSPI_PP;
968
        end else if (state == `WBQSPI_PP)
969
        begin // We come here under a full stop / full port idle mode
970
                // Issue our command immediately
971
                spi_wr <= 1'b1;
972
                spi_in <= { 8'h02,
973
                                {(24-ADDRESS_WIDTH){1'b0}},
974
                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
975
                spi_len <= 2'b11;
976
                spi_hold <= 1'b1;
977
                spi_spd  <= 1'b0;
978
                spi_dir  <= 1'b0; // Writing
979
                spif_req<= (spif_req) && (i_wb_cyc);
980
 
981
                // Once we get busy, move on
982
                if (spi_busy)
983
                        state <= `WBQSPI_WR_DATA;
984
                if (spif_sector == erased_sector)
985
                        dirty_sector <= 1'b1;
986
        end else if (state == `WBQSPI_QPP)
987
        begin // We come here under a full stop / full port idle mode
988
                // Issue our command immediately
989
                spi_wr <= 1'b1;
990
                spi_in <= { 8'h32,
991
                                {(24-ADDRESS_WIDTH){1'b0}},
992
                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
993
                spi_len <= 2'b11;
994
                spi_hold <= 1'b1;
995
                spi_spd  <= 1'b0;
996
                spi_dir  <= 1'b0; // Writing
997
                spif_req<= (spif_req) && (i_wb_cyc);
998
 
999
                // Once we get busy, move on
1000
                if (spi_busy)
1001
                begin
1002
                        // spi_wr is irrelevant here ...
1003
                        // Set the speed value once, but wait til we get busy
1004
                        // to do so.
1005
                        spi_spd <= 1'b1;
1006
                        state <= `WBQSPI_WR_DATA;
1007
                end
1008
                if (spif_sector == erased_sector)
1009
                        dirty_sector <= 1'b1;
1010
        end else if (state == `WBQSPI_WR_DATA)
1011
        begin
1012
                o_wb_stall <= 1'b1;
1013
                o_wb_ack   <= 1'b0;
1014
                spi_wr   <= 1'b1; // write without waiting
1015
                spi_in   <= {
1016
                        spif_data[ 7: 0],
1017
                        spif_data[15: 8],
1018
                        spif_data[23:16],
1019
                        spif_data[31:24] };
1020
                spi_len  <= 2'b11; // Write 4 bytes
1021
                spi_hold <= 1'b1;
1022
                if (~spi_busy)
1023
                begin
1024
                        o_wb_ack <= spif_req; // Ack when command given
1025
                        state <= `WBQSPI_WR_BUS_CYCLE;
1026
                end
1027
                spif_req<= (spif_req) && (i_wb_cyc);
1028
        end else if (state == `WBQSPI_WR_BUS_CYCLE)
1029
        begin
1030
                o_wb_ack <= 1'b0; // Turn off our ack and stall flags
1031
                o_wb_stall <= 1'b1;
1032
                spi_wr <= 1'b0;
1033
                spi_hold <= 1'b1;
1034
                write_in_progress <= 1'b1;
1035
                spif_req<= (spif_req) && (i_wb_cyc);
1036
                if (~i_wb_cyc)
1037
                begin
1038
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1039
                        spi_hold <= 1'b0;
1040
                end else if (spi_wr)
1041
                begin // Give the SPI a chance to get busy on the last write
1042
                        // Do nothing here.
1043
                end else if ((i_wb_data_stb)&&(i_wb_we)
1044
                                &&(i_wb_addr == (spif_addr+1))
1045
                                &&(i_wb_addr[(ADDRESS_WIDTH-3):6]==spif_addr[(ADDRESS_WIDTH-3):6]))
1046
                begin
1047
                        spif_cmd  <= 1'b1;
1048
                        spif_data <= i_wb_data;
1049
                        spif_addr <= i_wb_addr;
1050
                        spif_ctrl  <= 1'b0;
1051
                        spif_req<= 1'b1;
1052
                        // We'll keep the bus stalled on this request
1053
                        // for a while
1054
                        state <= `WBQSPI_WR_DATA;
1055
                        o_wb_ack   <= 1'b0;
1056
                        o_wb_stall <= 1'b0;
1057
                end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
1058
                begin
1059
                        spi_hold <= 1'b0;
1060
                        spi_wr   <= 1'b0;
1061
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1062
                end // Otherwise we stay here
1063
        end else if (state == `WBQSPI_WRITE_CONFIG)
1064
        begin // We enter immediately after commanding a WEN
1065
                o_wb_ack   <= 1'b0;
1066
                o_wb_stall <= 1'b1;
1067
 
1068
                spi_len <= 2'b10;
1069
                spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
1070
                spi_wr <= 1'b0;
1071
                spi_hold <= 1'b0;
1072
                spif_req <= (spif_req) && (i_wb_cyc);
1073
                if ((~spi_busy)&&(~spi_wr))
1074
                begin
1075
                        spi_wr <= 1'b1;
1076
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1077
                        write_in_progress <= 1'b1;
1078
                        quad_mode_enabled <= spif_data[1];
1079
                end
1080
        end else if (state == `WBQSPI_WRITE_STATUS)
1081
        begin // We enter immediately after commanding a WEN
1082
                o_wb_ack   <= 1'b0;
1083
                o_wb_stall <= 1'b1;
1084
 
1085
                spi_len <= 2'b01;
1086
                spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
1087
                // last_status <= i_wb_data[7:0]; // We'll read this in a moment
1088
                spi_wr <= 1'b0;
1089
                spi_hold <= 1'b0;
1090
                spif_req <= (spif_req) && (i_wb_cyc);
1091
                if ((~spi_busy)&&(~spi_wr))
1092
                begin
1093
                        spi_wr <= 1'b1;
1094
                        last_status <= spif_data[7:0];
1095
                        write_in_progress <= 1'b1;
1096
                        if(((last_status[6])||(last_status[5]))
1097
                                &&((~spif_data[6])&&(~spif_data[5])))
1098
                                state <= `WBQSPI_CLEAR_STATUS;
1099
                        else
1100
                                state <= `WBQSPI_WAIT_TIL_IDLE;
1101
                end
1102
        end else if (state == `WBQSPI_ERASE_CMD)
1103
        begin // Know that WIP is clear on entry, WEN has just been commanded
1104
                spi_wr     <= 1'b0;
1105
                o_wb_ack   <= 1'b0;
1106
                o_wb_stall <= 1'b1;
1107
                spi_hold   <= 1'b0;
1108
                spi_spd <= 1'b0;
1109
                spi_dir <= 1'b0;
1110
                spif_req <= (spif_req) && (i_wb_cyc);
1111
 
1112
                // Here's the erase command
1113
                spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
1114
                spi_len <= 2'b11; // 32 bit write
1115
                // together with setting our copy of the WIP bit
1116
                write_in_progress <= 1'b1;
1117
                // keeping track of which sector we just erased
1118
                erased_sector <= spif_data[(ADDRESS_WIDTH-3):14];
1119
                // and marking this erase sector as no longer dirty
1120
                dirty_sector <= 1'b0;
1121
 
1122
                // Wait for a full stop before issuing this command
1123
                if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
1124
                begin // When our command is accepted, move to the next state
1125
                        spi_wr <= 1'b1;
1126
                        state <= `WBQSPI_ERASE_BLOCK;
1127
                end
1128
        end else if (state == `WBQSPI_ERASE_BLOCK)
1129
        begin
1130
                spi_wr     <= 1'b0;
1131
                spi_hold   <= 1'b0;
1132
                o_wb_stall <= 1'b1;
1133
                o_wb_ack   <= 1'b0;
1134
                spif_req <= (spif_req) && (i_wb_cyc);
1135
                // When the port clears, we can head back to idle
1136
                if ((~spi_busy)&&(~spi_wr))
1137
                begin
1138
                        o_wb_ack <= spif_req;
1139
                        state <= `WBQSPI_IDLE;
1140
                end
1141
        end else if (state == `WBQSPI_CLEAR_STATUS)
1142
        begin // Issue a clear status command
1143
                spi_wr <= 1'b1;
1144
                spi_hold <= 1'b0;
1145
                spi_len <= 2'b00; // 8 bit command
1146
                spi_in <= { 8'h30, 24'h00 };
1147
                spi_spd <= 1'b0;
1148
                spi_dir <= 1'b0;
1149
                last_status[6:5] <= 2'b00;
1150
                spif_req <= (spif_req) && (i_wb_cyc);
1151
                if ((spi_wr)&&(~spi_busy))
1152
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1153
        end else if (state == `WBQSPI_IDLE_CHECK_WIP)
1154
        begin // We are now in read status register mode
1155
 
1156
                // No bus commands have (yet) been given
1157
                o_wb_stall <= 1'b1;
1158
                o_wb_ack   <= 1'b0;
1159
                spif_req <= (spif_req) && (i_wb_cyc);
1160
 
1161
                // Stay in this mode unless/until we get a command, or
1162
                //      the write is over
1163
                spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
1164
                                &&(write_in_progress));
1165
                spi_len <= 2'b00; // 8 bit reads
1166
                spi_spd <= 1'b0;  // SPI, not quad
1167
                spi_dir <= 1'b1;  // Read
1168
                if (spi_valid)
1169
                begin
1170
                        write_in_progress <= spi_out[0];
1171
                        if ((~spi_out[0])&&(write_in_progress))
1172
                                o_interrupt <= 1'b1;
1173
                end else
1174
                        o_interrupt <= 1'b0;
1175
 
1176
                if ((~spi_wr)&&(~spi_busy)&&(o_qspi_cs_n))
1177
                begin // We can now go to idle and process a command
1178
                        o_wb_stall <= 1'b0;
1179
                        o_wb_ack   <= 1'b0;
1180
                        state <= `WBQSPI_IDLE;
1181
                end
1182
`endif //       !READ_ONLY
1183
        end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
1184
        begin
1185
                spi_wr     <= 1'b0;
1186
                spi_hold   <= 1'b0;
1187
                o_wb_stall <= 1'b1;
1188
                o_wb_ack   <= 1'b0;
1189
                spif_req   <= 1'b0;
1190
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
1191
                begin // clearing of the SPI port before moving on
1192
                        state <= `WBQSPI_IDLE;
1193
                        o_wb_stall <= 1'b0;
1194
                        o_wb_ack   <= 1'b0; // Shouldn't be acking anything here
1195
                end
1196
        end
1197
        end
1198
 
1199
        // Command and control during the reset sequence
1200 11 dgisselq
        assign  o_qspi_cs_n = (spif_override)?alt_cmd :w_qspi_cs_n;
1201
        assign  o_qspi_sck  = (spif_override)?alt_ctrl:w_qspi_sck;
1202
        assign  o_qspi_mod  = (spif_override)?  2'b01 :w_qspi_mod;
1203
        assign  o_qspi_dat  = (spif_override)?  4'b00 :w_qspi_dat;
1204 2 dgisselq
endmodule

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