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[/] [s6soc/] [trunk/] [rtl/] [wbqspiflashp.v] - Blame information for rev 4

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1 4 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    wbspiflashp.v
4
//
5
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6
//
7
// Purpose:     This is identical to the wbspiflash.v file, save only that this
8
//              provides a writable interface to the flash whereas the other
9
//      is configured to be read only.
10
//
11
// Creator:     Dan Gisselquist
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//              Gisselquist Technology, LLC
13
//
14
///////////////////////////////////////////////////////////////////////////
15
//
16
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
17
//
18
// This program is free software (firmware): you can redistribute it and/or
19
// modify it under the terms of  the GNU General Public License as published
20
// by the Free Software Foundation, either version 3 of the License, or (at
21
// your option) any later version.
22
//
23
// This program is distributed in the hope that it will be useful, but WITHOUT
24
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
25
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
26
// for more details.
27
//
28
// You should have received a copy of the GNU General Public License along
29
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
31
// <http://www.gnu.org/licenses/> for a copy.
32
//
33
// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
35
//
36
//
37
///////////////////////////////////////////////////////////////////////////
38
//
39
`define WBQSPI_RESET            0
40
`define WBQSPI_RESET_QUADMODE   1
41
`define WBQSPI_IDLE             2
42
`define WBQSPI_RDIDLE           3       // Idle, but in fast read mode
43
`define WBQSPI_WBDECODE         4
44
`define WBQSPI_RD_DUMMY         5
45
`define WBQSPI_QRD_ADDRESS      6
46
`define WBQSPI_QRD_DUMMY        7
47
`define WBQSPI_READ_CMD         8
48
`define WBQSPI_READ_DATA        9
49
`define WBQSPI_WAIT_TIL_RDIDLE  10
50
`define WBQSPI_READ_ID_CMD      11
51
`define WBQSPI_READ_ID          12
52
`define WBQSPI_READ_STATUS      13
53
`define WBQSPI_READ_CONFIG      14
54
`define WBQSPI_WAIT_TIL_IDLE    15
55
//
56
//
57
`ifndef READ_ONLY
58
//
59
`define WBQSPI_WAIT_WIP_CLEAR   16
60
`define WBQSPI_CHECK_WIP_CLEAR  17
61
`define WBQSPI_CHECK_WIP_DONE   18
62
`define WBQSPI_WEN              19
63
`define WBQSPI_PP               20      // Program page
64
`define WBQSPI_QPP              21      // Program page, 4 bit mode
65
`define WBQSPI_WR_DATA          22
66
`define WBQSPI_WR_BUS_CYCLE     23
67
`define WBQSPI_WRITE_STATUS     24
68
`define WBQSPI_WRITE_CONFIG     25
69
`define WBQSPI_ERASE_WEN        26
70
`define WBQSPI_ERASE_CMD        27
71
`define WBQSPI_ERASE_BLOCK      28
72
`define WBQSPI_CLEAR_STATUS     29
73
`define WBQSPI_IDLE_CHECK_WIP   30
74
//
75
`endif
76
 
77
module  wbqspiflashp(i_clk_100mhz,
78
                // Internal wishbone connections
79
                i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
80
                i_wb_addr, i_wb_data,
81
                // Wishbone return values
82
                o_wb_ack, o_wb_stall, o_wb_data,
83
                // Quad Spi connections to the external device
84
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
85
                o_interrupt);
86
        parameter       ADDRESS_WIDTH=22;
87
        input                   i_clk_100mhz;
88
        // Wishbone, inputs first
89
        input                   i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
90
        input           [(ADDRESS_WIDTH-3):0]    i_wb_addr;
91
        input           [31:0]   i_wb_data;
92
        // then outputs
93
        output  reg             o_wb_ack;
94
        output  reg             o_wb_stall;
95
        output  reg     [31:0]   o_wb_data;
96
        // Quad SPI control wires
97
        output  wire            o_qspi_sck, o_qspi_cs_n;
98
        output  wire    [1:0]    o_qspi_mod;
99
        output  wire    [3:0]    o_qspi_dat;
100
        input           [3:0]    i_qspi_dat;
101
        // Interrupt line
102
        output  reg             o_interrupt;
103
        // output       wire    [31:0]  o_debug;
104
 
105
        reg             spi_wr, spi_hold, spi_spd, spi_dir;
106
        reg     [31:0]   spi_in;
107
        reg     [1:0]    spi_len;
108
        wire    [31:0]   spi_out;
109
        wire            spi_valid, spi_busy;
110
        wire            w_qspi_sck, w_qspi_cs_n;
111
        wire    [3:0]    w_qspi_dat;
112
        wire    [1:0]    w_qspi_mod;
113
        // wire [22:0]  spi_dbg;
114
        llqspi  lldriver(i_clk_100mhz,
115
                        spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
116
                                spi_out, spi_valid, spi_busy,
117
                        w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
118
                                i_qspi_dat);
119
 
120
        // Erase status tracking
121
        reg             write_in_progress, write_protect;
122
        reg     [(ADDRESS_WIDTH-17):0]   erased_sector;
123
        reg             dirty_sector;
124
        initial begin
125
                write_in_progress = 1'b0;
126
                erased_sector = 0;
127
                dirty_sector  = 1'b1;
128
                write_protect = 1'b1;
129
        end
130
 
131
        reg     [7:0]    last_status;
132
        reg             quad_mode_enabled;
133
        reg             spif_cmd, spif_override;
134
        reg     [(ADDRESS_WIDTH-3):0]    spif_addr;
135
        reg     [31:0]   spif_data;
136
        reg     [5:0]    state;
137
        reg             spif_ctrl, spif_req;
138
        wire    [(ADDRESS_WIDTH-17):0]   spif_sector;
139
        assign  spif_sector = spif_addr[(ADDRESS_WIDTH-3):14];
140
 
141
        // assign       o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
142
 
143
        initial state = `WBQSPI_RESET;
144
        initial o_wb_ack   = 1'b0;
145
        initial o_wb_stall = 1'b1;
146
        initial spi_wr     = 1'b0;
147
        initial spi_len    = 2'b00;
148
        initial quad_mode_enabled = 1'b0;
149
        initial o_interrupt = 1'b0;
150
        always @(posedge i_clk_100mhz)
151
        begin
152
        spif_override <= 1'b0;
153
        if (state == `WBQSPI_RESET)
154
        begin
155
                // From a reset, we should
156
                //      Enable the Quad I/O mode
157
                //      Disable the Write protection bits in the status register
158
                //      Chip should already be up and running, so we can start
159
                //      immediately ....
160
                o_wb_ack <= 1'b0;
161
                o_wb_stall <= 1'b1;
162
                spi_wr   <= 1'b0;
163
                spi_hold <= 1'b0;
164
                spi_spd  <= 1'b0;
165
                spi_dir  <= 1'b0;
166
                last_status <= 8'h00;
167
                state <= `WBQSPI_RESET_QUADMODE;
168
                spif_req <= 1'b0;
169
                spif_override <= 1'b1;
170
                last_status <= 8'hfc; //
171
                        // This guarantees that we aren't starting in quad
172
                        // I/O mode, where the FPGA configuration scripts may
173
                        // have left us.
174
        end else if (state == `WBQSPI_RESET_QUADMODE)
175
        begin
176
                // Okay, so here's the problem: we don't know whether or not
177
                // the Xilinx loader started us up in Quad Read I/O idle mode.
178
                // So, thus we need to 
179
                // Not ready to handle the bus yet, so stall any requests
180
                o_wb_ack   <= 1'b0;
181
                o_wb_stall <= 1'b1;
182
 
183
                // Do something ...
184
                if (last_status == 8'h00)
185
                begin
186
                        spif_override <= 1'b0;
187
                        state <= `WBQSPI_IDLE;
188
                end else begin
189
                        last_status <= last_status - 8'h1;
190
                        spif_override <= 1'b1;
191
                        spif_cmd  <= last_status[3]; // Toggle CS_n
192
                        spif_ctrl <= last_status[0]; // Toggle clock too
193
                end
194
        end else if (state == `WBQSPI_IDLE)
195
        begin
196
                o_interrupt <= 1'b0;
197
                o_wb_stall <= 1'b0;
198
                o_wb_ack <= 1'b0;
199
                spif_cmd   <= i_wb_we;
200
                spif_addr  <= i_wb_addr;
201
                spif_data  <= i_wb_data;
202
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
203
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
204
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
205
                spi_hold <= 1'b0;
206
                spi_spd  <= 1'b0;
207
                spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
208
                // Data register access
209
                if ((i_wb_data_stb)&&(i_wb_cyc))
210
                begin
211
 
212
                        if (i_wb_we) // Request to write a page
213
                        begin
214
`ifdef  READ_ONLY
215
                                o_wb_ack <= 1'b1;
216
                                o_wb_stall <= 1'b0;
217
                        end else
218
`else
219
                                if((~write_protect)&&(~write_in_progress))
220
                                begin // 00
221
                                        spi_wr <= 1'b1;
222
                                        spi_len <= 2'b00; // 8 bits
223
                                        // Send a write enable command
224
                                        spi_in <= { 8'h06, 24'h00 };
225
                                        state <= `WBQSPI_WEN;
226
 
227
                                        o_wb_ack <= 1'b0;
228
                                        o_wb_stall <= 1'b1;
229
                                end else if (write_protect)
230
                                begin // whether or not write-in_progress ...
231
                                        // Do nothing on a write protect
232
                                        // violation
233
                                        //
234
                                        o_wb_ack <= 1'b1;
235
                                        o_wb_stall <= 1'b0;
236
                                end else begin // write is in progress, wait
237
                                        // for it to complete
238
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
239
                                        o_wb_ack <= 1'b0;
240
                                        o_wb_stall <= 1'b1;
241
                                end
242
                        end else if (~write_in_progress)
243
`endif
244
                        begin // Read access, normal mode(s)
245
                                o_wb_ack   <= 1'b0;
246
                                o_wb_stall <= 1'b1;
247
                                spi_wr     <= 1'b1;     // Write cmd to device
248
                                if (quad_mode_enabled)
249
                                begin
250
                                        spi_in <= { 8'heb,
251
                                                {(24-ADDRESS_WIDTH){1'b0}},
252
                                                i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
253
                                        state <= `WBQSPI_QRD_ADDRESS;
254
                                        spi_len    <= 2'b00; // single byte, cmd only
255
                                end else begin
256
                                        spi_in <= { 8'h0b,
257
                                                {(24-ADDRESS_WIDTH){1'b0}},
258
                                                i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
259
                                        state <= `WBQSPI_RD_DUMMY;
260
                                        spi_len    <= 2'b11; // cmd+addr,32bits
261
                                end
262
`ifndef READ_ONLY
263
                        end else begin
264
                                // A write is in progress ... need to stall
265
                                // the bus until the write is complete.
266
                                state <= `WBQSPI_WAIT_WIP_CLEAR;
267
                                o_wb_ack   <= 1'b0;
268
                                o_wb_stall <= 1'b1;
269
`endif
270
                        end
271
                end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we))
272
                begin
273
`ifdef  READ_ONLY
274
                        o_wb_ack   <= 1'b1;
275
                        o_wb_stall <= 1'b0;
276
`else
277
                        o_wb_stall <= 1'b1;
278
                        case(i_wb_addr[1:0])
279
                        2'b00: begin // Erase command register
280
                                write_protect <= ~i_wb_data[28];
281
                                o_wb_stall <= 1'b0;
282
 
283
                                if((i_wb_data[31])&&(~write_in_progress))
284
                                begin
285
                                        // Command an erase--ack it immediately
286
 
287
                                        o_wb_ack <= 1'b1;
288
                                        o_wb_stall <= 1'b0;
289
 
290
                                        if ((i_wb_data[31])&&(~write_protect))
291
                                        begin
292
                                                spi_wr <= 1'b1;
293
                                                spi_len <= 2'b00;
294
                                                // Send a write enable command
295
                                                spi_in <= { 8'h06, 24'h00 };
296
                                                state <= `WBQSPI_ERASE_CMD;
297
                                                o_wb_stall <= 1'b1;
298
                                        end
299
                                end else if (i_wb_data[31])
300
                                begin
301
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
302
                                        o_wb_ack   <= 1'b1;
303
                                        o_wb_stall <= 1'b1;
304
                                end else
305
                                        o_wb_ack   <= 1'b1;
306
                                        o_wb_stall <= 1'b0;
307
                                end
308
                        2'b01: begin
309
                                // Write the configuration register
310
                                o_wb_ack <= 1'b1;
311
                                o_wb_stall <= 1'b1;
312
 
313
                                // Need to send a write enable command first
314
                                spi_wr <= 1'b1;
315
                                spi_len <= 2'b00; // 8 bits
316
                                // Send a write enable command
317
                                spi_in <= { 8'h06, 24'h00 };
318
                                state <= `WBQSPI_WRITE_CONFIG;
319
                                end
320
                        2'b10: begin
321
                                // Write the status register
322
                                o_wb_ack <= 1'b1; // Ack immediately
323
                                o_wb_stall <= 1'b1; // Stall other cmds
324
                                // Need to send a write enable command first
325
                                spi_wr <= 1'b1;
326
                                spi_len <= 2'b00; // 8 bits
327
                                // Send a write enable command
328
                                spi_in <= { 8'h06, 24'h00 };
329
                                state <= `WBQSPI_WRITE_STATUS;
330
                                end
331
                        2'b11: begin // Write the ID register??? makes no sense
332
                                o_wb_ack <= 1'b1;
333
                                o_wb_stall <= 1'b0;
334
                                end
335
                        endcase
336
`endif
337
                end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we))
338
                begin
339
                        case(i_wb_addr[1:0])
340
                        2'b00: begin // Read local register
341
                                if (write_in_progress) // Read status
342
                                begin// register, is write still in progress?
343
                                        state <= `WBQSPI_READ_STATUS;
344
                                        spi_wr <= 1'b1;
345
                                        spi_len <= 2'b01;// 8 bits out, 8 bits in
346
                                        spi_in <= { 8'h05, 24'h00};
347
 
348
                                        o_wb_ack <= 1'b0;
349
                                        o_wb_stall <= 1'b1;
350
                                end else begin // Return w/o talking to device
351
                                        o_wb_ack <= 1'b1;
352
                                        o_wb_stall <= 1'b0;
353
                                        o_wb_data <= { write_in_progress,
354
                                                dirty_sector, spi_busy,
355
                                                ~write_protect,
356
                                                quad_mode_enabled,
357
                                                {(29-ADDRESS_WIDTH){1'b0}},
358
                                                erased_sector, 14'h000 };
359
                                end end
360
                        2'b01: begin // Read configuration register
361
                                state <= `WBQSPI_READ_CONFIG;
362
                                spi_wr <= 1'b1;
363
                                spi_len <= 2'b01;
364
                                spi_in <= { 8'h35, 24'h00};
365
 
366
                                o_wb_ack <= 1'b0;
367
                                o_wb_stall <= 1'b1;
368
                                end
369
                        2'b10: begin // Read status register
370
                                state <= `WBQSPI_READ_STATUS;
371
                                spi_wr <= 1'b1;
372
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
373
                                spi_in <= { 8'h05, 24'h00};
374
 
375
                                o_wb_ack <= 1'b0;
376
                                o_wb_stall <= 1'b1;
377
                                end
378
                        2'b11: begin // Read ID register
379
                                state <= `WBQSPI_READ_ID_CMD;
380
                                spi_wr <= 1'b1;
381
                                spi_len <= 2'b00;
382
                                spi_in <= { 8'h9f, 24'h00};
383
 
384
                                o_wb_ack <= 1'b0;
385
                                o_wb_stall <= 1'b1;
386
                                end
387
                        endcase
388
`ifndef READ_ONLY
389
                end else if ((~i_wb_cyc)&&(write_in_progress))
390
                begin
391
                        state <= `WBQSPI_IDLE_CHECK_WIP;
392
                        spi_wr <= 1'b1;
393
                        spi_len <= 2'b01; // 8 bits out, 8 bits in
394
                        spi_in <= { 8'h05, 24'h00};
395
 
396
                        o_wb_ack <= 1'b0;
397
                        o_wb_stall <= 1'b1;
398
`endif
399
                end
400
        end else if (state == `WBQSPI_RDIDLE)
401
        begin
402
                spi_wr <= 1'b0;
403
                o_wb_stall <= 1'b0;
404
                o_wb_ack <= 1'b0;
405
                spif_cmd   <= i_wb_we;
406
                spif_addr  <= i_wb_addr;
407
                spif_data  <= i_wb_data;
408
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
409
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
410
                spi_hold <= 1'b0;
411
                spi_spd<= 1'b1;
412
                spi_dir <= 1'b0; // Write (for now)
413
                if ((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we))
414
                begin // Continue our read ... send the new address / mode
415
                        o_wb_stall <= 1'b1;
416
                        spi_wr <= 1'b1;
417
                        spi_len <= 2'b10; // Write address, but not mode byte
418
                        spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},
419
                                        i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 };
420
                        state <= `WBQSPI_QRD_DUMMY;
421
                end else if((i_wb_cyc)&&(i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
422
                begin
423
                        // A local read that doesn't touch the device, so leave
424
                        // the device in its current state
425
                        o_wb_stall <= 1'b0;
426
                        o_wb_ack <= 1'b1;
427
                        o_wb_data <= { write_in_progress,
428
                                        dirty_sector, spi_busy,
429
                                        ~write_protect,
430
                                        quad_mode_enabled,
431
                                        {(29-ADDRESS_WIDTH){1'b0}},
432
                                        erased_sector, 14'h000 };
433
                end else if((i_wb_cyc)&&((i_wb_ctrl_stb)||(i_wb_data_stb)))
434
                begin // Need to release the device from quad mode for all else
435
                        o_wb_ack   <= 1'b0;
436
                        o_wb_stall <= 1'b1;
437
                        spi_wr <= 1'b1;
438
                        spi_len <= 2'b11;
439
                        spi_in <= 32'h00;
440
                        state <= `WBQSPI_WBDECODE;
441
                end
442
        end else if (state == `WBQSPI_WBDECODE)
443
        begin
444
                // We were in quad SPI read mode, and had to get out.
445
                // Now we've got a command (not data read) to read and
446
                // execute.  Accomplish what we would've done while in the
447
                // IDLE state here, save only that we don't have to worry
448
                // about data reads, and we need to operate on a stored
449
                // version of the bus command
450
                o_wb_stall <= 1'b1;
451
                o_wb_ack <= 1'b0;
452
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
453
                spi_hold <= 1'b0;
454
                spi_spd <= 1'b0;
455
                spi_dir <= 1'b0;
456
                spif_req<= (spif_req) && (i_wb_cyc);
457
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...
458
                begin
459
                        // Data register access
460
                        if (~spif_ctrl)
461
                        begin
462
                                if (spif_cmd) // Request to write a page
463
                                begin
464
`ifdef  READ_ONLY
465
                                        o_wb_ack <= spif_req;
466
                                        o_wb_stall <= 1'b0;
467
                                        state <= `WBQSPI_IDLE;
468
`else
469
                                        if((~write_protect)&&(~write_in_progress))
470
                                        begin // 00
471
                                                spi_wr <= 1'b1;
472
                                                spi_len <= 2'b00; // 8 bits
473
                                                // Send a write enable command
474
                                                spi_in <= { 8'h06, 24'h00 };
475
                                                state <= `WBQSPI_WEN;
476
 
477
                                                o_wb_ack <= 1'b0;
478
                                                o_wb_stall <= 1'b1;
479
                                        end else if (write_protect)
480
                                        begin // whether or not write-in_progress ...
481
                                                // Do nothing on a write protect
482
                                                // violation
483
                                                //
484
                                                o_wb_ack <= spif_req;
485
                                                o_wb_stall <= 1'b0;
486
                                                state <= `WBQSPI_IDLE;
487
                                        end else begin // write is in progress, wait
488
                                                // for it to complete
489
                                                state <= `WBQSPI_WAIT_WIP_CLEAR;
490
                                                o_wb_ack <= 1'b0;
491
                                                o_wb_stall <= 1'b1;
492
                                        end
493
                                // end else if (~write_in_progress) // always true
494
                                // but ... we wouldn't get here on a normal read access
495
`endif
496
                                end else begin
497
                                        // Something's wrong, we should never
498
                                        //   get here
499
                                        // Attempt to go to idle to recover
500
                                        state <= `WBQSPI_IDLE;
501
                                end
502
                        end else if ((spif_ctrl)&&(spif_cmd))
503
                        begin
504
`ifdef  READ_ONLY
505
                                o_wb_ack   <= spif_req;
506
                                o_wb_stall <= 1'b0;
507
                                state <= `WBQSPI_IDLE;
508
`else
509
                                o_wb_stall <= 1'b1;
510
                                case(spif_addr[1:0])
511
                                2'b00: begin // Erase command register
512
                                        o_wb_ack   <= spif_req;
513
                                        o_wb_stall <= 1'b0;
514
                                        state <= `WBQSPI_IDLE;
515
                                        write_protect <= ~spif_data[28];
516
                                        // Are we commanding an erase?
517
                                        // We're in read mode, writes cannot
518
                                        // be in progress, so ...
519
                                        if (spif_data[31]) // Command an erase
520
                                        begin
521
                                                // Since we're not going back
522
                                                // to IDLE, we must stall the
523
                                                // bus here
524
                                                o_wb_stall <= 1'b1;
525
                                                spi_wr <= 1'b1;
526
                                                spi_len <= 2'b00;
527
                                                // Send a write enable command
528
                                                spi_in <= { 8'h06, 24'h00 };
529
                                                state <= `WBQSPI_ERASE_CMD;
530
                                        end end
531
                                2'b01: begin
532
                                        // Write the configuration register
533
                                        o_wb_ack <= spif_req;
534
                                        o_wb_stall <= 1'b1;
535
 
536
                                        // Need to send a write enable command first
537
                                        spi_wr <= 1'b1;
538
                                        spi_len <= 2'b00; // 8 bits
539
                                        // Send a write enable command
540
                                        spi_in <= { 8'h06, 24'h00 };
541
                                        state <= `WBQSPI_WRITE_CONFIG;
542
                                        end
543
                                2'b10: begin
544
                                        // Write the status register
545
                                        o_wb_ack <= spif_req; // Ack immediately
546
                                        o_wb_stall <= 1'b1; // Stall other cmds
547
                                        // Need to send a write enable command first
548
                                        spi_wr <= 1'b1;
549
                                        spi_len <= 2'b00; // 8 bits
550
                                        // Send a write enable command
551
                                        spi_in <= { 8'h06, 24'h00 };
552
                                        state <= `WBQSPI_WRITE_STATUS;
553
                                        end
554
                                2'b11: begin // Write the ID register??? makes no sense
555
                                        o_wb_ack <= spif_req;
556
                                        o_wb_stall <= 1'b0;
557
                                        state <= `WBQSPI_IDLE;
558
                                        end
559
                                endcase
560
`endif
561
                        end else begin // on (~spif_we)
562
                                case(spif_addr[1:0])
563
                                2'b00: begin // Read local register
564
                                        // Nonsense case--would've done this
565
                                        // already
566
                                        state <= `WBQSPI_IDLE;
567
                                        o_wb_ack <= spif_req;
568
                                        o_wb_stall <= 1'b0;
569
                                        end
570
                                2'b01: begin // Read configuration register
571
                                        state <= `WBQSPI_READ_CONFIG;
572
                                        spi_wr <= 1'b1;
573
                                        spi_len <= 2'b01;
574
                                        spi_in <= { 8'h35, 24'h00};
575
 
576
                                        o_wb_ack <= 1'b0;
577
                                        o_wb_stall <= 1'b1;
578
                                        end
579
                                2'b10: begin // Read status register
580
                                        state <= `WBQSPI_READ_STATUS;
581
                                        spi_wr <= 1'b1;
582
                                        spi_len <= 2'b01; // 8 bits out, 8 bits in
583
                                        spi_in <= { 8'h05, 24'h00};
584
 
585
                                        o_wb_ack <= 1'b0;
586
                                        o_wb_stall <= 1'b1;
587
                                        end
588
                                2'b11: begin // Read ID register
589
                                        state <= `WBQSPI_READ_ID_CMD;
590
                                        spi_wr <= 1'b1;
591
                                        spi_len <= 2'b00;
592
                                        spi_in <= { 8'h9f, 24'h00};
593
 
594
                                        o_wb_ack <= 1'b0;
595
                                        o_wb_stall <= 1'b1;
596
                                        end
597
                                endcase
598
                        end
599
                end
600
//
601
//
602
//      READ DATA section: for both data and commands
603
//
604
        end else if (state == `WBQSPI_RD_DUMMY)
605
        begin
606
                o_wb_ack   <= 1'b0;
607
                o_wb_stall <= 1'b1;
608
 
609
                spi_wr <= 1'b1; // Non-stop
610
                // Need to read one byte of dummy data,
611
                // just to consume 8 clocks
612
                spi_in <= { 8'h00, 24'h00 };
613
                spi_len <= 2'b00; // Read 8 bits
614
                spi_spd <= 1'b0;
615
                spi_hold <= 1'b0;
616
                spif_req<= (spif_req) && (i_wb_cyc);
617
 
618
                if ((~spi_busy)&&(~o_qspi_cs_n))
619
                        // Our command was accepted
620
                        state <= `WBQSPI_READ_CMD;
621
        end else if (state == `WBQSPI_QRD_ADDRESS)
622
        begin
623
                // We come in here immediately upon issuing a QRD read
624
                // command (8-bits), but we have to pause to give the
625
                // address (24-bits) and mode (8-bits) in quad speed.
626
                o_wb_ack   <= 1'b0;
627
                o_wb_stall <= 1'b1;
628
 
629
                spi_wr <= 1'b1; // Non-stop
630
                spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},
631
                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 };
632
                spi_len <= 2'b10; // Write address, not mode byte
633
                spi_spd <= 1'b1;
634
                spi_dir <= 1'b0; // Still writing
635
                spi_hold <= 1'b0;
636
                spif_req<= (spif_req) && (i_wb_cyc);
637
 
638
                if ((~spi_busy)&&(spi_spd))
639
                        // Our command was accepted
640
                        state <= `WBQSPI_QRD_DUMMY;
641
        end else if (state == `WBQSPI_QRD_DUMMY)
642
        begin
643
                o_wb_ack   <= 1'b0;
644
                o_wb_stall <= 1'b1;
645
 
646
                spi_wr <= 1'b1; // Non-stop
647
                spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
648
                spi_len <= 2'b10; // Write 8 bits
649
                spi_spd <= 1'b1;
650
                spi_dir <= 1'b0; // Still writing
651
                spi_hold <= 1'b0;
652
                spif_req<= (spif_req) && (i_wb_cyc);
653
 
654
                if ((~spi_busy)&&(spi_in[31:28] == 4'ha))
655
                        // Our command was accepted
656
                        state <= `WBQSPI_READ_CMD;
657
        end else if (state == `WBQSPI_READ_CMD)
658
        begin // Issue our first command to read 32 bits.
659
                o_wb_ack   <= 1'b0;
660
                o_wb_stall <= 1'b1;
661
 
662
                spi_wr <= 1'b1;
663
                spi_in <= { 8'hff, 24'h00 }; // Empty
664
                spi_len <= 2'b11; // Read 32 bits
665
                spi_dir <= 1'b1; // Now reading
666
                spi_hold <= 1'b0;
667
                spif_req<= (spif_req) && (i_wb_cyc);
668
                if ((spi_valid)&&(spi_len == 2'b11))
669
                        state <= `WBQSPI_READ_DATA;
670
        end else if (state == `WBQSPI_READ_DATA)
671
        begin
672
                // Pipelined read support
673
                spi_wr <=((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
674
                spi_in <= 32'h00;
675
                spi_len <= 2'b11;
676
                // Don't adjust the speed here, it was set in the setup
677
                spi_dir <= 1'b1;        // Now we get to read
678
                // Don't let the device go to idle until the bus cycle ends.
679
                //      This actually prevents a *really* nasty race condition,
680
                //      where the strobe comes in after the lower level device
681
                //      has decided to stop waiting.  The write is then issued,
682
                //      but no one is listening.  By leaving the device open,
683
                //      the device is kept in a state where a valid strobe
684
                //      here will be useful.  Of course, we don't accept
685
                //      all commands, just reads.  Further, the strobe needs
686
                //      to be high for two clocks cycles without changing
687
                //      anything on the bus--one for us to notice it and pull
688
                //      our head out of the sand, and a second for whoever
689
                //      owns the bus to realize their command went through.
690
                spi_hold <= 1'b1;
691
                spif_req<= (spif_req) && (i_wb_cyc);
692
                if ((spi_valid)&&(~spi_in[31]))
693
                begin // Single pulse acknowledge and write data out
694
                        o_wb_ack <= spif_req;
695
                        o_wb_stall <= (~spi_wr);
696
                        // adjust endian-ness to match the PC
697
                        o_wb_data <= { spi_out[7:0], spi_out[15:8],
698
                                spi_out[23:16], spi_out[31:24] };
699
                        state <= (spi_wr)?`WBQSPI_READ_DATA
700
                                : ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
701
                        spif_req <= spi_wr;
702
                        spi_hold <= (~spi_wr);
703
                        if (spi_wr)
704
                                spif_addr <= i_wb_addr;
705
                end else if (~i_wb_cyc)
706
                begin // FAIL SAFE: If the bus cycle ends, forget why we're
707
                        // here, just go back to idle
708
                        state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
709
                        spi_hold <= 1'b0;
710
                        o_wb_ack <= 1'b0;
711
                        o_wb_stall <= 1'b1;
712
                end else begin
713
                        o_wb_ack <= 1'b0;
714
                        o_wb_stall <= 1'b1;
715
                end
716
        end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
717
        begin // Wait 'til idle, but then go to fast read idle instead of full
718
                spi_wr     <= 1'b0;     // idle
719
                spi_hold   <= 1'b0;
720
                o_wb_stall <= 1'b1;
721
                o_wb_ack   <= 1'b0;
722
                spif_req   <= 1'b0;
723
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
724
                begin // clearing of the SPI port before moving on
725
                        state <= `WBQSPI_RDIDLE;
726
                        o_wb_stall <= 1'b0;
727
                        o_wb_ack   <= 1'b0;// Shouldn't be acking anything here
728
                end
729
        end else if (state == `WBQSPI_READ_ID_CMD)
730
        begin // We came into here immediately after issuing a 0x9f command
731
                // Now we need to read 32 bits of data.  Result should be
732
                // 0x0102154d (8'h manufacture ID, 16'h device ID, followed
733
                // by the number of extended bytes available 8'h4d).
734
                o_wb_ack <= 1'b0;
735
                o_wb_stall<= 1'b1;
736
 
737
                spi_wr <= 1'b1; // No data to send, but need four bytes, since
738
                spi_len <= 2'b11; // 32 bits of data are ... useful
739
                spi_in <= 32'h00; // Irrelevant
740
                spi_spd <= 1'b0; // Slow speed
741
                spi_dir <= 1'b1; // Reading
742
                spi_hold <= 1'b0;
743
                spif_req <= (spif_req) && (i_wb_cyc);
744
                if ((~spi_busy)&&(~o_qspi_cs_n)&&(spi_len == 2'b11))
745
                        // Our command was accepted, now go read the result
746
                        state <= `WBQSPI_READ_ID;
747
        end else if (state == `WBQSPI_READ_ID)
748
        begin
749
                o_wb_ack <= 1'b0; // Assuming we're still waiting
750
                o_wb_stall <= 1'b1;
751
 
752
                spi_wr <= 1'b0; // No more writes, we've already written the cmd
753
                spi_hold <= 1'b0;
754
                spif_req <= (spif_req) && (i_wb_cyc);
755
 
756
                // Here, we just wait until the result comes back
757
                // The problem is, the result may be the previous result.
758
                // So we use spi_len as an indicator
759
                spi_len <= 2'b00;
760
                if((spi_valid)&&(spi_len==2'b00))
761
                begin // Put the results out as soon as possible
762
                        o_wb_data <= spi_out[31:0];
763
                        o_wb_ack <= spif_req;
764
                        spif_req <= 1'b0;
765
                end else if ((~spi_busy)&&(o_qspi_cs_n))
766
                begin
767
                        state <= `WBQSPI_IDLE;
768
                        o_wb_stall <= 1'b0;
769
                end
770
        end else if (state == `WBQSPI_READ_STATUS)
771
        begin // We enter after the command has been given, for now just
772
                // read and return
773
                spi_wr <= 1'b0;
774
                o_wb_ack <= 1'b0;
775
                spi_hold <= 1'b0;
776
                spif_req <= (spif_req) && (i_wb_cyc);
777
                if (spi_valid)
778
                begin
779
                        o_wb_ack <= spif_req;
780
                        o_wb_stall <= 1'b1;
781
                        spif_req <= 1'b0;
782
                        last_status <= spi_out[7:0];
783
                        write_in_progress <= spi_out[0];
784
                        if (spif_addr[1:0] == 2'b00) // Local read, checking
785
                        begin // status, 'cause we're writing
786
                                o_wb_data <= { spi_out[0],
787
                                        dirty_sector, spi_busy,
788
                                        ~write_protect,
789
                                        quad_mode_enabled,
790
                                        {(29-ADDRESS_WIDTH){1'b0}},
791
                                        erased_sector, 14'h000 };
792
                        end else begin
793
                                o_wb_data <= { 24'h00, spi_out[7:0] };
794
                        end
795
                end
796
 
797
                if ((~spi_busy)&&(~spi_wr))
798
                        state <= `WBQSPI_IDLE;
799
        end else if (state == `WBQSPI_READ_CONFIG)
800
        begin // We enter after the command has been given, for now just
801
                // read and return
802
                spi_wr <= 1'b0;
803
                o_wb_ack <= 1'b0;
804
                o_wb_stall <= 1'b1;
805
                spi_hold <= 1'b0;
806
                spif_req <= (spif_req) && (i_wb_cyc);
807
 
808
                if (spi_valid)
809
                begin
810
                        o_wb_data <= { 24'h00, spi_out[7:0] };
811
                        quad_mode_enabled <= spi_out[1];
812
                end
813
 
814
                if ((~spi_busy)&&(~spi_wr))
815
                begin
816
                        state <= `WBQSPI_IDLE;
817
                        o_wb_ack   <= spif_req;
818
                        o_wb_stall <= 1'b0;
819
                        spif_req <= 1'b0;
820
                end
821
 
822
//
823
//
824
//      Write/erase data section
825
//
826
`ifndef READ_ONLY
827
        end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
828
        begin
829
                o_wb_stall <= 1'b1;
830
                o_wb_ack   <= 1'b0;
831
                spi_wr <= 1'b0;
832
                spif_req<= (spif_req) && (i_wb_cyc);
833
                if (~spi_busy)
834
                begin
835
                        spi_wr   <= 1'b1;
836
                        spi_in   <= { 8'h05, 24'h0000 };
837
                        spi_hold <= 1'b1;
838
                        spi_len  <= 2'b01; // 16 bits write, so we can read 8
839
                        state <= `WBQSPI_CHECK_WIP_CLEAR;
840
                        spi_spd  <= 1'b0; // Slow speed
841
                        spi_dir  <= 1'b0;
842
                end
843
        end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
844
        begin
845
                o_wb_stall <= 1'b1;
846
                o_wb_ack   <= 1'b0;
847
                // Repeat as often as necessary until we are clear
848
                spi_wr <= 1'b1;
849
                spi_in <= 32'h0000; // Values here are actually irrelevant
850
                spi_hold <= 1'b1;
851
                spi_len <= 2'b00; // One byte at a time
852
                spi_spd  <= 1'b0; // Slow speed
853
                spi_dir  <= 1'b0;
854
                spif_req<= (spif_req) && (i_wb_cyc);
855
                if ((spi_valid)&&(~spi_out[0]))
856
                begin
857
                        state <= `WBQSPI_CHECK_WIP_DONE;
858
                        spi_wr   <= 1'b0;
859
                        spi_hold <= 1'b0;
860
                        write_in_progress <= 1'b0;
861
                        last_status <= spi_out[7:0];
862
                end
863
        end else if (state == `WBQSPI_CHECK_WIP_DONE)
864
        begin
865
                o_wb_stall <= 1'b1;
866
                o_wb_ack   <= 1'b0;
867
                // Let's let the SPI port come back to a full idle,
868
                // and the chip select line go low before continuing
869
                spi_wr   <= 1'b0;
870
                spi_len  <= 2'b00;
871
                spi_hold <= 1'b0;
872
                spi_spd  <= 1'b0; // Slow speed
873
                spi_dir  <= 1'b0;
874
                spif_req<= (spif_req) && (i_wb_cyc);
875
                if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
876
                begin
877
                        spi_wr   <= 1'b0;
878
                        spi_hold <= 1'b0;
879
 
880
                        casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
881
                        4'b00??: begin // Read data from ... somewhere
882
                                spi_wr     <= 1'b1;     // Write cmd to device
883
                                if (quad_mode_enabled)
884
                                begin
885
                                        spi_in <= { 8'heb,
886
                                                {(24-ADDRESS_WIDTH){1'b0}},
887
                                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
888
                                        state <= `WBQSPI_QRD_ADDRESS;
889
                                        // spi_len    <= 2'b00; // single byte, cmd only
890
                                end else begin
891
                                        spi_in <= { 8'h0b,
892
                                                {(24-ADDRESS_WIDTH){1'b0}},
893
                                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
894
                                        state <= `WBQSPI_RD_DUMMY;
895
                                        spi_len    <= 2'b11; // Send cmd and addr
896
                                end end
897
                        4'b10??: begin // Write data to ... anywhere
898
                                spi_wr <= 1'b1;
899
                                spi_len <= 2'b00; // 8 bits
900
                                // Send a write enable command
901
                                spi_in <= { 8'h06, 24'h00 };
902
                                state <= `WBQSPI_WEN;
903
                                end
904
                        4'b0110: begin // Read status register
905
                                state <= `WBQSPI_READ_STATUS;
906
                                spi_wr <= 1'b1;
907
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
908
                                spi_in <= { 8'h05, 24'h00};
909
                                end
910
                        4'b0111: begin
911
                                state <= `WBQSPI_READ_ID_CMD;
912
                                spi_wr <= 1'b1;
913
                                spi_len <= 2'b00;
914
                                spi_in <= { 8'h9f, 24'h00};
915
                                end
916
                        default: begin //
917
                                o_wb_stall <= 1'b1;
918
                                o_wb_ack <= spif_req;
919
                                state <= `WBQSPI_WAIT_TIL_IDLE;
920
                                end
921
                        endcase
922
                // spif_cmd   <= i_wb_we;
923
                // spif_addr  <= i_wb_addr;
924
                // spif_data  <= i_wb_data;
925
                // spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
926
                // spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
927
                end
928
        end else if (state == `WBQSPI_WEN)
929
        begin // We came here after issuing a write enable command
930
                spi_wr <= 1'b0;
931
                o_wb_ack <= 1'b0;
932
                o_wb_stall <= 1'b1;
933
                spif_req<= (spif_req) && (i_wb_cyc);
934
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
935
                        state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
936
                        // state <= `WBQSPI_PP;
937
        end else if (state == `WBQSPI_PP)
938
        begin // We come here under a full stop / full port idle mode
939
                // Issue our command immediately
940
                spi_wr <= 1'b1;
941
                spi_in <= { 8'h02,
942
                                {(24-ADDRESS_WIDTH){1'b0}},
943
                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
944
                spi_len <= 2'b11;
945
                spi_hold <= 1'b1;
946
                spi_spd  <= 1'b0;
947
                spi_dir  <= 1'b0; // Writing
948
                spif_req<= (spif_req) && (i_wb_cyc);
949
 
950
                // Once we get busy, move on
951
                if (spi_busy)
952
                        state <= `WBQSPI_WR_DATA;
953
                if (spif_sector == erased_sector)
954
                        dirty_sector <= 1'b1;
955
        end else if (state == `WBQSPI_QPP)
956
        begin // We come here under a full stop / full port idle mode
957
                // Issue our command immediately
958
                spi_wr <= 1'b1;
959
                spi_in <= { 8'h32,
960
                                {(24-ADDRESS_WIDTH){1'b0}},
961
                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
962
                spi_len <= 2'b11;
963
                spi_hold <= 1'b1;
964
                spi_spd  <= 1'b0;
965
                spi_dir  <= 1'b0; // Writing
966
                spif_req<= (spif_req) && (i_wb_cyc);
967
 
968
                // Once we get busy, move on
969
                if (spi_busy)
970
                begin
971
                        // spi_wr is irrelevant here ...
972
                        // Set the speed value once, but wait til we get busy
973
                        // to do so.
974
                        spi_spd <= 1'b1;
975
                        state <= `WBQSPI_WR_DATA;
976
                end
977
                if (spif_sector == erased_sector)
978
                        dirty_sector <= 1'b1;
979
        end else if (state == `WBQSPI_WR_DATA)
980
        begin
981
                o_wb_stall <= 1'b1;
982
                o_wb_ack   <= 1'b0;
983
                spi_wr   <= 1'b1; // write without waiting
984
                spi_in   <= {
985
                        spif_data[ 7: 0],
986
                        spif_data[15: 8],
987
                        spif_data[23:16],
988
                        spif_data[31:24] };
989
                spi_len  <= 2'b11; // Write 4 bytes
990
                spi_hold <= 1'b1;
991
                if (~spi_busy)
992
                begin
993
                        o_wb_ack <= spif_req; // Ack when command given
994
                        state <= `WBQSPI_WR_BUS_CYCLE;
995
                end
996
                spif_req<= (spif_req) && (i_wb_cyc);
997
        end else if (state == `WBQSPI_WR_BUS_CYCLE)
998
        begin
999
                o_wb_ack <= 1'b0; // Turn off our ack and stall flags
1000
                o_wb_stall <= 1'b1;
1001
                spi_wr <= 1'b0;
1002
                spi_hold <= 1'b1;
1003
                write_in_progress <= 1'b1;
1004
                spif_req<= (spif_req) && (i_wb_cyc);
1005
                if (~i_wb_cyc)
1006
                begin
1007
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1008
                        spi_hold <= 1'b0;
1009
                end else if (spi_wr)
1010
                begin // Give the SPI a chance to get busy on the last write
1011
                        // Do nothing here.
1012
                end else if ((i_wb_data_stb)&&(i_wb_we)
1013
                                &&(i_wb_addr == (spif_addr+1))
1014
                                &&(i_wb_addr[(ADDRESS_WIDTH-3):6]==spif_addr[(ADDRESS_WIDTH-3):6]))
1015
                begin
1016
                        spif_cmd  <= 1'b1;
1017
                        spif_data <= i_wb_data;
1018
                        spif_addr <= i_wb_addr;
1019
                        spif_ctrl  <= 1'b0;
1020
                        spif_req<= 1'b1;
1021
                        // We'll keep the bus stalled on this request
1022
                        // for a while
1023
                        state <= `WBQSPI_WR_DATA;
1024
                        o_wb_ack   <= 1'b0;
1025
                        o_wb_stall <= 1'b0;
1026
                end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
1027
                begin
1028
                        spi_hold <= 1'b0;
1029
                        spi_wr   <= 1'b0;
1030
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1031
                end // Otherwise we stay here
1032
        end else if (state == `WBQSPI_WRITE_CONFIG)
1033
        begin // We enter immediately after commanding a WEN
1034
                o_wb_ack   <= 1'b0;
1035
                o_wb_stall <= 1'b1;
1036
 
1037
                spi_len <= 2'b10;
1038
                spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
1039
                spi_wr <= 1'b0;
1040
                spi_hold <= 1'b0;
1041
                spif_req <= (spif_req) && (i_wb_cyc);
1042
                if ((~spi_busy)&&(~spi_wr))
1043
                begin
1044
                        spi_wr <= 1'b1;
1045
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1046
                        write_in_progress <= 1'b1;
1047
                        quad_mode_enabled <= spif_data[1];
1048
                end
1049
        end else if (state == `WBQSPI_WRITE_STATUS)
1050
        begin // We enter immediately after commanding a WEN
1051
                o_wb_ack   <= 1'b0;
1052
                o_wb_stall <= 1'b1;
1053
 
1054
                spi_len <= 2'b01;
1055
                spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
1056
                // last_status <= i_wb_data[7:0]; // We'll read this in a moment
1057
                spi_wr <= 1'b0;
1058
                spi_hold <= 1'b0;
1059
                spif_req <= (spif_req) && (i_wb_cyc);
1060
                if ((~spi_busy)&&(~spi_wr))
1061
                begin
1062
                        spi_wr <= 1'b1;
1063
                        last_status <= spif_data[7:0];
1064
                        write_in_progress <= 1'b1;
1065
                        if(((last_status[6])||(last_status[5]))
1066
                                &&((~spif_data[6])&&(~spif_data[5])))
1067
                                state <= `WBQSPI_CLEAR_STATUS;
1068
                        else
1069
                                state <= `WBQSPI_WAIT_TIL_IDLE;
1070
                end
1071
        end else if (state == `WBQSPI_ERASE_CMD)
1072
        begin // Know that WIP is clear on entry, WEN has just been commanded
1073
                spi_wr     <= 1'b0;
1074
                o_wb_ack   <= 1'b0;
1075
                o_wb_stall <= 1'b1;
1076
                spi_hold   <= 1'b0;
1077
                spi_spd <= 1'b0;
1078
                spi_dir <= 1'b0;
1079
                spif_req <= (spif_req) && (i_wb_cyc);
1080
 
1081
                // Here's the erase command
1082
                spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
1083
                spi_len <= 2'b11; // 32 bit write
1084
                // together with setting our copy of the WIP bit
1085
                write_in_progress <= 1'b1;
1086
                // keeping track of which sector we just erased
1087
                erased_sector <= spif_data[(ADDRESS_WIDTH-3):14];
1088
                // and marking this erase sector as no longer dirty
1089
                dirty_sector <= 1'b0;
1090
 
1091
                // Wait for a full stop before issuing this command
1092
                if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
1093
                begin // When our command is accepted, move to the next state
1094
                        spi_wr <= 1'b1;
1095
                        state <= `WBQSPI_ERASE_BLOCK;
1096
                end
1097
        end else if (state == `WBQSPI_ERASE_BLOCK)
1098
        begin
1099
                spi_wr     <= 1'b0;
1100
                spi_hold   <= 1'b0;
1101
                o_wb_stall <= 1'b1;
1102
                o_wb_ack   <= 1'b0;
1103
                spif_req <= (spif_req) && (i_wb_cyc);
1104
                // When the port clears, we can head back to idle
1105
                if ((~spi_busy)&&(~spi_wr))
1106
                begin
1107
                        o_wb_ack <= spif_req;
1108
                        state <= `WBQSPI_IDLE;
1109
                end
1110
        end else if (state == `WBQSPI_CLEAR_STATUS)
1111
        begin // Issue a clear status command
1112
                spi_wr <= 1'b1;
1113
                spi_hold <= 1'b0;
1114
                spi_len <= 2'b00; // 8 bit command
1115
                spi_in <= { 8'h30, 24'h00 };
1116
                spi_spd <= 1'b0;
1117
                spi_dir <= 1'b0;
1118
                last_status[6:5] <= 2'b00;
1119
                spif_req <= (spif_req) && (i_wb_cyc);
1120
                if ((spi_wr)&&(~spi_busy))
1121
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1122
        end else if (state == `WBQSPI_IDLE_CHECK_WIP)
1123
        begin // We are now in read status register mode
1124
 
1125
                // No bus commands have (yet) been given
1126
                o_wb_stall <= 1'b1;
1127
                o_wb_ack   <= 1'b0;
1128
                spif_req <= (spif_req) && (i_wb_cyc);
1129
 
1130
                // Stay in this mode unless/until we get a command, or
1131
                //      the write is over
1132
                spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
1133
                                &&(write_in_progress));
1134
                spi_len <= 2'b00; // 8 bit reads
1135
                spi_spd <= 1'b0;  // SPI, not quad
1136
                spi_dir <= 1'b1;  // Read
1137
                if (spi_valid)
1138
                begin
1139
                        write_in_progress <= spi_out[0];
1140
                        if ((~spi_out[0])&&(write_in_progress))
1141
                                o_interrupt <= 1'b1;
1142
                end else
1143
                        o_interrupt <= 1'b0;
1144
 
1145
                if ((~spi_wr)&&(~spi_busy)&&(o_qspi_cs_n))
1146
                begin // We can now go to idle and process a command
1147
                        o_wb_stall <= 1'b0;
1148
                        o_wb_ack   <= 1'b0;
1149
                        state <= `WBQSPI_IDLE;
1150
                end
1151
`endif //       !READ_ONLY
1152
        end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
1153
        begin
1154
                spi_wr     <= 1'b0;
1155
                spi_hold   <= 1'b0;
1156
                o_wb_stall <= 1'b1;
1157
                o_wb_ack   <= 1'b0;
1158
                spif_req   <= 1'b0;
1159
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
1160
                begin // clearing of the SPI port before moving on
1161
                        state <= `WBQSPI_IDLE;
1162
                        o_wb_stall <= 1'b0;
1163
                        o_wb_ack   <= 1'b0; // Shouldn't be acking anything here
1164
                end
1165
        end
1166
        end
1167
 
1168
        // Command and control during the reset sequence
1169
        assign  o_qspi_cs_n = (spif_override)?spif_cmd :w_qspi_cs_n;
1170
        assign  o_qspi_sck  = (spif_override)?spif_ctrl:w_qspi_sck;
1171
        assign  o_qspi_mod  = (spif_override)?   2'b01 :w_qspi_mod;
1172
        assign  o_qspi_dat  = (spif_override)?   4'b00 :w_qspi_dat;
1173
endmodule

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