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[/] [s6soc/] [trunk/] [rtl/] [wbscopc.v] - Blame information for rev 46

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1 46 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    wbscopc.v
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//
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// Project:     FPGA Library of Routines
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//
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// Purpose:     This scope is identical in function to the wishbone scope
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//      found in wbscope, save that the output is compressed and that (as a
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//      result) it can only handle recording 31 bits at a time.  This allows
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//      the top bit to indicate an 'address difference'.   Okay, there's 
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//      another difference as well: this version only works in a synchronous
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//      fashion with the clock from the WB bus.  You cannot have a separate
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//      bus and data clock.
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//
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//      Reading/decompressing the output of this scope works in this fashion:
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//      Once the scope has stopped, read from the port.  Any time the high
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//      order bit is set, the other 31 bits tell you how many times to repeat
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//      the last value.  If the high order bit is not set, then the value
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//      is a new data value.
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//
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//      I've provided this version of a compressed scope to OpenCores for
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//      discussion purposes.  While wbscope.v works and works well by itself,
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//      this compressed scope has a couple of fundamental flaw that I have
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//      yet to fix.  One of them is that it is impossible to know when the
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//      trigger took place.  The second problem is that it may be impossible
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//      to know the state of the scope at the beginning of the buffer--should
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//      the buffer begin with an address difference value instead of a data
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//      value.
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//
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//      Ideally, the first item read out of the scope should be a data value,
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//      even if the scope was skipping values to a new address at the time.
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//      If it was in the middle of a skip, the next item out of the scope
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//      should be the skip length.  This, though, violates the rule that there
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//      are (1<<LGMEMLEN) items in the memory, and that the trigger took place
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//      on the last item of memory ... so that portion of this compressed
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//      scope is still to be defined.
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//
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//      Like I said, this version is placed here for discussion purposes,
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//      not because it runs well nor because I have recognized that it has any
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//      particular value (yet).
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//
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//      Well, I take that back.  When dealing with an interface such as the
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//      PS/2 interface, or even the 16x2 LCD interface, it is often true
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//      that things change _very_ slowly.  They could change so slowly that
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//      the other approach to the scope doesn't work.  This then gives you
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//      a working scope, by only capturing the changes.  You'll still need
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//      to figure out (after the fact) when the trigge took place.  Perhaps
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//      you'll wish to add the trigger as another data line, so you can find
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//      when it took place in your own data?
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//
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//      Okay, I take that back twice: I'm finding this compressed scope very
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//      valuable for evaluating the timing associated with a GPS PPS and
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//      associated NMEA stream.  I need to collect over a seconds worth of
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//      data, and I don't have enough memory to handle one memory value per
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//      clock, yet I still want to know exactly when the GPS PPS goes high,
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//      when it goes low, when I'm adjusting my clock, and when the clock's
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//      PPS output goes high.  Did I synchronize them well?  Oh, and when does
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//      the NMEA time string show up when compared with the PPS?  All of those
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//      are valuable, but could never be done if the scope wasn't compressed.
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015,2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module wbscopc(i_clk, i_ce, i_trigger, i_data,
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        i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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        o_wb_ack, o_wb_stall, o_wb_data,
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        o_interrupt);
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        parameter       LGMEM = 5'd10, NELM=31, BUSW = 32, SYNCHRONOUS=1;
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        // The input signals that we wish to record
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        input                           i_clk, i_ce, i_trigger;
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        input           [(NELM-1):0]     i_data;
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        // The WISHBONE bus for reading and configuring this scope
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        input                           i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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        input                           i_wb_addr; // One address line only
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        input           [(BUSW-1):0]     i_wb_data;
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        output  wire                    o_wb_ack, o_wb_stall;
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        output  wire    [(BUSW-1):0]     o_wb_data;
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        // And, finally, for a final flair --- offer to interrupt the CPU after
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        // our trigger has gone off.  This line is equivalent to the scope 
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        // being stopped.  It is not maskable here.
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        output  wire                    o_interrupt;
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        // Let's first see how far we can get by cheating.  We'll use the
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        // wbscope program, and suffer a lack of several features
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        // When is the full scope reset?  Capture that reset bit from any
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        // write.
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        wire    lcl_reset;
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        assign  lcl_reset = (i_wb_stb)&&(~i_wb_addr)&&(i_wb_we)
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                                &&(~i_wb_data[31]);
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        // A big part of this scope is the 'address' of any particular
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        // data value.  As of this current version, the 'address' changed
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        // in definition from an absolute time (which had all kinds of
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        // problems) to a difference in time.  Hence, when the address line
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        // is high on decompression, the 'address' field will record an
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        // address difference.
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        //
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        // To implement this, we set our 'address' to zero any time the
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        // data changes, but increment it on all other clocks.  Should the
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        // address difference get to our maximum value, we let it saturate
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        // rather than overflow.
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        reg     [(BUSW-2):0]     ck_addr;
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        reg     [(NELM-1):0]     lst_dat;
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        initial ck_addr = 0;
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        always @(posedge i_clk)
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                if ((lcl_reset)||((i_ce)&&(i_data != lst_dat)))
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                        ck_addr <= 0;
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                else if (&ck_addr)
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                        ;       // Saturated (non-overflowing) address diff
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                else
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                        ck_addr <= ck_addr + 1;
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        wire    [(BUSW-2):0]     w_data;
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        generate
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        if (NELM == BUSW-1)
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                assign w_data = i_data;
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        else
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                assign w_data = { {(BUSW-NELM-1){1'b0}}, i_data };
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        endgenerate
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        //
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        // To do our compression, we keep track of two registers: the most
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        // recent data to the device (imm_ prefix) and the data from one
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        // clock ago.  This allows us to suppress writes to the scope which
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        // would otherwise be two address writes in a row.
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        reg     imm_adr, lst_adr; // Is this an address (1'b1) or data value?
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        reg     [(BUSW-2):0]     lst_val, // Data for the scope, delayed by one
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                                imm_val; // Data to write to the scope
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        initial lst_dat = 0;
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        initial lst_adr = 1'b1;
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        initial imm_adr = 1'b1;
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        always @(posedge i_clk)
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                if (lcl_reset)
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                begin
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                        imm_val <= 31'h0;
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                        imm_adr <= 1'b1;
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                        lst_val <= 31'h0;
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                        lst_adr <= 1'b1;
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                        lst_dat <= 0;
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                end else if ((i_ce)&&(i_data != lst_dat))
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                begin
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                        imm_val <= w_data;
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                        imm_adr <= 1'b0;
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                        lst_val <= imm_val;
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                        lst_adr <= imm_adr;
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                        lst_dat <= i_data;
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                end else begin
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                        imm_val <= ck_addr; // Minimum value here is '1'
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                        imm_adr <= 1'b1;
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                        lst_val <= imm_val;
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                        lst_adr <= imm_adr;
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                end
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        //
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        // Here's where we suppress writing pairs of address words to the
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        // scope at once.
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        //
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        reg                     r_ce;
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        reg     [(BUSW-1):0]     r_data;
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        initial                 r_ce = 1'b0;
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        always @(posedge i_clk)
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                r_ce <= (~lst_adr)||(~imm_adr);
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        always @(posedge i_clk)
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                r_data <= ((~lst_adr)||(~imm_adr))
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                        ? { lst_adr, lst_val }
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                        : { {(32 - NELM){1'b0}}, i_data };
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        //
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        // The trigger needs some extra attention, in order to keep triggers
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        // that happen between events from being ignored.  
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        //
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        wire    w_trigger;
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        assign  w_trigger = (r_trigger)||(i_trigger);
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        reg     r_trigger;
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        initial r_trigger = 1'b0;
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        always @(posedge i_clk)
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                if (lcl_reset)
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                        r_trigger <= 1'b0;
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                else
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                        r_trigger <= w_trigger;
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        //
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        // Call the regular wishbone scope to do all of our real work, now
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        // that we've compressed the input.
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        //
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        wbscope #(.SYNCHRONOUS(1), .LGMEM(LGMEM),
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                .BUSW(BUSW))    cheatersscope(i_clk, r_ce, w_trigger, r_data,
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                i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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                o_wb_ack, o_wb_stall, o_wb_data, o_interrupt);
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endmodule

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