OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [wbscope.v] - Blame information for rev 16

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    wbscope.v
4
//
5
// Project:     FPGA Library of Routines
6
//
7
// Purpose:     This is a generic/library routine for providing a bus accessed
8
//              'scope' or (perhaps more appropriately) a bus accessed logic
9
//              analyzer.  The general operation is such that this 'scope' can
10
//              record and report on any 32 bit value transiting through the
11
//              FPGA.  Once started and reset, the scope records a copy of the
12
//              input data every time the clock ticks with the circuit enabled.
13
//              That is, it records these values up until the trigger.  Once
14
//              the trigger goes high, the scope will record for bw_holdoff
15
//              more counts before stopping.  Values may then be read from the
16
//              buffer, oldest to most recent.  After reading, the scope may
17
//              then be reset for another run.
18
//
19
//              In general, therefore, operation happens in this fashion:
20
//              1. A reset is issued.
21
//              2. Recording starts, in a circular buffer, and continues until
22
//              3. The trigger line is asserted.
23
//                      The scope registers the asserted trigger by setting
24
//                      the 'o_triggered' output flag.
25
//              4. A counter then ticks until the last value is written
26
//                      The scope registers that it has stopped recording by
27
//                      setting the 'o_stopped' output flag.
28
//              5. The scope recording is then paused until the next reset.
29
//              6. While stopped, the CPU can read the data from the scope
30
//              7. -- oldest to most recent
31
//              8. -- one value per i_rd&i_clk
32
//              9. Writes to the data register reset the address to the
33
//                      beginning of the buffer
34
//
35
//      Although the data width DW is parameterized, it is not very changable,
36
//      since the width is tied to the width of the data bus, as is the 
37
//      control word.  Therefore changing the data width would require changing
38
//      the interface.  It's doable, but it would be a change to the interface.
39
//
40
//      The SYNCHRONOUS parameter turns on and off meta-stability
41
//      synchronization.  Ideally a wishbone scope able to handle one or two
42
//      clocks would have a changing number of ports as this SYNCHRONOUS
43
//      parameter changed.  Other than running another script to modify
44
//      this, I don't know how to do that so ... we'll just leave it running
45
//      off of two clocks or not.
46
//
47
//
48
//      Internal to this routine, registers and wires are named with one of the
49
//      following prefixes:
50
//
51
//      i_      An input port to the routine
52
//      o_      An output port of the routine
53
//      br_     A register, controlled by the bus clock
54
//      dr_     A register, controlled by the data clock
55
//      bw_     A wire/net, controlled by the bus clock
56
//      dw_     A wire/net, controlled by the data clock
57
//
58
// Creator:     Dan Gisselquist, Ph.D.
59
//              Gisselquist Technology, LLC
60
//
61
///////////////////////////////////////////////////////////////////////////
62
//
63
// Copyright (C) 2015, Gisselquist Technology, LLC
64
//
65
// This program is free software (firmware): you can redistribute it and/or
66
// modify it under the terms of  the GNU General Public License as published
67
// by the Free Software Foundation, either version 3 of the License, or (at
68
// your option) any later version.
69
//
70
// This program is distributed in the hope that it will be useful, but WITHOUT
71
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
72
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
73
// for more details.
74
//
75
// You should have received a copy of the GNU General Public License along
76
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
77
// target there if the PDF file isn't present.)  If not, see
78
// <http://www.gnu.org/licenses/> for a copy.
79
//
80
// License:     GPL, v3, as defined and found on www.gnu.org,
81
//              http://www.gnu.org/licenses/gpl.html
82
//
83
//
84
/////////////////////////////////////////////////////////////////////////////
85
module wbscope(i_clk, i_ce, i_trigger, i_data,
86
        i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
87
        o_wb_ack, o_wb_stall, o_wb_data,
88
        o_interrupt);
89
        parameter       LGMEM = 5'd10, BUSW = 32, SYNCHRONOUS=1;
90
        // The input signals that we wish to record
91
        input                           i_clk, i_ce, i_trigger;
92
        input           [(BUSW-1):0]     i_data;
93
        // The WISHBONE bus for reading and configuring this scope
94
        input                           i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
95
        input                           i_wb_addr; // One address line only
96
        input           [(BUSW-1):0]     i_wb_data;
97
        output  wire                    o_wb_ack, o_wb_stall;
98
        output  reg     [(BUSW-1):0]     o_wb_data;
99
        // And, finally, for a final flair --- offer to interrupt the CPU after
100
        // our trigger has gone off.  This line is equivalent to the scope 
101
        // being stopped.  It is not maskable here.
102
        output  wire                    o_interrupt;
103
 
104
        reg     [(LGMEM-1):0]    raddr;
105
        reg     [(BUSW-1):0]     mem[0:((1<<LGMEM)-1)];
106
 
107
        // Our status/config register
108
        wire            bw_reset_request, bw_manual_trigger,
109
                        bw_disable_trigger, bw_reset_complete;
110
        reg     [22:0]   br_config;
111
        wire    [19:0]   bw_holdoff;
112
        initial br_config = ((1<<(LGMEM-1))-4);
113
        always @(posedge i_wb_clk)
114
                if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr))
115
                begin
116
                        if (i_wb_we)
117
                                br_config <= { i_wb_data[31],
118
                                        (i_wb_data[27]),
119
                                        i_wb_data[26],
120
                                        i_wb_data[19:0] };
121
                end else if (bw_reset_complete)
122
                        br_config[22] <= 1'b1;
123
        assign  bw_reset_request   = (~br_config[22]);
124
        assign  bw_manual_trigger  = (br_config[21]);
125
        assign  bw_disable_trigger = (br_config[20]);
126
        assign  bw_holdoff         = br_config[19:0];
127
 
128
        wire    dw_reset, dw_manual_trigger, dw_disable_trigger;
129
        generate
130
        if (SYNCHRONOUS > 0)
131
        begin
132
                assign  dw_reset = bw_reset_request;
133
                assign  dw_manual_trigger = bw_manual_trigger;
134
                assign  dw_disable_trigger = bw_disable_trigger;
135
                assign  bw_reset_complete = bw_reset_request;
136
        end else begin
137
                reg             r_reset_complete;
138
                reg     [2:0]    r_iflags, q_iflags;
139
 
140
                // Resets are synchronous to the bus clock, not the data clock
141
                // so do a clock transfer here
142
                initial q_iflags = 3'b000;
143
                initial r_reset_complete = 1'b0;
144
                always @(posedge i_clk)
145
                begin
146
                        q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger };
147
                        r_iflags <= q_iflags;
148
                        r_reset_complete <= (dw_reset);
149
                end
150
 
151
                assign  dw_reset = r_iflags[2];
152
                assign  dw_manual_trigger = r_iflags[1];
153
                assign  dw_disable_trigger = r_iflags[0];
154
 
155
                reg     q_reset_complete, qq_reset_complete;
156
                // Pass an acknowledgement back from the data clock to the bus
157
                // clock that the reset has been accomplished
158
                initial q_reset_complete = 1'b0;
159
                initial qq_reset_complete = 1'b0;
160
                always @(posedge i_wb_clk)
161
                begin
162
                        q_reset_complete  <= r_reset_complete;
163
                        qq_reset_complete <= q_reset_complete;
164
                end
165
 
166
                assign bw_reset_complete = qq_reset_complete;
167
        end endgenerate
168
 
169
        //
170
        // Set up the trigger
171
        //
172
        //
173
        // Write with the i-clk, or input clock.  All outputs read with the
174
        // WISHBONE-clk, or i_wb_clk clock.
175
        reg     dr_triggered, dr_primed;
176
        wire    dw_trigger;
177
        assign  dw_trigger = (dr_primed)&&(
178
                                ((i_trigger)&&(~dw_disable_trigger))
179
                                ||(dr_triggered)
180
                                ||(dw_manual_trigger));
181
        initial dr_triggered = 1'b0;
182
        always @(posedge i_clk)
183
                if (dw_reset)
184
                        dr_triggered <= 1'b0;
185
                else if ((i_ce)&&(dw_trigger))
186
                        dr_triggered <= 1'b1;
187
 
188
        //
189
        // Determine when memory is full and capture is complete
190
        //
191
        // Writes take place on the data clock
192
        reg             dr_stopped;
193
        reg     [19:0]   counter;        // This is unsigned
194
        initial dr_stopped = 1'b0;
195
        initial counter = 20'h0000;
196
        always @(posedge i_clk)
197
                if (dw_reset)
198
                begin
199
                        counter <= 0;
200
                        dr_stopped <= 1'b0;
201
                end else if ((i_ce)&&(dr_triggered))
202
                begin // MUST BE a < and not <=, so that we can keep this w/in
203
                        // 20 bits.  Else we'd need to add a bit to comparison 
204
                        // here.
205
                        if (counter < bw_holdoff)
206
                                counter <= counter + 20'h01;
207
                        else
208
                                dr_stopped <= 1'b1;
209
                end
210
 
211
        //
212
        //      Actually do our writes to memory.  Record, via 'primed' when
213
        //      the memory is full.
214
        //
215
        //      The 'waddr' address that we are using really crosses two clock
216
        //      domains.  While writing and changing, it's in the data clock
217
        //      domain.  Once stopped, it becomes part of the bus clock domain.
218
        //      The clock transfer on the stopped line handles the clock
219
        //      transfer for these signals.
220
        //
221
        reg     [(LGMEM-1):0]    waddr;
222
        initial waddr = {(LGMEM){1'b0}};
223
        initial dr_primed = 1'b0;
224
        always @(posedge i_clk)
225
                if (dw_reset) // For simulation purposes, supply a valid value
226
                begin
227
                        waddr <= 0; // upon reset.
228
                        dr_primed <= 1'b0;
229
                end else if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
230
                begin
231
                        // mem[waddr] <= i_data;
232
                        waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
233
                        dr_primed <= (dr_primed)||(&waddr);
234
                end
235
        always @(posedge i_clk)
236
                if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
237
                        mem[waddr] <= i_data;
238
 
239
        //
240
        // Clock transfer of the status signals
241
        //
242
        wire    bw_stopped, bw_triggered, bw_primed;
243
        generate
244
        if (SYNCHRONOUS > 0)
245
        begin
246
                assign  bw_stopped   = dr_stopped;
247
                assign  bw_triggered = dr_triggered;
248
                assign  bw_primed    = dr_primed;
249
        end else begin
250
                // These aren't a problem, since none of these are strobe
251
                // signals.  They goes from low to high, and then stays high
252
                // for many clocks.  Swapping is thus easy--two flip flops to
253
                // protect against meta-stability and we're done.
254
                //
255
                reg     [2:0]    q_oflags, r_oflags;
256
                initial q_oflags = 3'h0;
257
                initial r_oflags = 3'h0;
258
                always @(posedge i_wb_clk)
259
                        if (bw_reset_request)
260
                        begin
261
                                q_oflags <= 3'h0;
262
                                r_oflags <= 3'h0;
263
                        end else begin
264
                                q_oflags <= { dr_stopped, dr_triggered, dr_primed };
265
                                r_oflags <= q_oflags;
266
                        end
267
 
268
                assign  bw_stopped   = r_oflags[2];
269
                assign  bw_triggered = r_oflags[1];
270
                assign  bw_primed    = r_oflags[0];
271
        end endgenerate
272
 
273
        // Reads use the bus clock
274
        reg     br_wb_ack;
275
        initial br_wb_ack = 1'b0;
276
        wire    bw_cyc_stb;
277
        assign  bw_cyc_stb = ((i_wb_cyc)&&(i_wb_stb));
278
        always @(posedge i_wb_clk)
279
        begin
280
                if ((bw_reset_request)
281
                        ||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
282
                        raddr <= 0;
283
                else if ((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)&&(bw_stopped))
284
                        raddr <= raddr + {{(LGMEM-1){1'b0}},1'b1}; // Data read, when stopped
285
 
286
                if ((bw_cyc_stb)&&(~i_wb_we))
287
                begin // Read from the bus
288
                        br_wb_ack <= 1'b1;
289
                end else if ((bw_cyc_stb)&&(i_wb_we))
290
                        // We did this write above
291
                        br_wb_ack <= 1'b1;
292
                else // Do nothing if either i_wb_cyc or i_wb_stb are low
293
                        br_wb_ack <= 1'b0;
294
        end
295
 
296
        reg     [31:0]   nxt_mem;
297
        always @(posedge i_wb_clk)
298
                nxt_mem <= mem[raddr+waddr+
299
                        (((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)) ?
300
                                {{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
301
 
302
        wire    [4:0]    bw_lgmem;
303
        assign          bw_lgmem = LGMEM;
304
        always @(posedge i_wb_clk)
305
                if (~i_wb_addr) // Control register read
306
                        o_wb_data <= { bw_reset_request,
307
                                        bw_stopped,
308
                                        bw_triggered,
309
                                        bw_primed,
310
                                        bw_manual_trigger,
311
                                        bw_disable_trigger,
312
                                        (raddr == {(LGMEM){1'b0}}),
313
                                        bw_lgmem,
314
                                        bw_holdoff  };
315
                else if (~bw_stopped) // read, prior to stopping
316
                        o_wb_data <= i_data;
317
                else // if (i_wb_addr) // Read from FIFO memory
318
                        o_wb_data <= nxt_mem; // mem[raddr+waddr];
319
 
320
        assign  o_wb_stall = 1'b0;
321
        assign  o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
322
 
323
        reg     br_level_interrupt;
324
        initial br_level_interrupt = 1'b0;
325
        assign  o_interrupt = (bw_stopped)&&(~bw_disable_trigger)
326
                                        &&(~br_level_interrupt);
327
        always @(posedge i_wb_clk)
328
                if ((bw_reset_complete)||(bw_reset_request))
329
                        br_level_interrupt<= 1'b0;
330
                else
331
                        br_level_interrupt<= (bw_stopped)&&(~bw_disable_trigger);
332
 
333
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.