OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [sw/] [host/] [devbus.h] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    devbus.h
4
//
5 11 dgisselq
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6 8 dgisselq
//
7
// Purpose:     The purpose of this file is to document an interface which
8
//              any device with a bus, whether it be implemented over a UART,
9
//      an ethernet, or a PCI express bus, must implement.  This describes
10
//      only an interface, and not how that interface is to be accomplished.
11
//
12
//      The neat part of this interface is that, if programs are designed to
13
//      work with it, than the implementation details may be changed later
14
//      and any program that once worked with the interface should be able
15
//      to continue to do so.  (i.e., switch from a UART controlled bus to a
16
//      PCI express controlled bus, with minimal change to the software of
17
//      interest.)
18
//
19
//
20
// Creator:     Dan Gisselquist, Ph.D.
21
//              Gisselquist Technology, LLC
22
//
23
////////////////////////////////////////////////////////////////////////////////
24
//
25 11 dgisselq
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
26 8 dgisselq
//
27
// This program is free software (firmware): you can redistribute it and/or
28
// modify it under the terms of  the GNU General Public License as published
29
// by the Free Software Foundation, either version 3 of the License, or (at
30
// your option) any later version.
31
//
32
// This program is distributed in the hope that it will be useful, but WITHOUT
33
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
34
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
35
// for more details.
36
//
37 11 dgisselq
// You should have received a copy of the GNU General Public License along
38
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
39
// target there if the PDF file isn't present.)  If not, see
40
// <http://www.gnu.org/licenses/> for a copy.
41
//
42 8 dgisselq
// License:     GPL, v3, as defined and found on www.gnu.org,
43
//              http://www.gnu.org/licenses/gpl.html
44
//
45
//
46
////////////////////////////////////////////////////////////////////////////////
47
//
48
//
49
//
50
#ifndef DEVBUS_H
51
#define DEVBUS_H
52
 
53
#include <stdio.h>
54
#include <unistd.h>
55
 
56
typedef unsigned int    uint32;
57
 
58
class   BUSERR {
59
public:
60
        uint32 addr;
61
        BUSERR(const uint32 a) : addr(a) {};
62
};
63
 
64
class   DEVBUS {
65
public:
66
        typedef uint32  BUSW;
67
 
68
        virtual void    kill(void) = 0;
69
        virtual void    close(void) = 0;
70
 
71
        // Write a single value to a single address
72
        //      a is the address of the value to be read as it exists on the
73
        //              wishbone bus within the FPGA.
74
        //      v is the singular value to write to this address
75
        virtual void    writeio(const BUSW a, const BUSW v) = 0;
76
 
77
        // Read a single value to a single address
78
        //      a is the address of the value to be read as it exists on the
79
        //              wishbone bus within the FPGA.
80
        //      This function returns the value read from the device wishbone
81
        //              at address a.
82
        virtual BUSW    readio(const BUSW a) = 0;
83
 
84
        // Read a series of values from values from a block of memory
85
        //      a is the address of the value to be read as it exists on the
86
        //              wishbone bus within the FPGA.
87
        //      len is the number of words to read
88
        //      buf is a pointer to a place to store the words once read.
89
        // This is equivalent to:
90
        //      for(int i=0; i<len; i++)
91
        //              buf[i] = readio(a+i);
92
        // only it's faster in our implementation.
93
        virtual void    readi(const BUSW a, const int len, BUSW *buf) = 0;
94
 
95
        // Read a series of values from the same address in memory.  This 
96
        // call is identical to readi, save that the address is not incremented
97
        // from one read to the next.  It is equivalent to:
98
        //      for(int i=0; i<len; i++)
99
        //              buf[i] = readio(a);
100
        // only it's faster in our implementation.
101
        //
102
        virtual void    readz(const BUSW a, const int len, BUSW *buf) = 0;
103
 
104
        // Write a series of values into a block of memory on the FPGA
105
        //      a is the address of the value to be written as it exists on the
106
        //              wishbone bus within the FPGA.
107
        //      len is the number of words to write
108
        //      buf is a pointer to a place to from whence to grab the data
109
        //              to be written.
110
        // This is equivalent to:
111
        //      for(int i=0; i<len; i++)
112
        //              writeio(a+i, buf[i]);
113
        // only it's faster in our implementation.
114
        virtual void    writei(const BUSW a, const int len, const BUSW *buf) = 0;
115
        // Write a series of values into the same address on the FPGA bus.  This
116
        // call is identical to writei, save that the address is not incremented
117
        // from one write to the next.  It is equivalent to:
118
        //      for(int i=0; i<len; i++)
119
        //              writeio(a, buf[i]);
120
        // only it's faster in our implementation.
121
        //
122
        virtual void    writez(const BUSW a, const int len, const BUSW *buf) = 0;
123
 
124
        // Query whether or not an interrupt has taken place
125
        virtual bool    poll(void) = 0;
126
 
127
        // Sleep until interrupt, but sleep no longer than msec milliseconds
128
        virtual void    usleep(unsigned msec) = 0;
129
 
130
        // Sleep until an interrupt, no matter how long it takes for that
131
        // interrupt to take place
132
        virtual void    wait(void) = 0;
133
 
134
        // Query whether or not a bus error has taken place.  This is somewhat
135
        // of a misnomer, as my current bus error detection code exits any
136
        // interface, but ... it is what it is.
137
        virtual bool    bus_err(void) const = 0;
138
 
139
        // Clear any bus error condition.
140
        virtual void    reset_err(void) = 0;
141
 
142
        // Clear any interrupt condition that has already been noticed by
143
        // the interface, does not check for further interrupt
144
        virtual void    clear(void) = 0;
145
 
146
        virtual ~DEVBUS(void) { };
147
};
148
 
149
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.