OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [sw/] [host/] [regdefs.h] - Blame information for rev 12

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    regdefs.h
4
//
5
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6
//
7
// Purpose:     
8
//
9
// Creator:     Dan Gisselquist, Ph.D.
10
//              Gisselquist Technology, LLC
11
//
12
////////////////////////////////////////////////////////////////////////////////
13
//
14
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
15
//
16
// This program is free software (firmware): you can redistribute it and/or
17
// modify it under the terms of  the GNU General Public License as published
18
// by the Free Software Foundation, either version 3 of the License, or (at
19
// your option) any later version.
20
//
21
// This program is distributed in the hope that it will be useful, but WITHOUT
22
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
23
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
24
// for more details.
25
//
26
// You should have received a copy of the GNU General Public License along
27
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
28
// target there if the PDF file isn't present.)  If not, see
29
// <http://www.gnu.org/licenses/> for a copy.
30
//
31
// License:     GPL, v3, as defined and found on www.gnu.org,
32
//              http://www.gnu.org/licenses/gpl.html
33
//
34
//
35
////////////////////////////////////////////////////////////////////////////////
36
//
37
//
38
#ifndef REGDEFS_H
39
#define REGDEFS_H
40
 
41
#define R_VERSION       0x00000108
42
#define R_ICONTROL      0x00000100
43
#define R_BUSERR        0x00000101
44
#define R_ITIMERA       0x00000102
45
#define R_ITIMERB       0x00000103
46
#define R_PWM           0x00000104
47
#define R_SPIO          0x00000105
48
#define R_GPIO          0x00000106
49
#define R_UART          0x00000107
50
 
51
// WB Scope registers
52
#define R_SCOPE         0x00000200
53
#define R_SCOPED        0x00000201
54
//
55
// And because the flash driver needs these constants defined ...
56
#define R_QSPI_EREG     0x0000030c
57
#define R_QSPI_CREG     0x0000030d
58
#define R_QSPI_SREG     0x0000030e
59
#define R_QSPI_IDREG    0x0000030f
60
//
61
// FPGA CONFIG/ICAP REGISTERS
62
#define R_CFG_CRC       0x00000400
63
#define R_CFG_FAR_MAJ   0x00000401
64
#define R_CFG_FAR_MIN   0x00000402
65
#define R_CFG_FDRI      0x00000403
66
#define R_CFG_FDRO      0x00000404
67
#define R_CFG_CMD       0x00000405
68
#define R_CFG_CTL       0x00000406
69
#define R_CFG_MASK      0x00000407
70
#define R_CFG_STAT      0x00000408
71
#define R_CFG_LOUT      0x00000409
72
#define R_CFG_COR1      0x0000040a
73
#define R_CFG_COR2      0x0000040b
74
#define R_CFG_PWRDN     0x0000040c
75
#define R_CFG_FLR       0x0000040d
76
#define R_CFG_IDCODE    0x0000040e
77
#define R_CFG_CWDT      0x0000040f
78
#define R_CFG_HCOPT     0x00000410
79
#define R_CFG_CSBO      0x00000412
80
#define R_CFG_GEN1      0x00000413
81
#define R_CFG_GEN2      0x00000414
82
#define R_CFG_GEN3      0x00000415
83
#define R_CFG_GEN4      0x00000416
84
#define R_CFG_GEN5      0x00000417
85
#define R_CFG_MODE      0x00000418
86
#define R_CFG_GWE       0x00000419
87
#define R_CFG_GTS       0x0000041a
88
#define R_CFG_MFWR      0x0000041b
89
#define R_CFG_CCLK      0x0000041c
90
#define R_CFG_SEU       0x0000041d
91
#define R_CFG_EXP       0x0000041e
92
#define R_CFG_RDBK      0x0000041f
93
#define R_CFG_BOOTSTS   0x00000420
94
#define R_CFG_EYE       0x00000421
95
#define R_CFG_CBC       0x00000422
96
// RTC clock control
97
#define R_CLOCK         0x00000800
98
#define R_TIMER         0x00000801
99
#define R_STOPWATCH     0x00000802
100
#define R_CKALARM       0x00000803
101
 
102
// RAM memory space
103
#define RAMBASE         0x00002000
104
#define MEMWORDS        (1<<12)
105 11 dgisselq
#define RAMLEN          MEMWORDS
106
 
107 8 dgisselq
// Flash memory space
108 11 dgisselq
#define SPIFLASH        0x00400000
109
#define FLASHWORDS      (1<<22)
110
#define CONFIG_ADDRESS  0x00400000 // Main Xilinx configuration (ZipCPU)
111
#define ALTCONFIG_ADDRESS 0x440000 // Alternate Xilinx configuration (Debug)
112
#define RESET_ADDRESS   0x00480000 // ZipCPU Reset address
113 8 dgisselq
 
114
// Interrupt control constants
115 11 dgisselq
#define GIE             0x80000000      // Enable all interrupts
116
#define SCOPEN          0x80040004      // Enable WBSCOPE interrupts
117 12 dgisselq
#define ISPIF_EN        0x88000800      // Enable SPI Flash interrupts
118
#define ISPIF_DIS       0x08000000      // Disable SPI Flash interrupts
119
#define ISPIF_CLR       0x08000800      // Clear pending SPI Flash interrupt
120 8 dgisselq
 
121
// Flash control constants
122
#define ERASEFLAG       0x80000000
123
#define DISABLEWP       0x10000000
124
 
125 11 dgisselq
// Sectors are defined as 64 kB (16 kW)
126
#define SZPAGE          64      // 256 bytes
127
#define PGLEN           64      // 256 bytes
128
#define NPAGES          256     // 64 kB sectors / 256 bytes is ...
129 8 dgisselq
#define SECTORSZ        (NPAGES * SZPAGE)
130 11 dgisselq
#define NSECTORS        (FLASHWORDS/SECTORSZ)   // 256 sectors
131
#define SECTOROF(A)     ((A) & (-1<<14))        // 64 kB ea
132 8 dgisselq
#define PAGEOF(A)       ((A) & (-1<<6))
133
 
134
// Scop definition/sequences
135
#define SCOPE_NO_RESET  0x80000000
136
#define SCOPE_TRIGGER   (0x08000000|SCOPE_NO_RESET)
137
#define SCOPE_DISABLE   (0x04000000)
138
 
139
typedef struct {
140
        unsigned        m_addr;
141
        const char      *m_name;
142
} REGNAME;
143
 
144
extern  const   REGNAME *bregs;
145
extern  const   int     NREGS;
146
// #define      NREGS   (sizeof(bregs)/sizeof(bregs[0]))
147
 
148
extern  unsigned        addrdecode(const char *v);
149
extern  const   char *addrname(const unsigned v);
150
 
151
// #include "ttybus.h"
152
// #include "portbus.h"
153
// #include "deppbus.h"
154
 
155
// typedef      DEPPBUS FPGA;
156 11 dgisselq
#include "ttybus.h"
157
typedef TTYBUS  FPGA;
158 8 dgisselq
 
159
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.