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[/] [s6soc/] [trunk/] [sw/] [zipos/] [resetdump.s] - Blame information for rev 27

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Line No. Rev Author Line
1 22 dgisselq
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//
2
;;
3
;; Filename:    resetdump.s
4
;;
5
;; Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6
;;
7
;; Purpose:     While most of my ZipCPU programs to date have started with a
8
;;              simple assembly script to load the stack and call the program
9
;;      entry point, this is different.  This is a very complicated startup
10
;;      script designed to dump all of the internal information to the CPU
11
;;      to a UART output port.  This is on purpose.  Indeed, this may be my
12
;;      only means of debugging the device once it goes bad:
13
;;
14
;;      - To set a breakpoint
15
;;              at the location desired call kpanic(), the CPU will dump its
16
;;                      variables and restart.
17
;;              sometime before the desired clock, set the watchdog timer
18
;;                      (currently TIMER_B).  When the watchdog expires,
19
;;                      the CPU will restart.  Adjusting the watchdog will
20
;;                      adjust how long the CPU waits before restarting, and
21
;;                      may also adjust what instructions you find going on
22
;;
23
;;      - In hardware, you can set the scope.  On boot up, this resetdump
24
;;              startup will dump the value of the scope to the UART.
25
;;
26
;;      Of course, this all depends upon someone listening on the uart.  That's
27
;;      the purpose of the dumpuart.cpp program in the sw/host directory.
28
;;      That file will capture the dump so it can be examined later.
29
;;
30
;; Creator:     Dan Gisselquist, Ph.D.
31
;;              Gisselquist Technology, LLC
32
;;
33
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//
34
;;
35
;; Copyright (C) 2015-2016, Gisselquist Technology, LLC
36
;;
37
;; This program is free software (firmware): you can redistribute it and/or
38
;; modify it under the terms of  the GNU General Public License as published
39
;; by the Free Software Foundation, either version 3 of the License, or (at
40
;; your option) any later version.
41
;;
42
;; This program is distributed in the hope that it will be useful, but WITHOUT
43
;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
44
;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
45
;; for more details.
46
;;
47
;; You should have received a copy of the GNU General Public License along
48
;; with this program.  (It's in the $(ROOT)/doc directory, run make with no
49
;; target there if the PDF file isn't present.)  If not, see
50
;; <http://www.gnu.org/licenses/> for a copy.
51
;;
52
;; License:     GPL, v3, as defined and found on www.gnu.org,
53
;;              http://www.gnu.org/licenses/gpl.html
54
;;
55
;;
56
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//
57
;;
58
;;
59
        .section        .start
60
        .global         _start
61
        .type           _start,@function
62
_start:
63
; Upon reset, we must output our registers to the UART, lest we reset because
64
; of a crash
65
        STO     R0,(DBG)
66
        MOV     PC+1,R0
67
        BRA     internal_kpanic
68
        LDI     _top_of_stack,SP
69 27 dgisselq
        LDI     kernel_entry,R0
70
        BRA     bootloader
71 22 dgisselq
 
72
        .global         kpanic
73
        .type           kpanic,@function
74
kpanic:
75
        STO     R0,(DBG)
76
        STO     R1,1(DBG)
77
        STO     R2,2(DBG)
78
        LDI     'P',R1
79
        MOV     PC+1,R0
80
        JMP     raw_put_uart
81
        LDI     'a',R1
82
        MOV     PC+1,R0
83
        JMP     raw_put_uart
84
        LDI     'n',R1
85
        MOV     PC+1,R0
86
        JMP     raw_put_uart
87
        LDI     'i',R1
88
        MOV     PC+1,R0
89
        JMP     raw_put_uart
90
        LDI     'c',R1
91
        MOV     PC+1,R0
92
        JMP     raw_put_uart
93
        LDI     ':',R1
94
        MOV     PC+1,R0
95
        JMP     raw_put_uart
96
        LDI     ' ',R1
97
        MOV     PC+1,R0
98
        JMP     raw_put_uart
99
        LDI     '\r',R1
100
        MOV     PC+1,R0
101
        JMP     raw_put_uart
102
        LDI     '\n',R1
103
        MOV     PC+1,R0
104
        JMP     raw_put_uart
105
        LOD     1(DBG),R1
106
        LOD     2(DBG),R2
107
        MOV     PC+1,R0
108
        JMP     internal_kpanic
109 27 dgisselq
kpanic_wait_for_button_release:
110
        LOD     (SPIO),R0
111
        TEST    0x010,R0
112
        BNZ     kpanic_wait_for_button_release
113
kpanic_wait_for_button:
114
        LOD     (SPIO),R0
115
        TEST    0x010,R0
116
        BZ      kpanic_wait_for_button
117
        BRA     _start
118 22 dgisselq
        HALT
119
 
120
internal_kpanic:
121
        STO     R1,1(DBG)
122
        STO     R2,2(DBG)
123
        STO     R0,3(DBG)       ; Our return address
124
 
125
        ; R0
126
        LDI     0,R1
127
        LOD     (DBG),R2
128
        MOV     .Lcall0(PC),R0
129
        JMP     uart_put_reg_value
130
.Lcall0:
131
 
132
        ; R1
133
        LDI     1,R1
134
        LOD     1(DBG),R2
135
        MOV     .Lcall1(PC),R0
136
        JMP     uart_put_reg_value
137
.Lcall1:
138
        ; R2
139
        LDI     2,R1
140
        LOD     2(DBG),R2
141
        MOV     PC+1,R0
142
        JMP     uart_put_reg_value
143
        ; R3
144
        LDI     3,R1
145
        MOV     R3,R2
146
        MOV     PC+1,R0
147
        JMP     uart_put_reg_value
148
 
149
        ; R4
150
        LDI     4,R1
151
        MOV     R4,R2
152
        MOV     PC+1,R0
153
        JMP     uart_put_reg_value
154
 
155
        ; R5
156
        LDI     5,R1
157
        MOV     R5,R2
158
        MOV     PC+1,R0
159
        JMP     uart_put_reg_value
160
 
161
        ; R6
162
        LDI     6,R1
163
        MOV     R6,R2
164
        MOV     PC+1,R0
165
        JMP     uart_put_reg_value
166
 
167
        ; R7
168
        LDI     7,R1
169
        MOV     R7,R2
170
        MOV     PC+1,R0
171
        JMP     uart_put_reg_value
172
 
173
        ; R8
174
        LDI     8,R1
175
        MOV     R8,R2
176
        MOV     PC+1,R0
177
        JMP     uart_put_reg_value
178
 
179
        ; R9
180
        LDI     9,R1
181
        MOV     R9,R2
182
        MOV     PC+1,R0
183
        JMP     uart_put_reg_value
184
 
185
        ; R10
186
        LDI     10,R1
187
        MOV     R10,R2
188
        MOV     PC+1,R0
189
        JMP     uart_put_reg_value
190
 
191
        ; R11
192
        LDI     11,R1
193
        MOV     R11,R2
194
        MOV     PC+1,R0
195
        JMP     uart_put_reg_value
196
 
197
        ; R12
198
        LDI     12,R1
199
        MOV     R12,R2
200
        MOV     PC+1,R0
201
        JMP     uart_put_reg_value
202
 
203
        ; SP
204
        LDI     13,R1
205
        MOV     R13,R2
206
        MOV     PC+1,R0
207
        JMP     uart_put_reg_value
208
 
209
        ; uR0
210
        LDI     16,R1
211
        MOV     uR0,R2
212
        MOV     PC+1,R0
213
        JMP     uart_put_reg_value
214
 
215
        ; uR1
216
        LDI     17,R1
217
        MOV     uR1,R2
218
        MOV     PC+1,R0
219
        JMP     uart_put_reg_value
220
 
221
        LDI     18,R1
222
        MOV     uR2,R2
223
        MOV     PC+1,R0
224
        JMP     uart_put_reg_value
225
 
226
        LDI     19,R1
227
        MOV     uR3,R2
228
        MOV     PC+1,R0
229
        JMP     uart_put_reg_value
230
 
231
        LDI     20,R1
232
        MOV     uR4,R2
233
        MOV     PC+1,R0
234
        JMP     uart_put_reg_value
235
 
236
        LDI     21,R1
237
        MOV     uR5,R2
238
        MOV     PC+1,R0
239
        JMP     uart_put_reg_value
240
 
241
        LDI     22,R1
242
        MOV     uR6,R2
243
        MOV     PC+1,R0
244
        JMP     uart_put_reg_value
245
 
246
        LDI     23,R1
247
        MOV     uR7,R2
248
        MOV     PC+1,R0
249
        JMP     uart_put_reg_value
250
 
251
        LDI     24,R1
252
        MOV     uR8,R2
253
        MOV     PC+1,R0
254
        JMP     uart_put_reg_value
255
 
256
        LDI     25,R1
257
        MOV     uR9,R2
258
        MOV     PC+1,R0
259
        JMP     uart_put_reg_value
260
 
261
        LDI     26,R1
262
        MOV     uR10,R2
263
        MOV     PC+1,R0
264
        JMP     uart_put_reg_value
265
 
266
        LDI     27,R1
267
        MOV     uR11,R2
268
        MOV     PC+1,R0
269
        JMP     uart_put_reg_value
270
 
271
        LDI     28,R1
272
        MOV     uR12,R2
273
        MOV     PC+1,R0
274
        JMP     uart_put_reg_value
275
 
276
        ; uSP
277
        LDI     29,R1
278
        MOV     uSP,R2
279
        MOV     PC+1,R0
280
        JMP     uart_put_reg_value
281
 
282
        ; uCC
283
        LDI     30,R1
284
        MOV     uCC,R2
285
        MOV     PC+1,R0
286
        JMP     uart_put_reg_value
287
 
288
        ; uPC
289
        LDI     31,R1
290
        MOV     uPC,R2
291
        MOV     PC+1,R0
292
        JMP     uart_put_reg_value
293
 
294
;stack_mem_dump:
295
        ;LDI    0,R4
296
        ;LDI    _top_of_stack,R5
297
;stack_mem_dump_loop:
298
        ;MOV    R4,R1
299
        ;LOD    (R5),R2
300
        ;MOV    PC+1,R0
301
        ;JMP    uart_put_stack_value
302
        ;ADD    1,R4
303
        ;SUB    1,R5
304
        ;CMP    64,R4
305
        ;BLT    stack_mem_dump_loop
306
 
307
; Get prepared for a proper start by setting our stack register
308
        LDI     _top_of_stack,SP
309
 
310
        BRA     dump_scope
311
        ; BRA   end_internal_panic
312
 
313
; Now, do a full dump of all memory--all registers are available to us
314
dump_memory:
315
        LDI     RAM,R5
316
        LDI     0x1000,R6
317
        LDI     0x0f8,R7
318
        STO     R7,(SPIO)
319
full_mem_dump_loop:
320
        MOV     R5,R1
321
        LOD     (R5),R2
322
        MOV     PC+1,R0
323
        JMP     uart_dump_mem_value
324
        LDI     0x0f2,R7
325
        STO     R7,(SPIO)
326
 
327
        ADD     1,R5
328
        SUB     1,R6
329
        BGT     full_mem_dump_loop
330
 
331
        LDI     0x0f5,R7
332
        STO     R7,(SPIO)
333
 
334
dump_scope:
335
; Finally, do a full dump of the scope--if it had triggered
336
;   First, dump the scope control word
337
        LDI     SCOPE,R7        ; R7 = Debugging scope address
338
        MOV     R7,R1
339
        LOD     (R7),R2
340
        MOV     R2,R5           ; R5 will not be changed by a subroutine
341
        MOV     PC+1,R0
342
        BRA     uart_dump_mem_value
343
;   Then test whether or not the scope has stopped
344
        LDI     0x40000000,R1
345
        TEST    R1,R5
346
;   If not, start our kernel.
347
        BZ      dump_buserr
348
;   Otherwise, calculate the size of the scope
349
        LSR     20,R5
350
        AND     0x1f,R5
351
        LDI     1,R6
352
        LSL     R5,R6
353
;   And start dumping
354
        ADD     1,R7    ; Get the scope data address
355
dump_scope_loop:
356
        MOV     R7,R1
357
        LOD     (R7),R2
358
        MOV     PC+1,R0
359
        BRA     uart_dump_mem_value
360
        SUB     1,R6
361
        BGT     dump_scope_loop
362
 
363
dump_buserr:
364
; Dump a bus error address, if used
365
        LDI     'B',R1
366
        MOV     PC+1,R0
367
        BRA     raw_put_uart
368
        LDI     'u',R1
369
        MOV     PC+1,R0
370
        BRA     raw_put_uart
371
        LDI     's',R1
372
        MOV     PC+1,R0
373
        BRA     raw_put_uart
374
        LDI     'E',R1
375
        MOV     PC+1,R0
376
        BRA     raw_put_uart
377
        LDI     'r',R1
378
        MOV     PC+1,R0
379
        BRA     raw_put_uart
380
        LDI     'r',R1
381
        MOV     PC+1,R0
382
        BRA     raw_put_uart
383
        LDI     ':',R1
384
        MOV     PC+1,R0
385
        BRA     raw_put_uart
386
        LDI     ' ',R1
387
        MOV     PC+1,R0
388
        BRA     raw_put_uart
389
        LDI     BUSERR,R1
390
        LOD     (R1),R2
391
        MOV     PC+1,R0
392
        BRA     uart_dump_mem_value
393
 
394
end_internal_panic:
395
        LDI     '\r',R1
396
        MOV     PC+1,R0
397
        BRA     raw_put_uart
398
        LDI     '\n',R1
399
        MOV     PC+1,R0
400
        BRA     raw_put_uart
401
        LDI     '\r',R1
402
        MOV     PC+1,R0
403
        BRA     raw_put_uart
404
        LDI     '\n',R1
405
        MOV     PC+1,R0
406
        BRA     raw_put_uart
407
        LDI     0x0ff,R7
408
        STO     R7,(SPIO)
409
        LOD     3(DBG),PC
410
        JMP     R0
411
 
412
; R0 is return address
413
; R1 is register ID
414
; R2 is register to output
415
uart_put_reg_value:
416
        STO     R0,4(DBG)
417
        STO     R2,5(DBG)
418
        STO     R3,6(DBG)
419
        MOV     R1,R2
420
        LDI     'u',R1
421
        CMP     16,R2
422
        LDILO.LT 's',R1
423
        SUB.GE  16,R2
424
        MOV     PC+1,R0
425
        JMP     raw_put_uart
426
        LDI     '0',R1
427
        CMP     10,R2
428
        LDILO.GE '1',R1
429
        SUB.GE  10,R2
430
        MOV     PC+1,R0
431
        JMP     raw_put_uart
432
        MOV     R2,R1
433
        AND     15,R1
434
        MOV     PC+1,R0
435
        JMP     get_hex
436
        MOV     PC+1,R0
437
        JMP     raw_put_uart
438
        LDI     58,R1   ; A ':'
439
        MOV     PC+1,R0
440
        JMP     raw_put_uart
441
        LOD     5(DBG),R2
442
        LDI     8,R3
443
uart_put_loop:
444
        ROL     4,R2
445
        MOV     R2,R1
446
        AND     15,R1
447
        MOV     PC+1,R0
448
        JMP     get_hex
449
        MOV     PC+1,R0
450
        JMP     raw_put_uart
451
        SUB     1,R3
452
        BNZ     uart_put_loop
453
        LDI     '\r',R1
454
        MOV     PC+1,R0
455
        JMP     raw_put_uart
456
        LDI     '\n',R1
457
        MOV     PC+1,R0
458
        JMP     raw_put_uart
459
        LOD     4(DBG),R0
460
        LOD     5(DBG),R2
461
        LOD     6(DBG),R3
462
        JMP     R0
463
 
464
uart_dump_mem_value:
465
;       R0 = return address
466
;       R1 = Memory address
467
;       R2 = Memory Value
468
; Local: R3 = working value
469
        STO     R0,7(DBG)
470
        MOV     R1,R3           ; R3 = Memory address
471
        MOV     R2,R4           ; R4 = Memory Value
472
        LDI     77,R1           ; 77 = 'M'
473
        MOV     PC+1,R0
474
        JMP     raw_put_uart
475
        LDI     91,R1           ; 91 = '['
476
        MOV     PC+1,R0
477
        JMP     raw_put_uart
478
        LDI     48,R1           ; A '0'
479
        MOV     PC+1,R0
480
        JMP     raw_put_uart
481
        LDI     120,R1          ; An 'x'
482
        MOV     PC+1,R0
483
        JMP     raw_put_uart
484
        ; Set up a loop to dump things
485
        ROL     16,R3           ; Ignore the first 16 bits
486
        LDI     4,R2            ; We're going to do four hex digits here
487
        ;
488
uart_put_mem_address_loop:
489
        ROL     4,R3
490
        MOV     R3,R1
491
        AND     15,R1
492
        MOV     PC+1,R0
493
        JMP     get_hex
494
        MOV     PC+1,R0
495
        JMP     raw_put_uart
496
        SUB     1,R2
497
        BNZ     uart_put_mem_address_loop
498
        ; Put some transition characters
499
        LDI     93,R1           ; 93 = ']'
500
        MOV     PC+1,R0
501
        JMP     raw_put_uart
502
        LDI     58, R1          ; A semicolon
503
        MOV     PC+1,R0
504
        JMP     raw_put_uart
505
        LDI     32, R1          ; A space
506
        MOV     PC+1,R0
507
        JMP     raw_put_uart
508
 
509
        ; Set up a loop to dump the memory value now
510
        LDI     8,R2
511
uart_put_mem_value_loop:
512
        ROL     4,R4
513
        MOV     R4,R1
514
        AND     15,R1
515
        MOV     PC+1,R0
516
        JMP     get_hex
517
        MOV     PC+1,R0
518
        JMP     raw_put_uart
519
        SUB     1,R2
520
        BNZ     uart_put_mem_value_loop
521
        ; Clear the line
522
        LDI     '\r', R1
523
        MOV     PC+1,R0
524
        JMP     raw_put_uart
525
        LDI     '\n', R1
526
        MOV     PC+1,R0
527
        JMP     raw_put_uart
528
        ; And return from our subroutine
529
        LOD     7(DBG),R0
530
        JMP     R0
531
 
532
get_hex:
533
        ADD     0x30,R1
534
        CMP     0x39,R1
535
        ADD.GT  7,R1    ; Add 'A'-'0'-10
536
        JMP     R0
537
 
538
raw_put_uart:   ; R0 is return address, R1 is value to transmit
539
        STO     R2,8(DBG)
540
        LDI     INT_UARTTX,R2
541
        STO     R2,(PIC)        ; Clear the PIC, turn off interrupts, etc.
542
raw_put_uart_retest:
543
        LOD     (PIC),R2
544
        TEST    INT_UARTTX,R2
545
        BZ      raw_put_uart_retest
546
        STO     R1,(UART)
547
        LOD     8(DBG),R2
548
        JMP     R0
549
 
550
        .section        .fixdata
551
DBG:
552
.byte   0,0,0,0,0,0,0,0,0
553
 
554
.set    INT_UARTRX, 0x040
555
.set    INT_UARTTX, 0x080
556
.set    PIC,     0x0100
557
.set    BUSERR,  0x0101
558
.set    TMRA,    0x0102
559
.set    TMRB,    0x0103
560
.set    PWM,     0x0104
561
.set    SPIO,    0x0105
562
.set    GPIO,    0x0106
563
.set    UART,    0x0107
564
.set    VERSION, 0x0108
565
.set    SCOPE,   0x0200
566
.set    SCOPED,  0x0201
567
.set    CLOCK,   0x0800
568
.set    CONFIG,  0x0400
569
.set    TIMER,   0x0801
570
.set    STOPWATCH,0x802
571
.set    ALARM,   0x0803
572
.set    RAM,     0x2000

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