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[/] [s80186/] [trunk/] [fpga/] [common/] [VirtualJTAG.sv] - Blame information for rev 2

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1 2 jamieiles
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86.  If not, see .
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module VirtualJTAG(input logic [1:0] ir_out,
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                   input logic tdo,
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                   output logic [1:0] ir_in,
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                   output logic tck,
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                   output logic tdi,
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                   output logic virtual_state_cdr,
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                   output logic virtual_state_cir,
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                   output logic virtual_state_e1dr,
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                   output logic virtual_state_e2dr,
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                   output logic virtual_state_pdr,
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                   output logic virtual_state_sdr,
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                   output logic virtual_state_udr,
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                   output logic virtual_state_uir);
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sld_virtual_jtag        #(.sld_auto_instance_index("YES"),
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                          .sld_instance_index(0),
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                          .sld_ir_width(2),
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                          .sld_sim_action(""),
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                          .sld_sim_n_scan(0),
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                          .sld_sim_total_length(0))
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                        sld_virtual_jtag_component(.ir_out(ir_out),
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                                                   .tdo(tdo),
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                                                   .ir_in(ir_in),
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                                                   .tck(tck),
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                                                   .tdi(tdi),
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                                                   .virtual_state_cdr(virtual_state_cdr),
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                                                   .virtual_state_cir(virtual_state_cir),
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                                                   .virtual_state_e1dr(virtual_state_e1dr),
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                                                   .virtual_state_e2dr(virtual_state_e2dr),
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                                                   .virtual_state_pdr(virtual_state_pdr),
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                                                   .virtual_state_sdr(virtual_state_sdr),
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                                                   .virtual_state_udr(virtual_state_udr),
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                                                   .virtual_state_uir(virtual_state_uir),
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                                                   .jtag_state_cdr(),
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                                                   .jtag_state_cir(),
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                                                   .jtag_state_e1dr(),
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                                                   .jtag_state_e1ir(),
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                                                   .jtag_state_e2dr(),
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                                                   .jtag_state_e2ir(),
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                                                   .jtag_state_pdr(),
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                                                   .jtag_state_pir(),
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                                                   .jtag_state_rti(),
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                                                   .jtag_state_sdr(),
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                                                   .jtag_state_sdrs(),
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                                                   .jtag_state_sir(),
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                                                   .jtag_state_sirs(),
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                                                   .jtag_state_tlr(),
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                                                   .jtag_state_udr(),
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                                                   .jtag_state_uir(),
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                                                   .tms());
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endmodule

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