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[/] [s80186/] [trunk/] [fpga/] [uart/] [BaudRateGen.sv] - Blame information for rev 2

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1 2 jamieiles
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86.  If not, see .
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module BaudRateGen #(parameter clk_freq = 50000000)
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                    (input logic clk,
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                     input logic reset,
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                     output logic rxclk_en,
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                     output logic txclk_en);
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localparam RX_ACC_MAX = clk_freq / (115200 * 16);
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localparam TX_ACC_MAX = clk_freq / 115200;
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localparam RX_ACC_WIDTH = $clog2(RX_ACC_MAX);
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localparam TX_ACC_WIDTH = $clog2(TX_ACC_MAX);
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reg [RX_ACC_WIDTH - 1:0] rx_acc = 0;
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reg [TX_ACC_WIDTH - 1:0] tx_acc = 0;
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assign rxclk_en = (rx_acc == 5'd0);
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assign txclk_en = (tx_acc == 9'd0);
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always_ff @(posedge clk or posedge reset) begin
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    if (reset) begin
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        rx_acc <= {RX_ACC_WIDTH{1'b0}};
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    end else begin
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        if (rx_acc == RX_ACC_MAX[RX_ACC_WIDTH - 1:0])
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            rx_acc <= {RX_ACC_WIDTH{1'b0}};
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        else
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            rx_acc <= rx_acc + 1'b1;
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    end
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end
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always_ff @(posedge clk or posedge reset) begin
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    if (reset) begin
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        tx_acc <= {TX_ACC_WIDTH{1'b0}};
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    end else begin
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        if (tx_acc == TX_ACC_MAX[TX_ACC_WIDTH - 1:0])
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            tx_acc <= {TX_ACC_WIDTH{1'b0}};
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        else
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            tx_acc <= tx_acc + 1'b1;
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    end
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end
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endmodule

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