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jamieiles |
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see .
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// Multiplexed inc/dec
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.at 0xfe;
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width W8, modrm_start, mar_write, mar_wr_sel EA,
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jmp_dispatch_reg dispatch_fe;
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.auto_address;
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dispatch_fe:
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width W8, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem inc_fe_reg; // reg == 0
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width W8, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem dec_fe_reg; // reg == 1
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next_instruction; // reg == 2
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next_instruction; // reg == 3
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next_instruction; // reg == 4
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next_instruction; // reg == 5
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next_instruction; // reg == 6
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jmp invalid_opcode; // reg == 7
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inc_fe_reg:
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a_sel RA, b_sel IMMEDIATE, immediate 0x1, alu_op ADD,
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rd_sel_source MODRM_RM_REG, update_flags OF SF ZF AF PF,
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width WAUTO, next_instruction;
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inc_fe_mem:
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width WAUTO, segment DS, mem_read;
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a_sel MDR, b_sel IMMEDIATE, immediate 0x1, alu_op ADD,
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mdr_write, update_flags OF SF ZF AF PF, width WAUTO, segment DS,
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jmp write_complete;
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dec_fe_reg:
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a_sel RA, b_sel IMMEDIATE, immediate 0x1, alu_op SUB,
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rd_sel_source MODRM_RM_REG, update_flags OF SF ZF AF PF,
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width WAUTO, next_instruction;
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dec_fe_mem:
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width WAUTO, segment DS, mem_read;
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a_sel MDR, b_sel IMMEDIATE, immediate 0x1, alu_op SUB,
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mdr_write, update_flags OF SF ZF AF PF, width WAUTO, segment DS,
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jmp write_complete;
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#define INC_REG(opcode, reg) \
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.at opcode; \
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ra_sel reg, jmp inc ## reg; \
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inc ## reg: \
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a_sel RA, b_sel IMMEDIATE, immediate 0x1, alu_op ADD, \
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rd_sel_source MICROCODE_RD_SEL, rd_sel reg, \
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update_flags OF SF ZF AF PF, next_instruction;
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#define DEC_REG(opcode, reg) \
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.at opcode; \
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ra_sel reg, jmp dec ## reg; \
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dec ## reg: \
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a_sel RA, b_sel IMMEDIATE, immediate 0x1, alu_op SUB, \
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rd_sel_source MICROCODE_RD_SEL, rd_sel reg, \
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update_flags OF SF ZF AF PF, next_instruction;
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INC_REG(0x40, AX)
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INC_REG(0x41, CX)
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INC_REG(0x42, DX)
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INC_REG(0x43, BX)
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INC_REG(0x44, SP)
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INC_REG(0x45, BP)
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INC_REG(0x46, SI)
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INC_REG(0x47, DI)
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DEC_REG(0x48, AX)
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DEC_REG(0x49, CX)
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DEC_REG(0x4a, DX)
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DEC_REG(0x4b, BX)
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DEC_REG(0x4c, SP)
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DEC_REG(0x4d, BP)
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DEC_REG(0x4e, SI)
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DEC_REG(0x4f, DI)
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