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[/] [s80186/] [trunk/] [rtl/] [microcode/] [shift.us] - Blame information for rev 2

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1 2 jamieiles
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86.  If not, see .
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#define SHIFT1(alu_func, flags)                                                 \
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.auto_address;                                                                  \
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alu_func ## d0_d1_reg:                                                          \
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    a_sel RA, b_sel IMMEDIATE, immediate 0x1, alu_op alu_func,                  \
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        rd_sel_source MODRM_RM_REG, update_flags flags,                         \
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        width WAUTO, next_instruction;                               \
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alu_func ## d0_d1_mem:                                                          \
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    segment DS, mem_read, width WAUTO;                                          \
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    width WAUTO, a_sel MDR, b_sel IMMEDIATE, immediate 0x1, alu_op alu_func,    \
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        mdr_write, update_flags flags, segment DS, jmp write_complete;
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// Variable shifts first write the number of shifts into the temporary
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// register, then when processing, the ALU will perform a subtraction of the
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// count (which is an input to the ALU), and output the decremented value
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// along with a single bit-shifted value, stalling until complete.  The
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// temporary register needs to be written each cycle, as does the result.
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#define SHIFTN(alu_func, flags)                                                 \
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alu_func ## d2_d3:                                                              \
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    ra_modrm_rm_reg, b_sel RB, alu_op SELB, tmp_wr_en, width WAUTO,             \
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        segment DS, jmp_rm_reg_mem alu_func ## d2_d3_reg;                       \
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alu_func ## d2_d3_reg:                                                          \
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    a_sel RA, b_sel RB, alu_op alu_func, rd_sel_source MODRM_RM_REG,            \
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        update_flags flags, width WAUTO, tmp_wr_sel Q_HIGH,             \
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        tmp_wr_en, next_instruction, ra_modrm_rm_reg;                           \
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alu_func ## d2_d3_mem:                                                          \
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    segment DS, mem_read, width WAUTO, rb_cl;                                   \
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    width WAUTO, a_sel MDR, b_sel RB, alu_op alu_func, mdr_write,               \
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        update_flags flags, segment DS, tmp_wr_sel Q_HIGH, tmp_wr_en,           \
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        jmp write_complete;
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#define SHIFTN_IMM8(alu_func, flags)                                            \
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alu_func ## c0_reg:                                                             \
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    a_sel RA, b_sel IMMEDIATE, alu_op alu_func, rd_sel_source MODRM_RM_REG,     \
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        update_flags flags, width WAUTO, tmp_wr_sel Q_HIGH,             \
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        tmp_wr_en, next_instruction, ra_modrm_rm_reg;                           \
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alu_func ## c0_mem:                                                             \
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    segment DS, mem_read, width WAUTO;                                          \
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    width WAUTO, a_sel MDR, b_sel IMMEDIATE, alu_op alu_func, mdr_write,        \
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        update_flags flags, segment DS, tmp_wr_sel Q_HIGH, tmp_wr_en,           \
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        jmp write_complete;
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#define SHIFTN_IMM16(alu_func, flags)                                           \
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alu_func ## c1:                                                                 \
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    tmp_wr_en, alu_op SELB, b_sel IMMEDIATE, ra_modrm_rm_reg, segment DS,       \
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        jmp_rm_reg_mem alu_func ## c0_reg;

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