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[/] [s80186/] [trunk/] [tests/] [instructions/] [TestInt.cpp] - Blame information for rev 2

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// Copyright Jamie Iles, 2017
//
// This file is part of s80x86.
//
// s80x86 is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// s80x86 is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with s80x86.  If not, see <http://www.gnu.org/licenses/>.
 
#include <gtest/gtest.h>
 
#include "EmulateFixture.h"
#include "Flags.h"
 
// flags
// cs
// ip
TEST_F(EmulateFixture, Int3)
{
    write_mem16(VEC_INT + 2, 0x8000, CS); // CS
    write_mem16(VEC_INT + 0, 0x0100, CS); // IP
 
    // int 3
    write_reg(SP, 0x100);
    write_reg(CS, 0x7c00);
    write_reg(IP, 0x0001);
    write_flags(CF | IF);
 
    set_instruction({0xcc});
    emulate();
 
    ASSERT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS | CF);
    ASSERT_EQ(read_reg(CS), 0x8000);
    ASSERT_EQ(read_reg(IP), 0x0100);
    ASSERT_EQ(read_reg(SP), 0x0100 - 6);
 
    ASSERT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS | CF | IF);
    ASSERT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);
    // Return to the following instruction
    ASSERT_EQ(read_mem16(0x100 - 6, SS), 0x0002);
}
 
TEST_F(EmulateFixture, IntN)
{
    write_mem16(VEC_INT + 2, 0x8000, CS); // CS
    write_mem16(VEC_INT + 0, 0x0100, CS); // IP
 
    // int 3
    write_reg(SP, 0x100);
    write_reg(CS, 0x7c00);
    write_reg(IP, 0x0001);
    write_flags(CF | IF);
 
    set_instruction({0xcd, 0x03});
    emulate();
 
    EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS | CF);
    EXPECT_EQ(read_reg(CS), 0x8000);
    EXPECT_EQ(read_reg(IP), 0x0100);
    EXPECT_EQ(read_reg(SP), 0x0100 - 6);
 
    EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS | CF | IF);
    EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);
    // Return to the following instruction
    EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0003);
}
 
TEST_F(EmulateFixture, IntoNotTaken)
{
    // int 3
    write_reg(SP, 0x100);
    write_reg(CS, 0x7c00);
    write_reg(IP, 0x0001);
    write_flags(CF | IF);
 
    set_instruction({0xce});
    emulate();
 
    ASSERT_EQ(read_reg(IP), 0x0002);
    ASSERT_EQ(read_reg(SP), 0x0100);
}
 
TEST_F(EmulateFixture, IntoTaken)
{
    write_mem16(VEC_OVERFLOW + 2, 0x8000, CS); // CS
    write_mem16(VEC_OVERFLOW + 0, 0x0100, CS); // IP
 
    // int 3
    write_reg(SP, 0x100);
    write_reg(CS, 0x7c00);
    write_reg(IP, 0x0001);
    write_flags(CF | IF | OF);
 
    set_instruction({0xce});
    emulate();
 
    ASSERT_PRED_FORMAT2(AssertFlagsEqual, read_flags(),
                        FLAGS_STUCK_BITS | CF | OF);
    ASSERT_EQ(read_reg(CS), 0x8000);
    ASSERT_EQ(read_reg(IP), 0x0100);
    ASSERT_EQ(read_reg(SP), 0x0100 - 6);
 
    ASSERT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS | CF | IF | OF);
    ASSERT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);
    // Return to the following instruction
    ASSERT_EQ(read_mem16(0x100 - 6, SS), 0x0002);
}
 
TEST_F(EmulateFixture, NMITaken)
{
    write_mem16(VEC_NMI + 2, 0x8000, CS); // CS
    write_mem16(VEC_NMI + 0, 0x0100, CS); // IP
 
    write_reg(SP, 0x100);
    write_reg(CS, 0x7c00);
    write_reg(IP, 0x0001);
 
    write_flags(IF);
 
    set_instruction({});
    raise_nmi();
    emulate();
 
    EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);
    EXPECT_EQ(read_reg(CS), 0x8000);
    EXPECT_EQ(read_reg(IP), 0x0100);
    EXPECT_EQ(read_reg(SP), 0x0100 - 6);
 
    EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS | IF);
    EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);
    // Return to the instruction that would have been executed next
    EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0001);
}
 
TEST_F(EmulateFixture, IFClearExtIntNotTaken)
{
    write_mem16((9 * 4) + 2, 0x8000, CS); // CS
    write_mem16((9 * 4) + 0, 0x0100, CS); // IP
 
    write_reg(SP, 0x100);
    write_reg(CS, 0x7c00);
    write_reg(IP, 0x0001);
 
    write_flags(0);
 
    set_instruction({0x90});
    raise_irq(1);
    emulate();
 
    EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);
    EXPECT_EQ(read_reg(CS), 0x7c00);
    EXPECT_EQ(read_reg(IP), 0x0002);
}
 
TEST_F(EmulateFixture, IFSetExtIntTaken)
{
    write_io8(0x20, 0x13);
    write_io8(0x21, 0x00);
    write_io8(0x21, 0x01);
    write_io8(0x21, 0x00);
 
    write_mem16((4 * 4) + 2, 0x8000, CS); // CS
    write_mem16((4 * 4) + 0, 0x0100, CS); // IP
 
    write_reg(SP, 0x100);
    write_reg(CS, 0x7c00);
    write_reg(IP, 0x0001);
 
    write_flags(IF);
 
    set_instruction({});
    raise_irq(4);
    emulate();
 
    EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);
    EXPECT_EQ(read_reg(CS), 0x8000);
    EXPECT_EQ(read_reg(IP), 0x0100);
    EXPECT_EQ(read_reg(SP), 0x0100 - 6);
 
    EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS | IF);
    EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);
    // Return to the instruction that would have been executed next
    EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0001);
}
 
TEST_F(EmulateFixture, IFClearNMITaken)
{
    write_mem16(VEC_NMI + 2, 0x8000, CS); // CS
    write_mem16(VEC_NMI + 0, 0x0100, CS); // IP
 
    write_reg(SP, 0x100);
    write_reg(CS, 0x7c00);
    write_reg(IP, 0x0001);
 
    write_flags(0);
 
    set_instruction({});
    raise_nmi();
    emulate();
 
    EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);
    EXPECT_EQ(read_reg(CS), 0x8000);
    EXPECT_EQ(read_reg(IP), 0x0100);
    EXPECT_EQ(read_reg(SP), 0x0100 - 6);
 
    EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS);
    EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);
    // Return to the instruction that would have been executed next
    EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0001);
}
 
TEST_F(EmulateFixture, STIInhibitsInterrupts)
{
    write_mem16(VEC_NMI + 2, 0x8000, CS); // CS
    write_mem16(VEC_NMI + 0, 0x0100, CS); // IP
 
    write_reg(SP, 0x100);
    write_reg(CS, 0x7c00);
    write_reg(IP, 0x0001);
 
    write_flags(IF);
 
    set_instruction({0xfb});
    emulate();
 
    set_instruction({0x90});
    raise_nmi();
    emulate();
 
    EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);
    EXPECT_EQ(read_reg(CS), 0x8000);
    EXPECT_EQ(read_reg(IP), 0x0100);
    EXPECT_EQ(read_reg(SP), 0x0100 - 6);
 
    EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS | IF);
    EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);
    // Return to the instruction that would have been executed next
    EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0003);
}
 
TEST_F(EmulateFixture, MovSRInhibitsInterrupts)
{
    write_mem16(VEC_NMI + 2, 0x8000, CS); // CS
    write_mem16(VEC_NMI + 0, 0x0100, CS); // IP
 
    write_reg(SP, 0x100);
    write_reg(CS, 0x7c00);
    write_reg(IP, 0x0001);
 
    write_flags(IF);
 
    // mov es, ax
    set_instruction({0x8e, 0xc0});
    emulate();
 
    set_instruction({0x90});
    raise_nmi();
    emulate();
 
    EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);
    EXPECT_EQ(read_reg(CS), 0x8000);
    EXPECT_EQ(read_reg(IP), 0x0100);
    EXPECT_EQ(read_reg(SP), 0x0100 - 6);
 
    EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS | IF);
    EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);
    // Return to the instruction that would have been executed next
    EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0004);
}
 
TEST_F(EmulateFixture, PopSRInhibitsInterrupts)
{
    write_mem16(VEC_NMI + 2, 0x8000, CS); // CS
    write_mem16(VEC_NMI + 0, 0x0100, CS); // IP
 
    write_reg(SP, 0x0fe);
    write_reg(CS, 0x7c00);
    write_reg(IP, 0x0001);
 
    write_flags(IF);
 
    // pop es
    set_instruction({0x1f});
    emulate();
 
    set_instruction({0x90});
    raise_nmi();
    emulate();
 
    EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);
    EXPECT_EQ(read_reg(CS), 0x8000);
    EXPECT_EQ(read_reg(IP), 0x0100);
    EXPECT_EQ(read_reg(SP), 0x0100 - 6);
 
    EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS | IF);
    EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);
    // Return to the instruction that would have been executed next
    EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0003);
}
 
TEST_F(EmulateFixture, SingleStepTaken)
{
    write_mem16(VEC_SINGLE_STEP + 2, 0x8000, CS); // CS
    write_mem16(VEC_SINGLE_STEP + 0, 0x0100, CS); // IP
 
    write_reg(SP, 0x100);
    write_reg(CS, 0x7c00);
    write_reg(IP, 0x0001);
 
    write_flags(TF);
 
    set_instruction({0x90});
    emulate();
 
    EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);
    EXPECT_EQ(read_reg(CS), 0x8000);
    EXPECT_EQ(read_reg(IP), 0x0100);
    EXPECT_EQ(read_reg(SP), 0x0100 - 6);
 
    EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS | TF);
    EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);
    // Return to the instruction that would have been executed next
    EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0002);
}

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[/] [s80186/] [trunk/] [tests/] [instructions/] [TestInt.cpp] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jamieiles	`// Copyright Jamie Iles, 2017`
2			`//`
3			`// This file is part of s80x86.`
4			`//`
5			`// s80x86 is free software: you can redistribute it and/or modify`
6			`// it under the terms of the GNU General Public License as published by`
7			`// the Free Software Foundation, either version 3 of the License, or`
8			`// (at your option) any later version.`
9			`//`
10			`// s80x86 is distributed in the hope that it will be useful,`
11			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`// GNU General Public License for more details.`
14			`//`
15			`// You should have received a copy of the GNU General Public License`
16			`// along with s80x86. If not, see <http://www.gnu.org/licenses/>.`
17
18			`#include <gtest/gtest.h>`
19
20			`#include "EmulateFixture.h"`
21			`#include "Flags.h"`
22
23			`// flags`
24			`// cs`
25			`// ip`
26			`TEST_F(EmulateFixture, Int3)`
27			`{`
28			`write_mem16(VEC_INT + 2, 0x8000, CS); // CS`
29			`write_mem16(VEC_INT + 0, 0x0100, CS); // IP`
30
31			`// int 3`
32			`write_reg(SP, 0x100);`
33			`write_reg(CS, 0x7c00);`
34			`write_reg(IP, 0x0001);`
35			`write_flags(CF \| IF);`
36
37			`set_instruction({0xcc});`
38			`emulate();`
39
40			`ASSERT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS \| CF);`
41			`ASSERT_EQ(read_reg(CS), 0x8000);`
42			`ASSERT_EQ(read_reg(IP), 0x0100);`
43			`ASSERT_EQ(read_reg(SP), 0x0100 - 6);`
44
45			`ASSERT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS \| CF \| IF);`
46			`ASSERT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);`
47			`// Return to the following instruction`
48			`ASSERT_EQ(read_mem16(0x100 - 6, SS), 0x0002);`
49			`}`
50
51			`TEST_F(EmulateFixture, IntN)`
52			`{`
53			`write_mem16(VEC_INT + 2, 0x8000, CS); // CS`
54			`write_mem16(VEC_INT + 0, 0x0100, CS); // IP`
55
56			`// int 3`
57			`write_reg(SP, 0x100);`
58			`write_reg(CS, 0x7c00);`
59			`write_reg(IP, 0x0001);`
60			`write_flags(CF \| IF);`
61
62			`set_instruction({0xcd, 0x03});`
63			`emulate();`
64
65			`EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS \| CF);`
66			`EXPECT_EQ(read_reg(CS), 0x8000);`
67			`EXPECT_EQ(read_reg(IP), 0x0100);`
68			`EXPECT_EQ(read_reg(SP), 0x0100 - 6);`
69
70			`EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS \| CF \| IF);`
71			`EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);`
72			`// Return to the following instruction`
73			`EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0003);`
74			`}`
75
76			`TEST_F(EmulateFixture, IntoNotTaken)`
77			`{`
78			`// int 3`
79			`write_reg(SP, 0x100);`
80			`write_reg(CS, 0x7c00);`
81			`write_reg(IP, 0x0001);`
82			`write_flags(CF \| IF);`
83
84			`set_instruction({0xce});`
85			`emulate();`
86
87			`ASSERT_EQ(read_reg(IP), 0x0002);`
88			`ASSERT_EQ(read_reg(SP), 0x0100);`
89			`}`
90
91			`TEST_F(EmulateFixture, IntoTaken)`
92			`{`
93			`write_mem16(VEC_OVERFLOW + 2, 0x8000, CS); // CS`
94			`write_mem16(VEC_OVERFLOW + 0, 0x0100, CS); // IP`
95
96			`// int 3`
97			`write_reg(SP, 0x100);`
98			`write_reg(CS, 0x7c00);`
99			`write_reg(IP, 0x0001);`
100			`write_flags(CF \| IF \| OF);`
101
102			`set_instruction({0xce});`
103			`emulate();`
104
105			`ASSERT_PRED_FORMAT2(AssertFlagsEqual, read_flags(),`
106			`FLAGS_STUCK_BITS \| CF \| OF);`
107			`ASSERT_EQ(read_reg(CS), 0x8000);`
108			`ASSERT_EQ(read_reg(IP), 0x0100);`
109			`ASSERT_EQ(read_reg(SP), 0x0100 - 6);`
110
111			`ASSERT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS \| CF \| IF \| OF);`
112			`ASSERT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);`
113			`// Return to the following instruction`
114			`ASSERT_EQ(read_mem16(0x100 - 6, SS), 0x0002);`
115			`}`
116
117			`TEST_F(EmulateFixture, NMITaken)`
118			`{`
119			`write_mem16(VEC_NMI + 2, 0x8000, CS); // CS`
120			`write_mem16(VEC_NMI + 0, 0x0100, CS); // IP`
121
122			`write_reg(SP, 0x100);`
123			`write_reg(CS, 0x7c00);`
124			`write_reg(IP, 0x0001);`
125
126			`write_flags(IF);`
127
128			`set_instruction({});`
129			`raise_nmi();`
130			`emulate();`
131
132			`EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);`
133			`EXPECT_EQ(read_reg(CS), 0x8000);`
134			`EXPECT_EQ(read_reg(IP), 0x0100);`
135			`EXPECT_EQ(read_reg(SP), 0x0100 - 6);`
136
137			`EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS \| IF);`
138			`EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);`
139			`// Return to the instruction that would have been executed next`
140			`EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0001);`
141			`}`
142
143			`TEST_F(EmulateFixture, IFClearExtIntNotTaken)`
144			`{`
145			`write_mem16((9 * 4) + 2, 0x8000, CS); // CS`
146			`write_mem16((9 * 4) + 0, 0x0100, CS); // IP`
147
148			`write_reg(SP, 0x100);`
149			`write_reg(CS, 0x7c00);`
150			`write_reg(IP, 0x0001);`
151
152			`write_flags(0);`
153
154			`set_instruction({0x90});`
155			`raise_irq(1);`
156			`emulate();`
157
158			`EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);`
159			`EXPECT_EQ(read_reg(CS), 0x7c00);`
160			`EXPECT_EQ(read_reg(IP), 0x0002);`
161			`}`
162
163			`TEST_F(EmulateFixture, IFSetExtIntTaken)`
164			`{`
165			`write_io8(0x20, 0x13);`
166			`write_io8(0x21, 0x00);`
167			`write_io8(0x21, 0x01);`
168			`write_io8(0x21, 0x00);`
169
170			`write_mem16((4 * 4) + 2, 0x8000, CS); // CS`
171			`write_mem16((4 * 4) + 0, 0x0100, CS); // IP`
172
173			`write_reg(SP, 0x100);`
174			`write_reg(CS, 0x7c00);`
175			`write_reg(IP, 0x0001);`
176
177			`write_flags(IF);`
178
179			`set_instruction({});`
180			`raise_irq(4);`
181			`emulate();`
182
183			`EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);`
184			`EXPECT_EQ(read_reg(CS), 0x8000);`
185			`EXPECT_EQ(read_reg(IP), 0x0100);`
186			`EXPECT_EQ(read_reg(SP), 0x0100 - 6);`
187
188			`EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS \| IF);`
189			`EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);`
190			`// Return to the instruction that would have been executed next`
191			`EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0001);`
192			`}`
193
194			`TEST_F(EmulateFixture, IFClearNMITaken)`
195			`{`
196			`write_mem16(VEC_NMI + 2, 0x8000, CS); // CS`
197			`write_mem16(VEC_NMI + 0, 0x0100, CS); // IP`
198
199			`write_reg(SP, 0x100);`
200			`write_reg(CS, 0x7c00);`
201			`write_reg(IP, 0x0001);`
202
203			`write_flags(0);`
204
205			`set_instruction({});`
206			`raise_nmi();`
207			`emulate();`
208
209			`EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);`
210			`EXPECT_EQ(read_reg(CS), 0x8000);`
211			`EXPECT_EQ(read_reg(IP), 0x0100);`
212			`EXPECT_EQ(read_reg(SP), 0x0100 - 6);`
213
214			`EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS);`
215			`EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);`
216			`// Return to the instruction that would have been executed next`
217			`EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0001);`
218			`}`
219
220			`TEST_F(EmulateFixture, STIInhibitsInterrupts)`
221			`{`
222			`write_mem16(VEC_NMI + 2, 0x8000, CS); // CS`
223			`write_mem16(VEC_NMI + 0, 0x0100, CS); // IP`
224
225			`write_reg(SP, 0x100);`
226			`write_reg(CS, 0x7c00);`
227			`write_reg(IP, 0x0001);`
228
229			`write_flags(IF);`
230
231			`set_instruction({0xfb});`
232			`emulate();`
233
234			`set_instruction({0x90});`
235			`raise_nmi();`
236			`emulate();`
237
238			`EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);`
239			`EXPECT_EQ(read_reg(CS), 0x8000);`
240			`EXPECT_EQ(read_reg(IP), 0x0100);`
241			`EXPECT_EQ(read_reg(SP), 0x0100 - 6);`
242
243			`EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS \| IF);`
244			`EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);`
245			`// Return to the instruction that would have been executed next`
246			`EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0003);`
247			`}`
248
249			`TEST_F(EmulateFixture, MovSRInhibitsInterrupts)`
250			`{`
251			`write_mem16(VEC_NMI + 2, 0x8000, CS); // CS`
252			`write_mem16(VEC_NMI + 0, 0x0100, CS); // IP`
253
254			`write_reg(SP, 0x100);`
255			`write_reg(CS, 0x7c00);`
256			`write_reg(IP, 0x0001);`
257
258			`write_flags(IF);`
259
260			`// mov es, ax`
261			`set_instruction({0x8e, 0xc0});`
262			`emulate();`
263
264			`set_instruction({0x90});`
265			`raise_nmi();`
266			`emulate();`
267
268			`EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);`
269			`EXPECT_EQ(read_reg(CS), 0x8000);`
270			`EXPECT_EQ(read_reg(IP), 0x0100);`
271			`EXPECT_EQ(read_reg(SP), 0x0100 - 6);`
272
273			`EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS \| IF);`
274			`EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);`
275			`// Return to the instruction that would have been executed next`
276			`EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0004);`
277			`}`
278
279			`TEST_F(EmulateFixture, PopSRInhibitsInterrupts)`
280			`{`
281			`write_mem16(VEC_NMI + 2, 0x8000, CS); // CS`
282			`write_mem16(VEC_NMI + 0, 0x0100, CS); // IP`
283
284			`write_reg(SP, 0x0fe);`
285			`write_reg(CS, 0x7c00);`
286			`write_reg(IP, 0x0001);`
287
288			`write_flags(IF);`
289
290			`// pop es`
291			`set_instruction({0x1f});`
292			`emulate();`
293
294			`set_instruction({0x90});`
295			`raise_nmi();`
296			`emulate();`
297
298			`EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);`
299			`EXPECT_EQ(read_reg(CS), 0x8000);`
300			`EXPECT_EQ(read_reg(IP), 0x0100);`
301			`EXPECT_EQ(read_reg(SP), 0x0100 - 6);`
302
303			`EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS \| IF);`
304			`EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);`
305			`// Return to the instruction that would have been executed next`
306			`EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0003);`
307			`}`
308
309			`TEST_F(EmulateFixture, SingleStepTaken)`
310			`{`
311			`write_mem16(VEC_SINGLE_STEP + 2, 0x8000, CS); // CS`
312			`write_mem16(VEC_SINGLE_STEP + 0, 0x0100, CS); // IP`
313
314			`write_reg(SP, 0x100);`
315			`write_reg(CS, 0x7c00);`
316			`write_reg(IP, 0x0001);`
317
318			`write_flags(TF);`
319
320			`set_instruction({0x90});`
321			`emulate();`
322
323			`EXPECT_PRED_FORMAT2(AssertFlagsEqual, read_flags(), FLAGS_STUCK_BITS);`
324			`EXPECT_EQ(read_reg(CS), 0x8000);`
325			`EXPECT_EQ(read_reg(IP), 0x0100);`
326			`EXPECT_EQ(read_reg(SP), 0x0100 - 6);`
327
328			`EXPECT_EQ(read_mem16(0x100 - 2, SS), FLAGS_STUCK_BITS \| TF);`
329			`EXPECT_EQ(read_mem16(0x100 - 4, SS), 0x7c00);`
330			`// Return to the instruction that would have been executed next`
331			`EXPECT_EQ(read_mem16(0x100 - 6, SS), 0x0002);`
332			`}`