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[/] [s80186/] [trunk/] [tests/] [rtl/] [TestFifo.cpp] - Blame information for rev 2

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1 2 jamieiles
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86.  If not, see <http://www.gnu.org/licenses/>.
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#include <gtest/gtest.h>
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#include <VFifo.h>
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#include "VerilogTestbench.h"
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class FifoTestFixture : public VerilogTestbench<VFifo>, public ::testing::Test
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{
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public:
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    FifoTestFixture();
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    void push(uint32_t val);
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    bool is_empty() const
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    {
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        return empty;
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    }
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    uint32_t get_head() const
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    {
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        return head;
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    }
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    uint32_t pop();
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private:
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    bool empty;
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    uint32_t head;
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};
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FifoTestFixture::FifoTestFixture() : empty(true), head(0x7777)
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{
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    dut.wr_en = 0;
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    dut.wr_data = 0LU;
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    dut.rd_en = 0;
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    periodic(ClockCapture, [&] {
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        this->empty = this->dut.empty;
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        this->head = this->dut.rd_data;
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    });
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    reset();
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}
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void FifoTestFixture::push(uint32_t val)
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{
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    after_n_cycles(0, [&] {
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        this->dut.wr_data = val;
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        this->dut.wr_en = 1;
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        after_n_cycles(1, [&] { this->dut.wr_en = 0; });
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    });
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    cycle(2);
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}
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uint32_t FifoTestFixture::pop()
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{
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    while (is_empty())
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        cycle();
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    auto v = head;
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    after_n_cycles(0, [&] {
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        this->dut.rd_en = 1;
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        after_n_cycles(1, [&] { this->dut.rd_en = 0; });
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    });
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    cycle(2);
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    return v;
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}
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TEST_F(FifoTestFixture, empty_fifo_not_full)
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{
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    ASSERT_TRUE(dut.empty);
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    ASSERT_FALSE(dut.full);
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}
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TEST_F(FifoTestFixture, one_push_not_empty)
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{
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    ASSERT_TRUE(is_empty());
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    push(0xdeadbeef);
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    cycle();
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    ASSERT_FALSE(is_empty());
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}
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TEST_F(FifoTestFixture, one_push_one_pop)
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{
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    ASSERT_TRUE(dut.empty);
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    ASSERT_EQ(dut.rd_data, 0LU);
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    push(0xdeadbeef);
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    cycle();
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    ASSERT_FALSE(dut.empty);
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    auto v = pop();
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    ASSERT_TRUE(dut.empty);
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    ASSERT_EQ(v, 0xdeadbeef);
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}
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TEST_F(FifoTestFixture, push3pop3)
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{
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    for (uint32_t m = 0; m < 3; ++m)
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        push(m << 16);
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    ASSERT_FALSE(dut.empty);
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    ASSERT_FALSE(dut.full);
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    for (uint32_t m = 0; m < 3; ++m)
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        ASSERT_EQ(pop(), m << 16);
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    ASSERT_TRUE(dut.empty);
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}
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TEST_F(FifoTestFixture, overflow_no_corrupt)
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{
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    for (uint32_t m = 0; m < 8; ++m)
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        push(m);
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    ASSERT_TRUE(dut.full);
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    ASSERT_FALSE(dut.empty);
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    for (uint32_t m = 0; m < 6; ++m)
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        ASSERT_EQ(pop(), m);
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    cycle();
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    ASSERT_TRUE(is_empty());
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    ASSERT_FALSE(dut.full);
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}
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TEST_F(FifoTestFixture, read_during_write)
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{
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    push(0x1234);
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    after_n_cycles(0, [&] {
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        this->dut.wr_en = 1;
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        this->dut.wr_data = 0xaa55;
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        this->dut.rd_en = 1;
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        after_n_cycles(1, [&] {
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            this->dut.wr_en = 0;
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            this->dut.rd_en = 0;
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        });
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    });
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    ASSERT_EQ(pop(), 0x1234LU);
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    ASSERT_EQ(pop(), 0xaa55LU);
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}
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TEST_F(FifoTestFixture, fill_at_threshold)
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{
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    int pushed = 0;
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    for (;;) {
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        push(1);
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        ++pushed;
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        if (dut.nearly_full)
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            break;
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    }
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    ASSERT_EQ(pushed, 4);
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}
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TEST_F(FifoTestFixture, reset_empties)
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{
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    for (uint32_t m = 0; m < 4; ++m)
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        push(m);
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    ASSERT_FALSE(dut.empty);
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    reset();
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    ASSERT_TRUE(dut.empty);
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}

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