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Subversion Repositories sap_1_nanoprogrammed_processor

[/] [sap_1_nanoprogrammed_processor/] [branches/] [M3CPU8_tb.v] - Blame information for rev 5

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`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:37:36 07/31/2022
// Design Name:   M3CPU8
// Module Name:   F:/VIDEO FACTORY/XILINX/SAP_NANOPROGRAMMED/M3CPU8_tb.v
// Project Name:  SAP_NANOPROGRAMMED
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: M3CPU8
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
 
module M3CPU8_tb;
 
        // Inputs
        reg clk;
        reg rst;
 
        // Outputs
        wire [3:0] PC_o;
        wire [3:0] MAR_o;
        wire [8:0] SRAM_o;
        wire [4:0] IR_o_1;
        wire [3:0] IR_o_2;
        wire [3:0] AR_o;
        wire [3:0] PRE_o;
        wire [4:0] ROM_o;
        wire [4:0] NANO_PRE_o;
        wire [16:0] NANO_ROM_o;
        wire EP_o;
        wire CP_o;
        wire LM_o;
        wire CE_o;
        wire LI_o;
        wire EI_o;
        wire CS_o;
        wire LA_o;
        wire EA_o;
        wire SU_o;
        wire AD_o;
        wire EU_o;
        wire LB_o;
        wire LO_o;
        wire LOAD_MICRO_o;
        wire CLEAR_MICRO_o;
        wire INC_MICRO_o;
        wire [8:0] B_out;
        wire [8:0] ALU_out;
        wire [8:0] A_out;
        wire [8:0] OR_out;
 
        // Instantiate the Unit Under Test (UUT)
        M3CPU8 uut (
                .clk(clk),
                .rst(rst),
                .PC_o(PC_o),
                .MAR_o(MAR_o),
                .SRAM_o(SRAM_o),
                .IR_o_1(IR_o_1),
                .IR_o_2(IR_o_2),
                .AR_o(AR_o),
                .PRE_o(PRE_o),
                .ROM_o(ROM_o),
                .NANO_PRE_o(NANO_PRE_o),
                .NANO_ROM_o(NANO_ROM_o),
                .EP_o(EP_o),
                .CP_o(CP_o),
                .LM_o(LM_o),
                .CE_o(CE_o),
                .LI_o(LI_o),
                .EI_o(EI_o),
                .CS_o(CS_o),
                .LA_o(LA_o),
                .EA_o(EA_o),
                .SU_o(SU_o),
                .AD_o(AD_o),
                .EU_o(EU_o),
                .LB_o(LB_o),
                .LO_o(LO_o),
                .LOAD_MICRO_o(LOAD_MICRO_o),
                .CLEAR_MICRO_o(CLEAR_MICRO_o),
                .INC_MICRO_o(INC_MICRO_o),
                .B_out(B_out),
                .ALU_out(ALU_out),
                .A_out(A_out),
                .OR_out(OR_out)
        );
 
        initial begin
                // Start of LDA Nanoroutine
                clk = 0;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 1;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
// End of LDA Nanoroutine
// Start of ADD Nanoroutine
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
// End of ADD Nanoroutine
// Start of SUB Nanoroutine
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
// End of SUB Nanoroutine               
// Start of OUT Nanoroutine
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
 
 
 
 
 
 
 
 
 
        end
 
endmodule
 

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Subversion Repositories sap_1_nanoprogrammed_processor

[/] [sap_1_nanoprogrammed_processor/] [branches/] [M3CPU8_tb.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	sssayeekum	`timescale 1ns / 1ps
2
3			`////////////////////////////////////////////////////////////////////////////////`
4			`// Company:`
5			`// Engineer:`
6			`//`
7			`// Create Date: 14:37:36 07/31/2022`
8			`// Design Name: M3CPU8`
9			`// Module Name: F:/VIDEO FACTORY/XILINX/SAP_NANOPROGRAMMED/M3CPU8_tb.v`
10			`// Project Name: SAP_NANOPROGRAMMED`
11			`// Target Device:`
12			`// Tool versions:`
13			`// Description:`
14			`//`
15			`// Verilog Test Fixture created by ISE for module: M3CPU8`
16			`//`
17			`// Dependencies:`
18			`//`
19			`// Revision:`
20			`// Revision 0.01 - File Created`
21			`// Additional Comments:`
22			`//`
23			`////////////////////////////////////////////////////////////////////////////////`
24
25			`module M3CPU8_tb;`
26
27			`// Inputs`
28			`reg clk;`
29			`reg rst;`
30
31			`// Outputs`
32			`wire [3:0] PC_o;`
33			`wire [3:0] MAR_o;`
34			`wire [8:0] SRAM_o;`
35			`wire [4:0] IR_o_1;`
36			`wire [3:0] IR_o_2;`
37			`wire [3:0] AR_o;`
38			`wire [3:0] PRE_o;`
39			`wire [4:0] ROM_o;`
40			`wire [4:0] NANO_PRE_o;`
41			`wire [16:0] NANO_ROM_o;`
42			`wire EP_o;`
43			`wire CP_o;`
44			`wire LM_o;`
45			`wire CE_o;`
46			`wire LI_o;`
47			`wire EI_o;`
48			`wire CS_o;`
49			`wire LA_o;`
50			`wire EA_o;`
51			`wire SU_o;`
52			`wire AD_o;`
53			`wire EU_o;`
54			`wire LB_o;`
55			`wire LO_o;`
56			`wire LOAD_MICRO_o;`
57			`wire CLEAR_MICRO_o;`
58			`wire INC_MICRO_o;`
59			`wire [8:0] B_out;`
60			`wire [8:0] ALU_out;`
61			`wire [8:0] A_out;`
62			`wire [8:0] OR_out;`
63
64			`// Instantiate the Unit Under Test (UUT)`
65			`M3CPU8 uut (`
66			`.clk(clk),`
67			`.rst(rst),`
68			`.PC_o(PC_o),`
69			`.MAR_o(MAR_o),`
70			`.SRAM_o(SRAM_o),`
71			`.IR_o_1(IR_o_1),`
72			`.IR_o_2(IR_o_2),`
73			`.AR_o(AR_o),`
74			`.PRE_o(PRE_o),`
75			`.ROM_o(ROM_o),`
76			`.NANO_PRE_o(NANO_PRE_o),`
77			`.NANO_ROM_o(NANO_ROM_o),`
78			`.EP_o(EP_o),`
79			`.CP_o(CP_o),`
80			`.LM_o(LM_o),`
81			`.CE_o(CE_o),`
82			`.LI_o(LI_o),`
83			`.EI_o(EI_o),`
84			`.CS_o(CS_o),`
85			`.LA_o(LA_o),`
86			`.EA_o(EA_o),`
87			`.SU_o(SU_o),`
88			`.AD_o(AD_o),`
89			`.EU_o(EU_o),`
90			`.LB_o(LB_o),`
91			`.LO_o(LO_o),`
92			`.LOAD_MICRO_o(LOAD_MICRO_o),`
93			`.CLEAR_MICRO_o(CLEAR_MICRO_o),`
94			`.INC_MICRO_o(INC_MICRO_o),`
95			`.B_out(B_out),`
96			`.ALU_out(ALU_out),`
97			`.A_out(A_out),`
98			`.OR_out(OR_out)`
99			`);`
100
101			`initial begin`
102			`// Start of LDA Nanoroutine`
103			`clk = 0;`
104			`rst = 0;`
105
106			`#50;`
107			`clk = 0;`
108			`rst = 1;`
109
110			`#50;`
111			`clk = 1;`
112			`rst = 0;`
113
114			`#50;`
115			`clk = 0;`
116			`rst = 0;`
117
118			`#50;`
119			`clk = 1;`
120			`rst = 0;`
121
122			`#50;`
123			`clk = 0;`
124			`rst = 0;`
125
126			`#50;`
127			`clk = 1;`
128			`rst = 0;`
129
130			`#50;`
131			`clk = 0;`
132			`rst = 0;`
133
134			`#50;`
135			`clk = 1;`
136			`rst = 0;`
137
138			`#50;`
139			`clk = 0;`
140			`rst = 0;`
141
142			`#50;`
143			`clk = 1;`
144			`rst = 0;`
145
146			`#50;`
147			`clk = 0;`
148			`rst = 0;`
149
150			`#50;`
151			`clk = 1;`
152			`rst = 0;`
153			`// End of LDA Nanoroutine`
154			`// Start of ADD Nanoroutine`
155			`#50;`
156			`clk = 0;`
157			`rst = 0;`
158
159			`#50;`
160			`clk = 1;`
161			`rst = 0;`
162
163			`#50;`
164			`clk = 0;`
165			`rst = 0;`
166
167			`#50;`
168			`clk = 1;`
169			`rst = 0;`
170
171			`#50;`
172			`clk = 0;`
173			`rst = 0;`
174
175			`#50;`
176			`clk = 1;`
177			`rst = 0;`
178
179			`#50;`
180			`clk = 0;`
181			`rst = 0;`
182
183			`#50;`
184			`clk = 1;`
185			`rst = 0;`
186
187			`#50;`
188			`clk = 0;`
189			`rst = 0;`
190
191			`#50;`
192			`clk = 1;`
193			`rst = 0;`
194
195			`#50;`
196			`clk = 0;`
197			`rst = 0;`
198
199			`#50;`
200			`clk = 1;`
201			`rst = 0;`
202
203			`#50;`
204			`clk = 0;`
205			`rst = 0;`
206
207			`#50;`
208			`clk = 1;`
209			`rst = 0;`
210
211			`#50;`
212			`clk = 0;`
213			`rst = 0;`
214
215			`#50;`
216			`clk = 1;`
217			`rst = 0;`
218
219			`#50;`
220			`clk = 0;`
221			`rst = 0;`
222
223			`#50;`
224			`clk = 1;`
225			`rst = 0;`
226
227			`#50;`
228			`clk = 0;`
229			`rst = 0;`
230
231			`#50;`
232			`clk = 1;`
233			`rst = 0;`
234			`// End of ADD Nanoroutine`
235			`// Start of SUB Nanoroutine`
236			`#50;`
237			`clk = 0;`
238			`rst = 0;`
239
240			`#50;`
241			`clk = 1;`
242			`rst = 0;`
243
244			`#50;`
245			`clk = 0;`
246			`rst = 0;`
247
248			`#50;`
249			`clk = 1;`
250			`rst = 0;`
251
252			`#50;`
253			`clk = 0;`
254			`rst = 0;`
255
256			`#50;`
257			`clk = 1;`
258			`rst = 0;`
259
260			`#50;`
261			`clk = 0;`
262			`rst = 0;`
263
264			`#50;`
265			`clk = 1;`
266			`rst = 0;`
267
268			`#50;`
269			`clk = 0;`
270			`rst = 0;`
271
272			`#50;`
273			`clk = 1;`
274			`rst = 0;`
275
276			`#50;`
277			`clk = 0;`
278			`rst = 0;`
279
280			`#50;`
281			`clk = 1;`
282			`rst = 0;`
283
284			`#50;`
285			`clk = 0;`
286			`rst = 0;`
287
288			`#50;`
289			`clk = 1;`
290			`rst = 0;`
291
292			`#50;`
293			`clk = 0;`
294			`rst = 0;`
295
296			`#50;`
297			`clk = 1;`
298			`rst = 0;`
299			`// End of SUB Nanoroutine`
300			`// Start of OUT Nanoroutine`
301			`#50;`
302			`clk = 0;`
303			`rst = 0;`
304
305			`#50;`
306			`clk = 1;`
307			`rst = 0;`
308
309
310			`#50;`
311			`clk = 0;`
312			`rst = 0;`
313
314			`#50;`
315			`clk = 1;`
316			`rst = 0;`
317
318			`#50;`
319			`clk = 0;`
320			`rst = 0;`
321
322			`#50;`
323			`clk = 1;`
324			`rst = 0;`
325
326			`#50;`
327			`clk = 0;`
328			`rst = 0;`
329
330			`#50;`
331			`clk = 1;`
332			`rst = 0;`
333
334			`#50;`
335			`clk = 0;`
336			`rst = 0;`
337
338			`#50;`
339			`clk = 1;`
340			`rst = 0;`
341
342			`#50;`
343			`clk = 0;`
344			`rst = 0;`
345
346			`#50;`
347			`clk = 1;`
348			`rst = 0;`
349
350			`#50;`
351			`clk = 0;`
352			`rst = 0;`
353
354			`#50;`
355			`clk = 1;`
356			`rst = 0;`
357
358
359
360
361
362
363
364
365
366
367			`end`
368
369			`endmodule`
370