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`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   18:19:16 07/03/2022
// Design Name:   M2CPU8
// Module Name:   F:/VIDEO FACTORY/XILINX/SAP_VERTICAL_MICROPROGRAMMED/M2CPU8_tb.v
// Project Name:  SAP_VERTICAL_MICROPROGRAMMED
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: M2CPU8
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
 
module M2CPU8_tb;
 
        // Inputs
        reg clk;
        reg rst;
 
        // Outputs
        wire EP;
        wire CP;
        wire [4:0] PC_OUT_o;
        wire [4:0] SRAM_ADDR_o;
        wire LM;
        wire CE_o;
        wire [3:0] IR_1_OUT_o;
        wire [4:0] IR_2_OUT_o;
        wire [8:0] SRAM_OUT;
        wire LI_o;
        wire EI_o;
        wire CS_o;
        wire LOAD_o;
        wire INC_o;
        wire CLR_o;
        wire LA_o;
        wire EA_o;
        wire SU_o;
        wire AD_o;
        wire EU_o;
        wire LB_o;
        wire LO_o;
        wire [8:0] OUT_o;
        wire [4:0] PRE_OUT_o;
        wire [8:0] ACC_OUT_o;
        wire [8:0] ACC_OUT_bus_o;
        wire [8:0] B_o;
        wire [8:0] ALU_OUT_o;
        wire [8:0] ALU_OUT_bus;
 
        // Instantiate the Unit Under Test (UUT)
        M2CPU8 uut (
                .clk(clk),
                .rst(rst),
                .EP(EP),
                .CP(CP),
                .PC_OUT_o(PC_OUT_o),
                .SRAM_ADDR_o(SRAM_ADDR_o),
                .LM(LM),
                .CE_o(CE_o),
                .IR_1_OUT_o(IR_1_OUT_o),
                .IR_2_OUT_o(IR_2_OUT_o),
                .SRAM_OUT(SRAM_OUT),
                .LI_o(LI_o),
                .EI_o(EI_o),
                .CS_o(CS_o),
                .LOAD_o(LOAD_o),
                .INC_o(INC_o),
                .CLR_o(CLR_o),
                .LA_o(LA_o),
                .EA_o(EA_o),
                .SU_o(SU_o),
                .AD_o(AD_o),
                .EU_o(EU_o),
                .LB_o(LB_o),
                .LO_o(LO_o),
                .OUT_o(OUT_o),
                .PRE_OUT_o(PRE_OUT_o),
                .ACC_OUT_o(ACC_OUT_o),
                .ACC_OUT_bus_o(ACC_OUT_bus_o),
                .B_o(B_o),
                .ALU_OUT_o(ALU_OUT_o),
                .ALU_OUT_bus(ALU_OUT_bus)
        );
 
        initial begin
                // Start LDA Routine
                clk = 0;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 1;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
// End of LDA Routine
// Start of ADD Routine
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
// End of ADD Routine
// Start of SUB Routine
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
// End of SUB Routine
// Start of OUT Routine
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
// End of OUT Routine
        end
 
endmodule
 

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Subversion Repositories sap_1_vertical_microprogrammed_processor

[/] [sap_1_vertical_microprogrammed_processor/] [branches/] [M2CPU8_tb.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	sssayeekum	`timescale 1ns / 1ps
2
3			`////////////////////////////////////////////////////////////////////////////////`
4			`// Company:`
5			`// Engineer:`
6			`//`
7			`// Create Date: 18:19:16 07/03/2022`
8			`// Design Name: M2CPU8`
9			`// Module Name: F:/VIDEO FACTORY/XILINX/SAP_VERTICAL_MICROPROGRAMMED/M2CPU8_tb.v`
10			`// Project Name: SAP_VERTICAL_MICROPROGRAMMED`
11			`// Target Device:`
12			`// Tool versions:`
13			`// Description:`
14			`//`
15			`// Verilog Test Fixture created by ISE for module: M2CPU8`
16			`//`
17			`// Dependencies:`
18			`//`
19			`// Revision:`
20			`// Revision 0.01 - File Created`
21			`// Additional Comments:`
22			`//`
23			`////////////////////////////////////////////////////////////////////////////////`
24
25			`module M2CPU8_tb;`
26
27			`// Inputs`
28			`reg clk;`
29			`reg rst;`
30
31			`// Outputs`
32			`wire EP;`
33			`wire CP;`
34			`wire [4:0] PC_OUT_o;`
35			`wire [4:0] SRAM_ADDR_o;`
36			`wire LM;`
37			`wire CE_o;`
38			`wire [3:0] IR_1_OUT_o;`
39			`wire [4:0] IR_2_OUT_o;`
40			`wire [8:0] SRAM_OUT;`
41			`wire LI_o;`
42			`wire EI_o;`
43			`wire CS_o;`
44			`wire LOAD_o;`
45			`wire INC_o;`
46			`wire CLR_o;`
47			`wire LA_o;`
48			`wire EA_o;`
49			`wire SU_o;`
50			`wire AD_o;`
51			`wire EU_o;`
52			`wire LB_o;`
53			`wire LO_o;`
54			`wire [8:0] OUT_o;`
55			`wire [4:0] PRE_OUT_o;`
56			`wire [8:0] ACC_OUT_o;`
57			`wire [8:0] ACC_OUT_bus_o;`
58			`wire [8:0] B_o;`
59			`wire [8:0] ALU_OUT_o;`
60			`wire [8:0] ALU_OUT_bus;`
61
62			`// Instantiate the Unit Under Test (UUT)`
63			`M2CPU8 uut (`
64			`.clk(clk),`
65			`.rst(rst),`
66			`.EP(EP),`
67			`.CP(CP),`
68			`.PC_OUT_o(PC_OUT_o),`
69			`.SRAM_ADDR_o(SRAM_ADDR_o),`
70			`.LM(LM),`
71			`.CE_o(CE_o),`
72			`.IR_1_OUT_o(IR_1_OUT_o),`
73			`.IR_2_OUT_o(IR_2_OUT_o),`
74			`.SRAM_OUT(SRAM_OUT),`
75			`.LI_o(LI_o),`
76			`.EI_o(EI_o),`
77			`.CS_o(CS_o),`
78			`.LOAD_o(LOAD_o),`
79			`.INC_o(INC_o),`
80			`.CLR_o(CLR_o),`
81			`.LA_o(LA_o),`
82			`.EA_o(EA_o),`
83			`.SU_o(SU_o),`
84			`.AD_o(AD_o),`
85			`.EU_o(EU_o),`
86			`.LB_o(LB_o),`
87			`.LO_o(LO_o),`
88			`.OUT_o(OUT_o),`
89			`.PRE_OUT_o(PRE_OUT_o),`
90			`.ACC_OUT_o(ACC_OUT_o),`
91			`.ACC_OUT_bus_o(ACC_OUT_bus_o),`
92			`.B_o(B_o),`
93			`.ALU_OUT_o(ALU_OUT_o),`
94			`.ALU_OUT_bus(ALU_OUT_bus)`
95			`);`
96
97			`initial begin`
98			`// Start LDA Routine`
99			`clk = 0;`
100			`rst = 0;`
101
102			`#50;`
103			`clk = 0;`
104			`rst = 1;`
105
106			`#50;`
107			`clk = 1;`
108			`rst = 0;`
109
110			`#50;`
111			`clk = 0;`
112			`rst = 0;`
113
114			`#50;`
115			`clk = 1;`
116			`rst = 0;`
117
118			`#50;`
119			`clk = 0;`
120			`rst = 0;`
121
122			`#50;`
123			`clk = 1;`
124			`rst = 0;`
125
126			`#50;`
127			`clk = 0;`
128			`rst = 0;`
129
130			`#50;`
131			`clk = 1;`
132			`rst = 0;`
133
134			`#50;`
135			`clk = 0;`
136			`rst = 0;`
137
138			`#50;`
139			`clk = 1;`
140			`rst = 0;`
141
142			`#50;`
143			`clk = 0;`
144			`rst = 0;`
145
146			`#50;`
147			`clk = 1;`
148			`rst = 0;`
149			`// End of LDA Routine`
150			`// Start of ADD Routine`
151			`#50;`
152			`clk = 0;`
153			`rst = 0;`
154
155			`#50;`
156			`clk = 1;`
157			`rst = 0;`
158
159			`#50;`
160			`clk = 0;`
161			`rst = 0;`
162
163			`#50;`
164			`clk = 1;`
165			`rst = 0;`
166
167			`#50;`
168			`clk = 0;`
169			`rst = 0;`
170
171			`#50;`
172			`clk = 1;`
173			`rst = 0;`
174
175			`#50;`
176			`clk = 0;`
177			`rst = 0;`
178
179			`#50;`
180			`clk = 1;`
181			`rst = 0;`
182
183			`#50;`
184			`clk = 0;`
185			`rst = 0;`
186
187			`#50;`
188			`clk = 1;`
189			`rst = 0;`
190
191			`#50;`
192			`clk = 0;`
193			`rst = 0;`
194
195			`#50;`
196			`clk = 1;`
197			`rst = 0;`
198
199			`#50;`
200			`clk = 0;`
201			`rst = 0;`
202
203			`#50;`
204			`clk = 1;`
205			`rst = 0;`
206
207			`#50;`
208			`clk = 0;`
209			`rst = 0;`
210
211			`#50;`
212			`clk = 1;`
213			`rst = 0;`
214
215			`#50;`
216			`clk = 0;`
217			`rst = 0;`
218
219			`#50;`
220			`clk = 1;`
221			`rst = 0;`
222			`// End of ADD Routine`
223			`// Start of SUB Routine`
224			`#50;`
225			`clk = 0;`
226			`rst = 0;`
227
228			`#50;`
229			`clk = 1;`
230			`rst = 0;`
231
232			`#50;`
233			`clk = 0;`
234			`rst = 0;`
235
236			`#50;`
237			`clk = 1;`
238			`rst = 0;`
239
240			`#50;`
241			`clk = 0;`
242			`rst = 0;`
243
244			`#50;`
245			`clk = 1;`
246			`rst = 0;`
247
248			`#50;`
249			`clk = 0;`
250			`rst = 0;`
251
252			`#50;`
253			`clk = 1;`
254			`rst = 0;`
255
256			`#50;`
257			`clk = 0;`
258			`rst = 0;`
259
260			`#50;`
261			`clk = 1;`
262			`rst = 0;`
263
264			`#50;`
265			`clk = 0;`
266			`rst = 0;`
267
268			`#50;`
269			`clk = 1;`
270			`rst = 0;`
271
272			`#50;`
273			`clk = 0;`
274			`rst = 0;`
275
276			`#50;`
277			`clk = 1;`
278			`rst = 0;`
279
280			`#50;`
281			`clk = 0;`
282			`rst = 0;`
283
284			`#50;`
285			`clk = 1;`
286			`rst = 0;`
287
288			`#50;`
289			`clk = 0;`
290			`rst = 0;`
291
292			`#50;`
293			`clk = 1;`
294			`rst = 0;`
295			`// End of SUB Routine`
296			`// Start of OUT Routine`
297			`#50;`
298			`clk = 0;`
299			`rst = 0;`
300
301			`#50;`
302			`clk = 1;`
303			`rst = 0;`
304
305			`#50;`
306			`clk = 0;`
307			`rst = 0;`
308
309			`#50;`
310			`clk = 1;`
311			`rst = 0;`
312
313			`#50;`
314			`clk = 0;`
315			`rst = 0;`
316
317			`#50;`
318			`clk = 1;`
319			`rst = 0;`
320
321			`#50;`
322			`clk = 0;`
323			`rst = 0;`
324
325			`#50;`
326			`clk = 1;`
327			`rst = 0;`
328
329			`#50;`
330			`clk = 0;`
331			`rst = 0;`
332
333			`#50;`
334			`clk = 1;`
335			`rst = 0;`
336
337			`#50;`
338			`clk = 0;`
339			`rst = 0;`
340
341			`#50;`
342			`clk = 1;`
343			`rst = 0;`
344
345			`#50;`
346			`clk = 0;`
347			`rst = 0;`
348
349			`#50;`
350			`clk = 1;`
351			`rst = 0;`
352			`// End of OUT Routine`
353			`end`
354
355			`endmodule`
356