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[/] [sap_microprogrammed_processor/] [branches/] [MCPU8_1_tb.v] - Blame information for rev 6

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`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   22:10:26 07/02/2022
// Design Name:   MCPU8_1
// Module Name:   F:/VIDEO FACTORY/XILINX/SAP_MICROPROGRAMMED_HARDWARE/MCPU8_1_tb.v
// Project Name:  SAP_MICROPROGRAMMED_HARDWARE
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: MCPU8_1
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
 
module MCPU8_1_tb;
 
        // Inputs
        reg clk;
        reg rst;
 
        // Outputs
        wire [4:0] PC_OUT;
        wire [4:0] MAR_OUT;
        wire [3:0] IR_OUT1;
        wire [4:0] IR_OUT2;
        wire [8:0] DATA_OUT1;
        wire [4:0] ADDR_OUT1;
        wire [4:0] COUNT_OUT;
        wire [8:0] ACCUMULATOR_OUT;
        wire [8:0] DATA_OUTPUT;
        wire [8:0] B_REG;
        wire [8:0] ALU_OUT;
        wire [8:0] OR_out;
        wire [16:0] CW;
        wire EP;
        wire CP;
        wire LM;
        wire CE;
        wire LI;
        wire EI;
        wire CS;
        wire LOAD;
        wire CLR;
        wire INC;
        wire LA;
        wire EA;
        wire LB;
        wire SU;
        wire AD;
        wire EU;
        wire LO;
 
        // Instantiate the Unit Under Test (UUT)
        MCPU8_1 uut (
                .clk(clk),
                .rst(rst),
                .PC_OUT(PC_OUT),
                .MAR_OUT(MAR_OUT),
                .IR_OUT1(IR_OUT1),
                .IR_OUT2(IR_OUT2),
                .DATA_OUT1(DATA_OUT1),
                .ADDR_OUT1(ADDR_OUT1),
                .COUNT_OUT(COUNT_OUT),
                .ACCUMULATOR_OUT(ACCUMULATOR_OUT),
                .DATA_OUTPUT(DATA_OUTPUT),
                .B_REG(B_REG),
                .ALU_OUT(ALU_OUT),
                .OR_out(OR_out),
                .CW(CW),
                .EP(EP),
                .CP(CP),
                .LM(LM),
                .CE(CE),
                .LI(LI),
                .EI(EI),
                .CS(CS),
                .LOAD(LOAD),
                .CLR(CLR),
                .INC(INC),
                .LA(LA),
                .EA(EA),
                .LB(LB),
                .SU(SU),
                .AD(AD),
                .EU(EU),
                .LO(LO)
        );
 
        initial begin
 
                // Start LDA Routine
                clk = 0;
                rst = 0;
 
                #50;
      clk = 0;
                rst = 1;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
// End of LDA Routine
// Start ADD Routine
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
// End of ADD Routine
// Start SUB Routine
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
// End of SUB Routine
// Start of OUT Routine
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
      #50;
      clk = 0;
                rst = 0;
 
      #50;
      clk = 1;
                rst = 0;
 
        end
 
endmodule
 

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Subversion Repositories sap_microprogrammed_processor

[/] [sap_microprogrammed_processor/] [branches/] [MCPU8_1_tb.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	6	sssayeekum	`timescale 1ns / 1ps
2
3			`////////////////////////////////////////////////////////////////////////////////`
4			`// Company:`
5			`// Engineer:`
6			`//`
7			`// Create Date: 22:10:26 07/02/2022`
8			`// Design Name: MCPU8_1`
9			`// Module Name: F:/VIDEO FACTORY/XILINX/SAP_MICROPROGRAMMED_HARDWARE/MCPU8_1_tb.v`
10			`// Project Name: SAP_MICROPROGRAMMED_HARDWARE`
11			`// Target Device:`
12			`// Tool versions:`
13			`// Description:`
14			`//`
15			`// Verilog Test Fixture created by ISE for module: MCPU8_1`
16			`//`
17			`// Dependencies:`
18			`//`
19			`// Revision:`
20			`// Revision 0.01 - File Created`
21			`// Additional Comments:`
22			`//`
23			`////////////////////////////////////////////////////////////////////////////////`
24
25			`module MCPU8_1_tb;`
26
27			`// Inputs`
28			`reg clk;`
29			`reg rst;`
30
31			`// Outputs`
32			`wire [4:0] PC_OUT;`
33			`wire [4:0] MAR_OUT;`
34			`wire [3:0] IR_OUT1;`
35			`wire [4:0] IR_OUT2;`
36			`wire [8:0] DATA_OUT1;`
37			`wire [4:0] ADDR_OUT1;`
38			`wire [4:0] COUNT_OUT;`
39			`wire [8:0] ACCUMULATOR_OUT;`
40			`wire [8:0] DATA_OUTPUT;`
41			`wire [8:0] B_REG;`
42			`wire [8:0] ALU_OUT;`
43			`wire [8:0] OR_out;`
44			`wire [16:0] CW;`
45			`wire EP;`
46			`wire CP;`
47			`wire LM;`
48			`wire CE;`
49			`wire LI;`
50			`wire EI;`
51			`wire CS;`
52			`wire LOAD;`
53			`wire CLR;`
54			`wire INC;`
55			`wire LA;`
56			`wire EA;`
57			`wire LB;`
58			`wire SU;`
59			`wire AD;`
60			`wire EU;`
61			`wire LO;`
62
63			`// Instantiate the Unit Under Test (UUT)`
64			`MCPU8_1 uut (`
65			`.clk(clk),`
66			`.rst(rst),`
67			`.PC_OUT(PC_OUT),`
68			`.MAR_OUT(MAR_OUT),`
69			`.IR_OUT1(IR_OUT1),`
70			`.IR_OUT2(IR_OUT2),`
71			`.DATA_OUT1(DATA_OUT1),`
72			`.ADDR_OUT1(ADDR_OUT1),`
73			`.COUNT_OUT(COUNT_OUT),`
74			`.ACCUMULATOR_OUT(ACCUMULATOR_OUT),`
75			`.DATA_OUTPUT(DATA_OUTPUT),`
76			`.B_REG(B_REG),`
77			`.ALU_OUT(ALU_OUT),`
78			`.OR_out(OR_out),`
79			`.CW(CW),`
80			`.EP(EP),`
81			`.CP(CP),`
82			`.LM(LM),`
83			`.CE(CE),`
84			`.LI(LI),`
85			`.EI(EI),`
86			`.CS(CS),`
87			`.LOAD(LOAD),`
88			`.CLR(CLR),`
89			`.INC(INC),`
90			`.LA(LA),`
91			`.EA(EA),`
92			`.LB(LB),`
93			`.SU(SU),`
94			`.AD(AD),`
95			`.EU(EU),`
96			`.LO(LO)`
97			`);`
98
99			`initial begin`
100
101			`// Start LDA Routine`
102			`clk = 0;`
103			`rst = 0;`
104
105			`#50;`
106			`clk = 0;`
107			`rst = 1;`
108
109			`#50;`
110			`clk = 1;`
111			`rst = 0;`
112
113			`#50;`
114			`clk = 0;`
115			`rst = 0;`
116
117			`#50;`
118			`clk = 1;`
119			`rst = 0;`
120
121			`#50;`
122			`clk = 0;`
123			`rst = 0;`
124
125			`#50;`
126			`clk = 1;`
127			`rst = 0;`
128
129			`#50;`
130			`clk = 0;`
131			`rst = 0;`
132
133			`#50;`
134			`clk = 1;`
135			`rst = 0;`
136
137			`#50;`
138			`clk = 0;`
139			`rst = 0;`
140
141			`#50;`
142			`clk = 1;`
143			`rst = 0;`
144
145			`#50;`
146			`clk = 0;`
147			`rst = 0;`
148
149			`#50;`
150			`clk = 1;`
151			`rst = 0;`
152			`// End of LDA Routine`
153			`// Start ADD Routine`
154			`#50;`
155			`clk = 0;`
156			`rst = 0;`
157
158			`#50;`
159			`clk = 1;`
160			`rst = 0;`
161
162			`#50;`
163			`clk = 0;`
164			`rst = 0;`
165
166			`#50;`
167			`clk = 1;`
168			`rst = 0;`
169
170			`#50;`
171			`clk = 0;`
172			`rst = 0;`
173
174			`#50;`
175			`clk = 1;`
176			`rst = 0;`
177
178			`#50;`
179			`clk = 0;`
180			`rst = 0;`
181
182			`#50;`
183			`clk = 1;`
184			`rst = 0;`
185
186			`#50;`
187			`clk = 0;`
188			`rst = 0;`
189
190			`#50;`
191			`clk = 1;`
192			`rst = 0;`
193
194			`#50;`
195			`clk = 0;`
196			`rst = 0;`
197
198			`#50;`
199			`clk = 1;`
200			`rst = 0;`
201
202			`#50;`
203			`clk = 0;`
204			`rst = 0;`
205
206			`#50;`
207			`clk = 1;`
208			`rst = 0;`
209
210			`#50;`
211			`clk = 0;`
212			`rst = 0;`
213
214			`#50;`
215			`clk = 1;`
216			`rst = 0;`
217
218			`#50;`
219			`clk = 0;`
220			`rst = 0;`
221
222			`#50;`
223			`clk = 1;`
224			`rst = 0;`
225			`// End of ADD Routine`
226			`// Start SUB Routine`
227			`#50;`
228			`clk = 0;`
229			`rst = 0;`
230
231			`#50;`
232			`clk = 1;`
233			`rst = 0;`
234
235			`#50;`
236			`clk = 0;`
237			`rst = 0;`
238
239			`#50;`
240			`clk = 1;`
241			`rst = 0;`
242
243			`#50;`
244			`clk = 0;`
245			`rst = 0;`
246
247			`#50;`
248			`clk = 1;`
249			`rst = 0;`
250
251			`#50;`
252			`clk = 0;`
253			`rst = 0;`
254
255			`#50;`
256			`clk = 1;`
257			`rst = 0;`
258
259			`#50;`
260			`clk = 0;`
261			`rst = 0;`
262
263			`#50;`
264			`clk = 1;`
265			`rst = 0;`
266
267			`#50;`
268			`clk = 0;`
269			`rst = 0;`
270
271			`#50;`
272			`clk = 1;`
273			`rst = 0;`
274
275			`#50;`
276			`clk = 0;`
277			`rst = 0;`
278
279			`#50;`
280			`clk = 1;`
281			`rst = 0;`
282
283			`#50;`
284			`clk = 0;`
285			`rst = 0;`
286
287			`#50;`
288			`clk = 1;`
289			`rst = 0;`
290
291			`#50;`
292			`clk = 0;`
293			`rst = 0;`
294
295			`#50;`
296			`clk = 1;`
297			`rst = 0;`
298			`// End of SUB Routine`
299			`// Start of OUT Routine`
300			`#50;`
301			`clk = 0;`
302			`rst = 0;`
303
304			`#50;`
305			`clk = 1;`
306			`rst = 0;`
307
308			`#50;`
309			`clk = 0;`
310			`rst = 0;`
311
312			`#50;`
313			`clk = 1;`
314			`rst = 0;`
315
316			`#50;`
317			`clk = 0;`
318			`rst = 0;`
319
320			`#50;`
321			`clk = 1;`
322			`rst = 0;`
323
324			`#50;`
325			`clk = 0;`
326			`rst = 0;`
327
328			`#50;`
329			`clk = 1;`
330			`rst = 0;`
331
332			`#50;`
333			`clk = 0;`
334			`rst = 0;`
335
336			`#50;`
337			`clk = 1;`
338			`rst = 0;`
339
340			`#50;`
341			`clk = 0;`
342			`rst = 0;`
343
344			`#50;`
345			`clk = 1;`
346			`rst = 0;`
347
348			`#50;`
349			`clk = 0;`
350			`rst = 0;`
351
352			`#50;`
353			`clk = 1;`
354			`rst = 0;`
355
356			`end`
357
358			`endmodule`
359