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ashwin_men |
##############################################################
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#
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# Xilinx Core Generator version 12.2
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# Date: Wed Jun 13 13:42:08 2012
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc6vlx240t
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SET devicefamily = virtex6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = ff1156
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SET removerpms = false
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SET simulationfiles = Structural
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SET speedgrade = -1
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SET verilogsim = false
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SET vhdlsim = true
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# END Project Options
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# BEGIN Select
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SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a
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# END Select
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# BEGIN Parameters
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CSET component_name=cmd_layer_ila
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CSET counter_width_1=Disabled
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CSET counter_width_10=Disabled
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CSET counter_width_11=Disabled
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CSET counter_width_12=Disabled
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CSET counter_width_13=Disabled
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CSET counter_width_14=Disabled
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CSET counter_width_15=Disabled
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CSET counter_width_16=Disabled
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CSET counter_width_2=Disabled
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CSET counter_width_3=Disabled
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CSET counter_width_4=Disabled
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CSET counter_width_5=Disabled
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CSET counter_width_6=Disabled
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CSET counter_width_7=Disabled
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CSET counter_width_8=Disabled
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CSET counter_width_9=Disabled
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CSET data_port_width=0
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CSET data_same_as_trigger=true
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CSET enable_storage_qualification=true
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CSET enable_trigger_output_port=false
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CSET exclude_from_data_storage_1=false
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CSET exclude_from_data_storage_10=false
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CSET exclude_from_data_storage_11=false
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CSET exclude_from_data_storage_12=false
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CSET exclude_from_data_storage_13=false
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CSET exclude_from_data_storage_14=false
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CSET exclude_from_data_storage_15=false
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CSET exclude_from_data_storage_16=false
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CSET exclude_from_data_storage_2=false
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CSET exclude_from_data_storage_3=false
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CSET exclude_from_data_storage_4=false
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CSET exclude_from_data_storage_5=false
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CSET exclude_from_data_storage_6=false
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CSET exclude_from_data_storage_7=false
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CSET exclude_from_data_storage_8=false
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CSET exclude_from_data_storage_9=false
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CSET match_type_1=basic_with_edges
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CSET match_type_10=basic_with_edges
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CSET match_type_11=basic_with_edges
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CSET match_type_12=basic_with_edges
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CSET match_type_13=basic_with_edges
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CSET match_type_14=basic_with_edges
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CSET match_type_15=basic_with_edges
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CSET match_type_16=basic_with_edges
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CSET match_type_2=basic_with_edges
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CSET match_type_3=basic_with_edges
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CSET match_type_4=basic_with_edges
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CSET match_type_5=basic_with_edges
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CSET match_type_6=basic_with_edges
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CSET match_type_7=basic_with_edges
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CSET match_type_8=basic_with_edges
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CSET match_type_9=basic_with_edges
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CSET match_units_1=1
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CSET match_units_10=1
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CSET match_units_11=1
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CSET match_units_12=1
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CSET match_units_13=1
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CSET match_units_14=1
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CSET match_units_15=1
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CSET match_units_16=1
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CSET match_units_2=1
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CSET match_units_3=1
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CSET match_units_4=1
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CSET match_units_5=1
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CSET match_units_6=1
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CSET match_units_7=1
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CSET match_units_8=1
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CSET match_units_9=1
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CSET max_sequence_levels=1
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CSET number_of_trigger_ports=14
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CSET sample_data_depth=1024
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CSET sample_on=Rising
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CSET trigger_port_width_1=4
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CSET trigger_port_width_10=24
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CSET trigger_port_width_11=16
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CSET trigger_port_width_12=12
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CSET trigger_port_width_13=16
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CSET trigger_port_width_14=32
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CSET trigger_port_width_15=8
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CSET trigger_port_width_16=8
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CSET trigger_port_width_2=32
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CSET trigger_port_width_3=32
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CSET trigger_port_width_4=32
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CSET trigger_port_width_5=32
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CSET trigger_port_width_6=2
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CSET trigger_port_width_7=2
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CSET trigger_port_width_8=32
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CSET trigger_port_width_9=32
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CSET use_rpms=true
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# END Parameters
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GENERATE
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# CRC: 5bd813f9
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