URL https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk

Subversion Repositories sata_controller_core

[/] [sata_controller_core/] [trunk/] [sata2_bus_v1_00_a/] [base_system/] [pcores/] [sata_core_v1_00_a/] [hdl/] [verilog/] [mux_41.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	ashwin_men	`//--------------------------------------------------------------------------------`
2			`// Entity mux_21`
3			`// Version: 1.0`
4			`// Author: Ashwin Mendon`
5			`// Description: 32 bit 4:1 Multiplexer`
6			`//--------------------------------------------------------------------------------`
7
8			`module mux_41`
9			`(`
10			`input wire [31:0] a,`
11			`input wire [31:0] b,`
12			`input wire [31:0] c,`
13			`input wire [31:0] d,`
14			`input wire [1:0] sel,`
15			`output reg [31:0] o`
16			`);`
17
18			`always @ (a or b or c or d or sel)`
19			`begin`
20			`case (sel)`
21			`2'b00:`
22			`o = a;`
23			`2'b01:`
24			`o = b;`
25			`2'b10:`
26			`o = c;`
27			`2'b11:`
28			`o = d;`
29			`endcase`
30			`end`
31
32			`endmodule`
33