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[/] [sata_controller_core/] [trunk/] [sata2_bus_v1_00_a/] [base_system/] [pcores/] [sata_core_v1_00_a/] [hdl/] [vhdl/] [sata_link_layer.vhd] - Blame information for rev 13

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1 11 ashwin_men 
-- Copyright (C) 2012
2 
-- Ashwin A. Mendon
3 
--
4 
-- This file is part of SATA2 core.
5 
--
6 
-- This program is free software; you can redistribute it and/or modify
7 
-- it under the terms of the GNU General Public License as published by
8 
-- the Free Software Foundation; either version 3 of the License, or
9 
-- (at your option) any later version.
10 
--
11 
-- This program is distributed in the hope that it will be useful,
12 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 
-- GNU General Public License for more details.
15 
--
16 
-- You should have received a copy of the GNU General Public License
17 
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
18 
 
19 
----------------------------------------------------------------------------------------
20 
-- ENTITY: sata_link_layer
21 
-- Version: 1.0
22 
-- Author:  Ashwin Mendon
23 
-- Description: This sub-module implements the Transport and Link Layers of the SATA Protocol
24 
--              It is the heart of the SATA Core where the major functions of sending/receiving
25 
--              sequences of Frame Information Structures (FIS), packing them into
26 
--              Frames and sending/receiving Frames are accomplished.
27 
--              The Master FSM deals with the Transport Layer functions of sending receiving FISs
28 
--              using the TX and RX FSMs.
29 
--              The TX and RX FSMs use the crc, scrambler and primitive muxes to construct and
30 
--              deconstruct Frames. They also implement a Frame transmission/reception protocol.
31 
-- PORTS:
32 
-----------------------------------------------------------------------------------------
33 
 
34 
library IEEE;
35 
use IEEE.STD_LOGIC_1164.all;
36 
use IEEE.STD_LOGIC_ARITH.all;
37 
use IEEE.STD_LOGIC_UNSIGNED.all;
38 
 
39 
entity sata_link_layer is
40 
  generic(
41 
    CHIPSCOPE           : boolean := false;
42 
    DATA_WIDTH          : natural := 32
43 
       );
44 
  port(
45 
    -- Clock and Reset Signals
46 
    --clk                   : in  std_logic;
47 
    sw_reset              : in  std_logic;
48 
    -- ChipScope ILA / Trigger Signals
49 
    sata_rx_frame_ila_control : in  std_logic_vector(35 downto 0);
50 
    sata_tx_frame_ila_control : in  std_logic_vector(35 downto 0);
51 
    --master_fsm_ila_control    : in  std_logic_vector(35 downto 0);
52 
    oob_control_ila_control   : in  std_logic_vector(35 downto 0);
53 
    sata_phy_ila_control      : in  std_logic_vector(35 downto 0);
54 
    scrambler_ila_control    : in std_logic_vector (35 downto 0);
55 
    descrambler_ila_control    : in std_logic_vector (35 downto 0);
56 
    ---------------------------------------
57 
    -- Signals from/to User Logic
58 
    sata_user_clk_out     : out std_logic;
59 
    GTX_RESET_IN          : in  std_logic;
60 
    ready_for_cmd_out     : out std_logic;
61 
    new_cmd_in            : in  std_logic;
62 
    cmd_type              : in  std_logic_vector(1 downto 0);
63 
    sector_count          : in  integer;
64 
    sata_din              : in  std_logic_vector(DATA_WIDTH-1 downto 0);
65 
    sata_din_we           : in  std_logic;
66 
    sata_dout             : out std_logic_vector(DATA_WIDTH-1 downto 0);
67 
    sata_dout_re          : in  std_logic;
68 
    read_fifo_empty       : out std_logic;
69 
    write_fifo_full       : out std_logic;
70 
    ---------------------------------------
71 
    --  Ports from/to SATA PHY
72 
    REFCLK_PAD_P_IN : in std_logic;     -- MGTCLKA,  clocks GTP_X0Y0-2
73 
    REFCLK_PAD_N_IN : in std_logic;     -- MGTCLKA
74 
    TXP0_OUT              : out std_logic;
75 
    TXN0_OUT              : out std_logic;
76 
    RXP0_IN               : in  std_logic;
77 
    RXN0_IN               : in  std_logic;
78 
    PLLLKDET_OUT_N  : out std_logic;
79 
    DCMLOCKED_OUT         : out std_logic;
80 
    LINKUP_led            : out std_logic;
81 
    --GEN2_led              : out std_logic;
82 
    CLKIN_150             : in  std_logic
83 
      );
84 
end sata_link_layer;
85 
 
86 
 
87 
-------------------------------------------------------------------------------
88 
-- ARCHITECTURE
89 
-------------------------------------------------------------------------------
90 
architecture BEHAV of sata_link_layer is
91 
 
92 
  -------------------------------------------------------------------------------
93 
  -- LINK LAYER
94 
  -------------------------------------------------------------------------------
95 
 
96 
  -------------------------------------------------------------------------------
97 
  -- Constants
98 
  -------------------------------------------------------------------------------
99 
  --Commands
100 
  constant IDEN_DEV     : std_logic_vector(1 downto 0) := "00";
101 
  constant READ_DMA     : std_logic_vector(1 downto 0) := "01";
102 
  constant WRITE_DMA    : std_logic_vector(1 downto 0) := "10";
103 
  constant SET_FEATURES : std_logic_vector(1 downto 0) := "11";
104 
  --Primitves
105 
  constant SYNC     : std_logic_vector(3 downto 0) := "0000";
106 
  constant R_RDY    : std_logic_vector(3 downto 0) := "0001";
107 
  constant R_IP     : std_logic_vector(3 downto 0) := "0010";
108 
  constant R_OK     : std_logic_vector(3 downto 0) := "0011";
109 
  constant R_ERR    : std_logic_vector(3 downto 0) := "0100";
110 
  constant X_RDY    : std_logic_vector(3 downto 0) := "0101";
111 
  constant WTRM     : std_logic_vector(3 downto 0) := "0110";
112 
  constant HOLD     : std_logic_vector(3 downto 0) := "0111";
113 
  constant HOLD_ACK : std_logic_vector(3 downto 0) := "1000";
114 
  constant CONT     : std_logic_vector(3 downto 0) := "1001";
115 
 
116 
  constant SOF      : std_logic_vector(3 downto 0) := "1010";
117 
  constant EOF      : std_logic_vector(3 downto 0) := "1011";
118 
  constant FIS      : std_logic_vector(3 downto 0) := "1100";
119 
  constant PRIM_SCRM : std_logic_vector(3 downto 0) := "1101";
120 
 
121 
  constant COMMAND_FIS       : std_logic_vector(15 downto 0) := conv_std_logic_vector(5, 16);   -- (6DWORDS: 5 + 1CRC)
122 
  --constant DATA_FIS          : std_logic_vector(15 downto 0) := conv_std_logic_vector(259, 16);  -- 260 WORDS (130DWORDS: 1FIS_TYPE + 128DATA + 1CRC)
123 
  constant REG_FIS_NDWORDS   : std_logic_vector(15 downto 0) := conv_std_logic_vector(6, 16);   -- (6DWORDS: 5 + 1CRC)
124 
  constant DATA_FIS_NDWORDS  : integer := 130;
125 
  constant SECTOR_NDWORDS     : integer := 128;  -- 256 WORDS / 512 Byte Sector
126 
  constant NDWORDS_PER_DATA_FIS : std_logic_vector(15 downto 0) := conv_std_logic_vector(2048, 16);--128*16
127 
  constant NDWORDS_PER_DATA_FIS_32 : std_logic_vector(31 downto 0) := conv_std_logic_vector(2048, 32);--128*16
128 
  constant SYNC_COUNT_VALUE  : std_logic_vector(7 downto 0)  := conv_std_logic_vector(30, 8);    -- 50  WORDS
129 
  -----------------------------------------------------------------------------
130 
  -- Finite State Machine Declaration (curr and next states)
131 
  -----------------------------------------------------------------------------
132 
  type MASTER_FSM_TYPE is (idle, capture_dev_sign, wait_for_cmd, H2D_REG_FIS, D2H_DMA_ACT_FIS,
133 
            H2D_DATA_FIS, D2H_REG_FIS, D2H_DATA_FIS, D2H_PIO_SETUP, dead
134 
                     );
135 
  signal master_fsm_curr, master_fsm_next : MASTER_FSM_TYPE := idle;
136 
  signal master_fsm_value                  : std_logic_vector (0 to 3);
137 
 
138 
 
139 
  type RX_FRAME_FSM_TYPE is (idle, send_R_RDY, send_R_IP, send_HOLD_ACK, send_R_OK,
140 
                        send_SYNC, wait_for_X_RDY, dead
141 
                     );
142 
  signal rx_frame_curr, rx_frame_next  : RX_FRAME_FSM_TYPE := idle;
143 
  signal rx_frame_value                : std_logic_vector (0 to 3);
144 
 
145 
 
146 
  type TX_FRAME_FSM_TYPE is (idle, send_X_RDY, send_SOF, send_FIS, send_EOF, send_WTRM,
147 
                        send_SYNC, send_HOLD_ACK, send_HOLD, dead
148 
                     );
149 
  signal tx_frame_curr, tx_frame_next  : TX_FRAME_FSM_TYPE := idle;
150 
  signal tx_frame_value                : std_logic_vector (0 to 3);
151 
  -----------------------------------------------------------------------------
152 
  -- Finite State Machine Declaration (curr and next states)
153 
  -----------------------------------------------------------------------------
154 
 
155 
  signal new_cmd                       : std_logic;
156 
 
157 
  signal FIS_word_count, FIS_word_count_next : std_logic_vector(0 to 15); --Counter for FIS WORD Count (WRITE)
158 
  signal FIS_count_value, FIS_count_value_next : std_logic_vector(0 to 15);  --Counter LIMIT for FIS WORD Count (WRITE)
159 
  signal rx_sector_count : std_logic_vector(0 to 15); --Counter for number of received sectors
160 
  signal tx_sector_count, tx_sector_count_next : std_logic_vector(0 to 15); --Counter for number of transmitted sectors
161 
  signal dword_count : std_logic_vector(0 to 7);     --Counter for DWORDS in each received sector
162 
  signal DATA_FIS_dword_count : std_logic_vector(0 to 15);     --Counter for DWORDS in each received DATA FIS
163 
  signal dword_count_init_value      : std_logic_vector(0 to 31);
164 
  signal dword_count_value           : std_logic_vector(0 to 15);
165 
  signal start_rx, start_tx, rx_done, tx_done : std_logic;
166 
  signal start_rx_next, start_tx_next, rx_done_next, tx_done_next : std_logic;
167 
  signal prim_type_rx, prim_type_tx, prim_type       : std_logic_vector (0 to 3);
168 
  signal prim_type_rx_next, prim_type_tx_next : std_logic_vector (0 to 3);
169 
  signal rx_tx_state_sel, rx_tx_state_sel_next : std_logic;
170 
  signal sync_count_rx, sync_count_rx_next : std_logic_vector (0 to 7);
171 
  signal sync_count_tx, sync_count_tx_next : std_logic_vector (0 to 7);
172 
  signal ready_for_cmd_next              : std_logic;
173 
  signal ready_for_cmd                   : std_logic;
174 
  signal frame_err, frame_err_next       : std_logic;
175 
  signal tx_err, tx_err_next : std_logic;
176 
 
177 
  signal tx_r_rdy, tx_r_ip, tx_r_ok, tx_r_err        : std_logic_vector(0 to DATA_WIDTH-1);
178 
  signal tx_x_rdy, tx_wtrm, tx_sof, tx_eof, tx_sync  : std_logic_vector(0 to DATA_WIDTH-1);
179 
  signal tx_hold, tx_hold_ack, tx_cont               : std_logic_vector(0 to DATA_WIDTH-1);
180 
  signal tx_dataout                                  : std_logic_vector(0 to DATA_WIDTH-1);
181 
  signal tx_charisk_out                  : std_logic;
182 
  signal tx_charisk_RX_FRAME, tx_charisk_TX_FRAME: std_logic;
183 
  signal output_mux_sel                              : std_logic_vector(0 to 3);
184 
  signal align_en_out                                : std_logic;
185 
 
186 
  -- Primitive Detectors
187 
  signal SYNC_det         : std_logic;
188 
  signal R_RDY_det        : std_logic;
189 
  signal R_IP_det         : std_logic;
190 
  signal R_OK_det         : std_logic;
191 
  signal R_ERR_det        : std_logic;
192 
  signal SOF_det          : std_logic;
193 
  signal EOF_det          : std_logic;
194 
  signal X_RDY_det        : std_logic;
195 
  signal WTRM_det         : std_logic;
196 
  signal CONT_det         : std_logic;
197 
  signal HOLD_det         : std_logic;
198 
  signal HOLD_det_r       : std_logic;
199 
  signal HOLD_det_r2      : std_logic;
200 
  signal HOLD_det_r3      : std_logic;
201 
  signal HOLD_det_r4      : std_logic;
202 
  signal HOLD_start_det   : std_logic;
203 
  signal HOLD_stop_det    : std_logic;
204 
  signal HOLD_stop_after_ALIGN_det  : std_logic;
205 
  signal CORNER_CASE_HOLD : std_logic;
206 
  signal HOLD_ACK_det     : std_logic;
207 
  signal ALIGN_det        : std_logic;
208 
  signal ALIGN_det_r      : std_logic;
209 
  signal ALIGN_det_r2     : std_logic;
210 
  signal TWO_HOLD_det     : std_logic;
211 
  signal TWO_HOLD_det_r   : std_logic;
212 
 
213 
  -----------------------------------------------------------------------------
214 
  -- Internal Signals
215 
  -----------------------------------------------------------------------------
216 
  signal sata_user_clk : std_logic;
217 
  signal rx_datain    : std_logic_vector(0 to DATA_WIDTH-1);
218 
  signal rxelecidle   : std_logic;
219 
  signal rx_charisk_in  : std_logic_vector(3 downto 0);
220 
  -- Debugging OOB
221 
  signal OOB_state    : std_logic_vector (0 to 7);
222 
 
223 
  signal LINKUP           : std_logic;
224 
  signal GEN2_led_i       : std_logic;
225 
 
226 
  -- Scrambler/DeScrambler
227 
  signal scrambler_din                   : std_logic_vector(0 to DATA_WIDTH-1);
228 
  signal scrambler_dout                  : std_logic_vector(0 to DATA_WIDTH-1);
229 
  signal scrambler_en, scrambler_en_r    : std_logic;
230 
  signal scrambler_din_re, scrambler_din_re_r : std_logic;
231 
  signal scrambler_dout_we               : std_logic;
232 
  signal scrambler_reset                 : std_logic;
233 
  signal scrambler_reset_after_FIS       : std_logic;
234 
  signal descrambler_din                 : std_logic_vector(0 to DATA_WIDTH-1);
235 
  signal descrambler_dout                : std_logic_vector(0 to DATA_WIDTH-1);
236 
  signal descrambler_en                  : std_logic;
237 
  signal descrambler_din_re, descrambler_din_re_r  : std_logic;
238 
  signal descrambler_dout_we             : std_logic;
239 
  signal descrambler_reset               : std_logic;
240 
  signal scrambler_count                 : std_logic_vector(0 to 15);
241 
  signal scrambler_count_init_value      : std_logic_vector(0 to 31);
242 
  signal scrambler_count_value           : std_logic_vector(0 to 15);
243 
  signal scrambler_count_en_reg_fis      : std_logic;
244 
  signal scrambler_count_en_data_fis     : std_logic;
245 
 
246 
  -- CRC
247 
  signal crc_reset                       : std_logic;
248 
  signal crc_din                         : std_logic_vector(0 to DATA_WIDTH-1);
249 
  signal crc_dout                        : std_logic_vector(0 to DATA_WIDTH-1);
250 
  signal crc_dout_r                      : std_logic_vector(0 to DATA_WIDTH-1);
251 
  signal crc_en                          : std_logic;
252 
 
253 
  -----------------------------------------------------------------------------
254 
  -- Post-DeScramble Read FIFO to Command Layer
255 
  -----------------------------------------------------------------------------
256 
  signal read_fifo_re      : std_logic;
257 
  signal read_fifo_we      : std_logic;
258 
  signal read_fifo_empty_i : std_logic;
259 
  signal read_fifo_almost_empty : std_logic;
260 
  signal read_fifo_full    : std_logic;
261 
  signal read_fifo_prog_full : std_logic;
262 
  signal read_fifo_din     : std_logic_vector(0 to DATA_WIDTH-1);
263 
  signal read_fifo_dout    : std_logic_vector(0 to DATA_WIDTH-1);
264 
 
265 
  -----------------------------------------------------------------------------
266 
  -- Pre-DeScramble RX FIFO from PHY Layer
267 
  -----------------------------------------------------------------------------
268 
  signal rx_fifo_we        : std_logic;
269 
  signal rx_fifo_we_next   : std_logic;
270 
  signal rx_fifo_re        : std_logic;
271 
  signal rx_fifo_empty     : std_logic;
272 
  signal rx_fifo_almost_empty : std_logic;
273 
  signal rx_fifo_full      : std_logic;
274 
  signal rx_fifo_prog_full  : std_logic;
275 
  signal rx_fifo_din       : std_logic_vector(0 to DATA_WIDTH-1);
276 
  signal rx_fifo_dout      : std_logic_vector(0 to DATA_WIDTH-1);
277 
  signal rx_fifo_data_count      : std_logic_vector(0 to 9);
278 13 ashwin_men 
  signal rx_fifo_reset      : std_logic;
279 11 ashwin_men 
 
280 
  -----------------------------------------------------------------------------
281 
  -- Pre-Scramble Write FIFO from Command Layer
282 
  -----------------------------------------------------------------------------
283 
  signal write_fifo_we        : std_logic;
284 
  signal write_fifo_re        : std_logic;
285 
  signal write_fifo_empty     : std_logic;
286 
  signal write_fifo_almost_empty  : std_logic;
287 
  signal write_fifo_full_i    : std_logic;
288 
  signal write_fifo_prog_full : std_logic;
289 
  signal write_fifo_din       : std_logic_vector(0 to DATA_WIDTH-1);
290 
  signal write_fifo_dout      : std_logic_vector(0 to DATA_WIDTH-1);
291 
 
292 
  -----------------------------------------------------------------------------
293 
  -- Post-Scramble TX FIFO to PHY Layer
294 
  -----------------------------------------------------------------------------
295 
  signal tx_fifo_re      : std_logic;
296 
  signal tx_fifo_re_next : std_logic;
297 
  signal tx_fifo_we      : std_logic;
298 
  signal tx_fifo_empty   : std_logic;
299 
  signal tx_fifo_almost_empty : std_logic;
300 
  signal tx_fifo_full    : std_logic;
301 
  signal tx_fifo_prog_full  : std_logic;
302 
  signal tx_fifo_din     : std_logic_vector(0 to DATA_WIDTH-1);
303 
  signal tx_fifo_dout    : std_logic_vector(0 to DATA_WIDTH-1);
304 
  signal tx_fifo_data_count      : std_logic_vector(0 to 9);
305 
 
306 
  -----------------------------------------------------------------------------
307 
  -- Replay FIFO Signals
308 
  -----------------------------------------------------------------------------
309 
  signal replay_buffer_clear     : std_logic;
310 
  signal replay_buffer_clear_next: std_logic;
311 
 
312 
  -----------------------------------------------------------------------------
313 
  -- FIFO Declarations
314 
  -----------------------------------------------------------------------------
315 
   component read_write_fifo
316 
     port (
317 
        clk: IN std_logic;
318 
        rst: IN std_logic;
319 
        rd_en: IN std_logic;
320 
        din: IN std_logic_VECTOR(31 downto 0);
321 
        wr_en: IN std_logic;
322 
        dout: OUT std_logic_VECTOR(31 downto 0);
323 
        almost_empty: OUT std_logic;
324 
        empty: OUT std_logic;
325 
        full: OUT std_logic;
326 
        prog_full: OUT std_logic
327 
        );
328 
   end component;
329 
 
330 
   component rx_tx_fifo
331 
     port (
332 
        clk: IN std_logic;
333 
        rst: IN std_logic;
334 
        rd_en: IN std_logic;
335 
        din: IN std_logic_VECTOR(31 downto 0);
336 
        wr_en: IN std_logic;
337 
        dout: OUT std_logic_VECTOR(31 downto 0);
338 
        almost_empty: OUT std_logic;
339 
        empty: OUT std_logic;
340 
        full: OUT std_logic;
341 
        prog_full: OUT std_logic;
342 
        data_count: OUT std_logic_vector(9 downto 0)
343 
        );
344 
   end component;
345 
 
346 
  -----------------------------------------------------------------------------
347 
  -- SATA PHY Declaration
348 
  -----------------------------------------------------------------------------
349 
   component sata_phy
350 
     port (
351 
        oob_control_ila_control: in std_logic_vector(35 downto 0);
352 
        sata_phy_ila_control  : in  std_logic_vector(35 downto 0);
353 
        REFCLK_PAD_P_IN       : in  std_logic;     -- MGTCLKA,  clocks GTP_X0Y0-2
354 
        REFCLK_PAD_N_IN       : in  std_logic;    -- MGTCLKA
355 
        GTXRESET_IN           : in  std_logic;    -- GTP initialization
356 
        PLLLKDET_OUT_N        : out std_logic;
357 
        TXP0_OUT              : out std_logic;
358 
        TXN0_OUT              : out std_logic;
359 
        RXP0_IN               : in  std_logic;
360 
        RXN0_IN               : in  std_logic;
361 
        DCMLOCKED_OUT         : out std_logic;
362 
        LINKUP                : out std_logic;
363 
        LINKUP_led            : out std_logic;
364 
        sata_user_clk         : out std_logic;
365 
        GEN2_led              : out std_logic;
366 
        align_en_out          : out std_logic;
367 
        tx_datain             : in  std_logic_vector(DATA_WIDTH-1 downto 0);
368 
        tx_charisk_in         : in  std_logic;
369 
        rx_dataout            : out std_logic_vector(DATA_WIDTH-1 downto 0);
370 
        rx_charisk_out        : out std_logic_vector(3 downto 0);
371 
        CurrentState_out      : out std_logic_vector(7 downto 0);
372 
        rxelecidle_out        : out std_logic;
373 
        CLKIN_150             : in  std_logic
374 
      );
375 
   end component;
376 
 
377 
   component sata_rx_frame_ila
378 
    port (
379 
      control : in std_logic_vector(35 downto 0);
380 
      clk     : in std_logic;
381 
      trig0   : in std_logic_vector(3  downto 0);
382 
      trig1   : in std_logic_vector(31 downto 0);
383 
      trig2   : in std_logic_vector(7 downto 0);
384 
      trig3   : in std_logic_vector(3 downto 0);
385 
      trig4   : in std_logic_vector(3 downto 0);
386 
      trig5   : in std_logic_vector(7 downto 0);
387 
      trig6   : in std_logic_vector(31 downto 0);
388 
      trig7   : in std_logic_vector(31 downto 0);
389 
      trig8   : in std_logic_vector(31 downto 0);
390 
      trig9   : in std_logic_vector(31 downto 0);
391 
      trig10  : in std_logic_vector(31 downto 0);
392 
      trig11  : in std_logic_vector(7 downto 0);
393 
      trig12  : in std_logic_vector(15 downto 0);
394 
      trig13  : in std_logic_vector(15 downto 0);
395 
      trig14  : in std_logic_vector(15 downto 0);
396 
      trig15  : in std_logic_vector(31 downto 0)
397 
    );
398 
  end component;
399 
 
400 
 
401 
  component sata_tx_frame_ila
402 
    port (
403 
      control : in std_logic_vector(35 downto 0);
404 
      clk     : in std_logic;
405 
      trig0   : in std_logic_vector(3  downto 0);
406 
      trig1   : in std_logic_vector(31 downto 0);
407 
      trig2   : in std_logic_vector(31 downto 0);
408 
      trig3   : in std_logic_vector(31 downto 0);
409 
      trig4   : in std_logic_vector(3 downto 0);
410 
      trig5   : in std_logic_vector(31 downto 0);
411 
      trig6   : in std_logic_vector(31 downto 0);
412 
      trig7   : in std_logic_vector(31 downto 0);
413 
      trig8   : in std_logic_vector(15 downto 0);
414 
      trig9   : in std_logic_vector(15 downto 0);
415 
      trig10  : in std_logic_vector(31 downto 0);
416 
      trig11  : in std_logic_vector(31 downto 0);
417 
      trig12  : in std_logic_vector(31 downto 0);
418 
      trig13  : in std_logic_vector(15 downto 0);
419 
      trig14  : in std_logic_vector(15 downto 0);
420 
      trig15  : in std_logic_vector(9 downto 0)
421 
   );
422 
  end component;
423 
 
424 
-------------------------------------------------------------------------------
425 
-- BEGIN
426 
-------------------------------------------------------------------------------
427 
begin
428 
 
429 
-------------------------------------------------------------------------------
430 
-- LINK LAYER
431 
-------------------------------------------------------------------------------
432 
 
433 
  -----------------------------------------------------------------------------
434 
  -- PROCESS: MASTER_FSM_VALUE_PROC
435 
  -- PURPOSE: ChipScope State Indicator Signal
436 
  -----------------------------------------------------------------------------
437 
  MASTER_FSM_VALUE_PROC : process (master_fsm_curr) is
438 
  begin
439 
    case (master_fsm_curr) is
440 
      when idle               => master_fsm_value <= x"0";
441 
      when capture_dev_sign   => master_fsm_value <= x"1";
442 
      when wait_for_cmd       => master_fsm_value <= x"2";
443 
      when H2D_REG_FIS        => master_fsm_value <= x"3";
444 
      when D2H_DMA_ACT_FIS    => master_fsm_value <= x"4";
445 
      when H2D_DATA_FIS       => master_fsm_value <= x"5";
446 
      when D2H_DATA_FIS       => master_fsm_value <= x"6";
447 
      when D2H_REG_FIS        => master_fsm_value <= x"7";
448 
      when D2H_PIO_SETUP      => master_fsm_value <= x"8";
449 
      when dead               => master_fsm_value <= x"9";
450 
      when others             => master_fsm_value <= x"A";
451 
    end case;
452 
  end process MASTER_FSM_VALUE_PROC;
453 
 
454 
  -----------------------------------------------------------------------------
455 
  -- PROCESS: MASTER_FSM_STATE_PROC
456 
  -- PURPOSE: Registering Signals and Next State
457 
  -----------------------------------------------------------------------------
458 
  MASTER_FSM_STATE_PROC : process (sata_user_clk)
459 
  begin
460 
    if ((sata_user_clk'event) and (sata_user_clk = '1')) then
461 
      if (sw_reset = '1') then
462 
        --Initializing internal signals
463 
        master_fsm_curr         <= idle;
464 
        FIS_count_value         <= (others => '0');
465 
        start_rx                <= '0';
466 
        start_tx                <= '0';
467 
        new_cmd                 <= '0';
468 
        ready_for_cmd           <= '0';
469 
      else
470 
        -- Register all Current Signals to their _next Signals
471 
        master_fsm_curr         <= master_fsm_next;
472 
        FIS_count_value         <= FIS_count_value_next;
473 
        start_rx                <= start_rx_next;
474 
        start_tx                <= start_tx_next;
475 
        ready_for_cmd           <= ready_for_cmd_next;
476 
        if (new_cmd_in = '1') then
477 
            new_cmd                 <= '1';
478 
        else
479 
            new_cmd                 <= '0';
480 
        end if;
481 
      end if;
482 
    end if;
483 
  end process MASTER_FSM_STATE_PROC;
484 
 
485 
  -----------------------------------------------------------------------------
486 
  -- PROCESS: MASTER_FSM_LOGIC_PROC
487 
  -- PURPOSE: Implements a Sequence of FIS transfers for sending READ/WRITE sector
488 
  --          command. (Transport Layer)
489 
  -----------------------------------------------------------------------------
490 
  MASTER_FSM_LOGIC_PROC : process (master_fsm_curr, rx_done, tx_done, tx_err,
491 
                                   LINKUP, new_cmd, tx_sector_count
492 
                                   ) is
493 
  begin
494 
    -- Register _next to current signals
495 
    master_fsm_next          <= master_fsm_curr;
496 
    FIS_count_value_next     <= (others => '0');
497 
    start_rx_next            <= start_rx;
498 
    start_tx_next            <= start_tx;
499 
    ---------------------------------------------------------------------------
500 
    -- Finite State Machine
501 
    ---------------------------------------------------------------------------
502 
    case (master_fsm_curr) is
503 
 
504 
     -- x0
505 
     when idle =>
506 
         if (LINKUP = '1') then
507 
            start_rx_next    <=  '1';
508 
            master_fsm_next  <= capture_dev_sign;
509 
         end if;
510 
 
511 
     -- x1
512 
     when capture_dev_sign =>
513 
         start_rx_next    <=  '0';
514 
         if (rx_done = '1') then
515 
            master_fsm_next  <= wait_for_cmd;
516 
         end if;
517 
 
518 
     -- x2
519 
     when wait_for_cmd =>
520 
         if (new_cmd = '1') then
521 
            start_tx_next    <=  '1';
522 
            master_fsm_next  <= H2D_REG_FIS;
523 
         end if;
524 
 
525 
     -- x3
526 
     when H2D_REG_FIS =>
527 
         FIS_count_value_next <= COMMAND_FIS;
528 
         start_tx_next    <=  '0';
529 
         if (tx_done = '1') then
530 
            start_rx_next    <=  '1';
531 
            case (cmd_type) is
532 
              when IDEN_DEV =>
533 
                master_fsm_next   <= D2H_PIO_SETUP;
534 
              when READ_DMA =>
535 
                master_fsm_next   <= D2H_DATA_FIS;
536 
              when WRITE_DMA =>
537 
                master_fsm_next   <= D2H_DMA_ACT_FIS;
538 
              when others =>
539 
                master_fsm_next   <= D2H_REG_FIS;
540 
            end case;
541 
         end if;
542 
         if(tx_err = '1') then
543 
            start_tx_next    <=  '1';
544 
            master_fsm_next  <= H2D_REG_FIS;
545 
         end if;
546 
 
547 
     -- x4
548 
     when D2H_DMA_ACT_FIS =>
549 
         start_rx_next    <=  '0';
550 
         if (rx_done = '1') then
551 
            start_tx_next     <=  '1';
552 
            master_fsm_next   <= H2D_DATA_FIS;
553 
         end if;
554 
 
555 
     -- x5
556 
     when H2D_DATA_FIS =>
557 
         --FIS_count_value_next <= conv_std_logic_vector(((SECTOR_NDWORDS * sector_count) + 1), 16);
558 
         FIS_count_value_next <= (NDWORDS_PER_DATA_FIS + 1);
559 
         start_tx_next        <=  '0';
560 
         if ((tx_done = '1') or (tx_err = '1')) then
561 
            start_rx_next     <=  '1';
562 
            if (tx_sector_count >= conv_std_logic_vector(sector_count, 16)) then
563 
               master_fsm_next   <= D2H_REG_FIS;
564 
            else
565 
               master_fsm_next   <= D2H_DMA_ACT_FIS;
566 
            end if;
567 
         end if;
568 
 
569 
    -- x6
570 
     when D2H_DATA_FIS =>
571 
         start_rx_next    <=  '0';
572 
         if (rx_done = '1') then
573 
            if (cmd_type = READ_DMA) then
574 
               start_rx_next     <=  '1';
575 
               master_fsm_next   <= D2H_REG_FIS;
576 
            else
577 
               master_fsm_next   <= wait_for_cmd;
578 
            end if;
579 
         end if;
580 
 
581 
     -- x7
582 
     when D2H_REG_FIS =>
583 
         start_rx_next    <=  '0';
584 
         if (rx_done = '1') then
585 
            master_fsm_next   <= wait_for_cmd;
586 
         end if;
587 
 
588 
     -- x8
589 
     when D2H_PIO_SETUP =>
590 
         start_rx_next    <=  '0';
591 
         if (rx_done = '1') then
592 
            start_rx_next    <=  '1';
593 
            master_fsm_next  <= D2H_DATA_FIS;
594 
         end if;
595 
 
596 
     -- x9
597 
     when dead =>
598 
         master_fsm_next   <= dead;
599 
 
600 
     -- xA
601 
     when others =>
602 
         master_fsm_next   <= dead;
603 
 
604 
   end case;
605 
 end process MASTER_FSM_LOGIC_PROC;
606 
 
607 
 ready_for_cmd_next  <= '1' when (master_fsm_curr = wait_for_cmd) else '0';
608 
 ready_for_cmd_out   <= ready_for_cmd;
609 
 
610 
-----------------------------------------------------------------------------
611 
-- PROCESS: RX_FRAME_VALUE_PROC
612 
-- PURPOSE: ChipScope State Indicator Signal
613 
-----------------------------------------------------------------------------
614 
  RX_FRAME_VALUE_PROC : process (rx_frame_curr) is
615 
  begin
616 
    case (rx_frame_curr) is
617 
      when idle               => rx_frame_value <= x"0";
618 
      when send_R_RDY         => rx_frame_value <= x"1";
619 
      when send_R_IP          => rx_frame_value <= x"2";
620 
      when send_HOLD_ACK      => rx_frame_value <= x"3";
621 
      when send_R_OK          => rx_frame_value <= x"4";
622 
      when send_SYNC          => rx_frame_value <= x"5";
623 
      when wait_for_X_RDY     => rx_frame_value <= x"6";
624 
      when dead               => rx_frame_value <= x"7";
625 
      when others             => rx_frame_value <= x"8";
626 
    end case;
627 
  end process RX_FRAME_VALUE_PROC;
628 
 
629 
  -----------------------------------------------------------------------------
630 
  -- PROCESS: RX_FRAME_STATE_PROC
631 
  -- PURPOSE: Registering Signals and Next State
632 
  -----------------------------------------------------------------------------
633 
  RX_FRAME_STATE_PROC : process (sata_user_clk)
634 
  begin
635 
    if ((sata_user_clk'event) and (sata_user_clk = '1')) then
636 
      if (sw_reset = '1') then
637 
        --Initializing internal signals
638 
        rx_frame_curr           <= idle;
639 
        sync_count_rx           <= (others => '0');
640 
        rx_done                 <= '0';
641 
        rx_fifo_we              <= '0';
642 
        prim_type_rx            <= (others => '0');
643 
        ALIGN_det_r             <= '0';
644 
        ALIGN_det_r2            <= '0';
645 
        HOLD_det_r              <= '0';
646 
        HOLD_det_r2             <= '0';
647 
        HOLD_det_r3             <= '0';
648 
        HOLD_det_r4             <= '0';
649 
        TWO_HOLD_det_r          <= '0';
650 
      else
651 
        -- Register all Current Signals to their _next Signals
652 
        rx_frame_curr           <= rx_frame_next;
653 
        sync_count_rx           <= sync_count_rx_next;
654 
        rx_done                 <= rx_done_next;
655 
        rx_fifo_we              <= rx_fifo_we_next;
656 
        prim_type_rx            <= prim_type_rx_next;
657 
        ALIGN_det_r             <= ALIGN_det;
658 
        ALIGN_det_r2            <= ALIGN_det_r;
659 
        HOLD_det_r              <= HOLD_det;
660 
        HOLD_det_r2             <= HOLD_det_r;
661 
        HOLD_det_r3             <= HOLD_det_r2;
662 
        HOLD_det_r4             <= HOLD_det_r3;
663 
        TWO_HOLD_det_r          <= TWO_HOLD_det;
664 
      end if;
665 
    end if;
666 
  end process RX_FRAME_STATE_PROC;
667 
 
668 
  -----------------------------------------------------------------------------
669 
  -- PROCESS: RX_FRAME_LOGIC_PROC
670 
  -- PURPOSE: Receive FRAME from disk and unpack the FIS
671 
  -----------------------------------------------------------------------------
672 
  RX_FRAME_LOGIC_PROC : process (rx_frame_curr, sync_count_rx, ALIGN_det, HOLD_det,
673 
                        HOLD_stop_after_ALIGN_det,
674 
                        SOF_det, EOF_det, HOLD_start_det, HOLD_stop_det, SYNC_det,
675 
                        start_rx, LINKUP, rx_datain, rx_sector_count, sector_count
676 
                                ) is
677 
  begin
678 
    -- Register _next to current signals
679 
    rx_frame_next            <= rx_frame_curr;
680 
    sync_count_rx_next       <= sync_count_rx;
681 
    rx_done_next             <= rx_done;
682 
    prim_type_rx_next        <= prim_type_rx;
683 
    rx_fifo_we_next          <= '0';
684 
    ---------------------------------------------------------------------------
685 
    -- Finite State Machine
686 
    ---------------------------------------------------------------------------
687 
    case (rx_frame_curr) is
688 
 
689 
     -- x0
690 
     when idle =>
691 
         rx_done_next <= '0';
692 
         prim_type_rx_next <= SYNC;
693 
         if (start_rx = '1') then
694 
            --if (master_fsm_curr = capture_dev_sign) then
695 
               rx_frame_next  <= send_R_RDY;
696 
            --else
697 
              -- rx_frame_next  <= wait_for_X_RDY;
698 
            --end if;
699 
         end if;
700 
 
701 
     -- x6
702 
     --Wait for X_RDY before sending R_RDY
703 
     when wait_for_X_RDY =>
704 
         prim_type_rx_next <= SYNC;
705 
         if (X_RDY_det = '1') then
706 
            rx_frame_next  <= send_R_RDY;
707 
         end if;
708 
 
709 
     -- x1
710 
     when send_R_RDY =>
711 
     --Send R_RDY to get device signature
712 
         prim_type_rx_next <= R_RDY;
713 
 
714 
         if (SOF_det = '1') then
715 
            rx_frame_next  <= send_R_IP;
716 
         end if;
717 
 
718 
     -- x2
719 
     when send_R_IP =>
720 
     --Send R_IP to indicate Reception in Progress
721 
         prim_type_rx_next <= R_IP;
722 
 
723 
         rx_fifo_we_next   <= '1';
724 
 
725 
         if (ALIGN_det = '1' or HOLD_det = '1') then
726 
            rx_fifo_we_next   <= '0';
727 
         end if;
728 
 
729 
         if (EOF_det = '1') then
730 
            rx_fifo_we_next   <= '0';
731 
            rx_frame_next  <= send_R_OK;
732 
         end if;
733 
 
734 
         -- Check for 2 HOLD primitives followed by CONT which indicates FIS pause
735 
         if (HOLD_start_det = '1') then
736 
            rx_fifo_we_next   <= '0';
737 
            rx_frame_next  <= send_HOLD_ACK;
738 
         end if;
739 
 
740 
     -- x3
741 
     when send_HOLD_ACK =>
742 
     -- Send HOLD ACK to Acknowledge FIS pause
743 
         prim_type_rx_next <= HOLD_ACK;
744 
         if (HOLD_stop_after_ALIGN_det = '1') then
745 
            rx_fifo_we_next   <= '1';
746 
            rx_frame_next  <= send_R_IP;
747 
         end if;
748 
         if (HOLD_stop_det = '1') then
749 
            rx_frame_next  <= send_R_IP;
750 
         end if;
751 
 
752 
     -- x4
753 
     when send_R_OK =>
754 
         -- Send R_OK to indicate good frame
755 
         prim_type_rx_next <= R_OK;
756 
 
757 
         if (SYNC_det = '1') then
758 
            if (master_fsm_curr = D2H_DATA_FIS) then
759 
               if (rx_sector_count < conv_std_logic_vector(sector_count,16)) then
760 
                  rx_frame_next  <= send_R_RDY;
761 
               else
762 
                  rx_done_next   <= '1';
763 
                  rx_frame_next  <= idle;
764 
               end if;
765 
            else
766 
               rx_frame_next  <= send_SYNC;
767 
            end if;
768 
         end if;
769 
 
770 
     -- x5
771 
     when send_SYNC =>
772 
         -- Send SYNC to indicate host idle
773 
         prim_type_rx_next <= SYNC;
774 
 
775 
         if (sync_count_rx = SYNC_COUNT_VALUE) then
776 
            rx_done_next    <= '1';
777 
            sync_count_rx_next <= (others => '0');
778 
            rx_frame_next   <=  idle;
779 
         else
780 
            sync_count_rx_next <= sync_count_rx + 1;
781 
         end if;
782 
 
783 
     -- x6
784 
     when dead =>
785 
         rx_frame_next  <= dead;
786 
 
787 
     -- x7
788 
     when others =>
789 
         rx_frame_next  <= dead;
790 
 
791 
   end case;
792 
 end process RX_FRAME_LOGIC_PROC;
793 
 
794 
-- Counter for number of received sectors (used when number of RX sectors exceeds max 16 in one data FIS)
795 
  RX_SECTOR_CNT: process(sata_user_clk) is
796 
  begin
797 
       if ((sata_user_clk'event) and (sata_user_clk = '1')) then
798 
          if (sw_reset = '1' or new_cmd = '1') then
799 
                dword_count <= (others => '0');
800 
                rx_sector_count <= (others => '0');
801 
          elsif ((dword_count < (SECTOR_NDWORDS-1)) and (master_fsm_curr = D2H_DATA_FIS) and (rx_fifo_we_next = '1')) then
802 
                dword_count <= dword_count + 1;
803 
          elsif (dword_count = (SECTOR_NDWORDS-1)) then
804 
                dword_count <= (others => '0');
805 
                rx_sector_count <= rx_sector_count + 1;
806 
          elsif (EOF_det = '1') then
807 
                dword_count <= (others => '0');
808 
          else
809 
                dword_count <= dword_count;
810 
                rx_sector_count <= rx_sector_count;
811 
          end if;
812 
       end if;
813 
  end process RX_SECTOR_CNT;
814 
 
815 
 
816 
    -- DATA FIS DWORD Counter for stripping off DATA FIS header and CRC
817 
    DATA_FIS_DWORD_CNT: process(sata_user_clk) is
818 
     begin
819 
       if ((sata_user_clk'event) and (sata_user_clk = '1')) then
820 
          if (sw_reset = '1') then
821 
             DATA_FIS_dword_count <= (others => '0');
822 
             dword_count_init_value <= (others => '0');
823 
          elsif ((master_fsm_curr = D2H_DATA_FIS) and (DATA_FIS_dword_count < dword_count_value)) then
824 
             if (descrambler_dout_we = '1') then
825 
                DATA_FIS_dword_count <= DATA_FIS_dword_count + 1;
826 
             else
827 
                DATA_FIS_dword_count <= DATA_FIS_dword_count;
828 
             end if;
829 
          elsif ((DATA_FIS_dword_count = dword_count_value) and (master_fsm_curr = D2H_DATA_FIS)) then
830 
             if(dword_count_init_value >= NDWORDS_PER_DATA_FIS_32) then
831 
               dword_count_init_value <= (dword_count_init_value - NDWORDS_PER_DATA_FIS_32);
832 
             end if;
833 
             DATA_FIS_dword_count <= (others => '0');
834 
          else
835 
             DATA_FIS_dword_count <= (others => '0');
836 
          end if;
837 
 
838 
          if(new_cmd = '1') then
839 
             dword_count_init_value <= conv_std_logic_vector((SECTOR_NDWORDS * sector_count), 32);
840 
             dword_count_value <= (others => '0');
841 
          elsif(dword_count_init_value < NDWORDS_PER_DATA_FIS_32) then
842 
             dword_count_value <= dword_count_init_value(16 to 31) + conv_std_logic_vector(1,16);
843 
          elsif(dword_count_init_value >= NDWORDS_PER_DATA_FIS_32) then
844 
             dword_count_value <= NDWORDS_PER_DATA_FIS + 1;
845 
          end if;
846 
       end if;
847 
    end process DATA_FIS_DWORD_CNT;
848 
 
849 
  -----------------------------------------------------------------------------
850 
  -- PROCESS: TX_FRAME_VALUE_PROC
851 
  -- PURPOSE: ChipScope State Indicator Signal
852 
  -----------------------------------------------------------------------------
853 
  TX_FRAME_VALUE_PROC : process (tx_frame_curr) is
854 
  begin
855 
    case (tx_frame_curr) is
856 
      when idle              => tx_frame_value <= x"0";
857 
      when send_X_RDY        => tx_frame_value <= x"1";
858 
      when send_SOF          => tx_frame_value <= x"2";
859 
      when send_FIS          => tx_frame_value <= x"3";
860 
      when send_EOF          => tx_frame_value <= x"4";
861 
      when send_WTRM         => tx_frame_value <= x"5";
862 
      when send_SYNC         => tx_frame_value <= x"6";
863 
      when send_HOLD_ACK     => tx_frame_value <= x"7";
864 
      when send_HOLD         => tx_frame_value <= x"8";
865 
      when dead              => tx_frame_value <= x"9";
866 
      when others            => tx_frame_value <= x"A";
867 
    end case;
868 
  end process TX_FRAME_VALUE_PROC;
869 
 
870 
  -----------------------------------------------------------------------------
871 
  -- PROCESS: TX_FRAME_STATE_PROC
872 
  -- PURPOSE: Registering Signals and Next State
873 
  -----------------------------------------------------------------------------
874 
  TX_FRAME_STATE_PROC : process (sata_user_clk)
875 
  begin
876 
    if ((sata_user_clk'event) and (sata_user_clk = '1')) then
877 
      if (sw_reset = '1') then
878 
        --Initializing internal signals
879 
        tx_frame_curr           <= idle;
880 
        sync_count_tx           <= (others => '0');
881 
        rx_tx_state_sel         <= '0';
882 
        tx_done                 <= '0';
883 
        tx_fifo_re              <= '0';
884 
        frame_err               <= '0';
885 
        tx_err                  <= '0';
886 
        replay_buffer_clear     <= '0';
887 
        prim_type_tx            <= (others => '0');
888 
        FIS_word_count          <= (others => '0');
889 
        tx_sector_count         <= (others => '0');
890 
      elsif(new_cmd = '1') then
891 
        tx_sector_count         <= (others => '0');
892 
      else
893 
        -- Register all Current Signals to their _next Signals
894 
        tx_frame_curr           <= tx_frame_next;
895 
        sync_count_tx           <= sync_count_tx_next;
896 
        rx_tx_state_sel         <= rx_tx_state_sel_next;
897 
        tx_done                 <= tx_done_next;
898 
        tx_fifo_re              <= tx_fifo_re_next;
899 
        frame_err               <= frame_err_next;
900 
        tx_err                  <= tx_err_next;
901 
        replay_buffer_clear     <= replay_buffer_clear_next;
902 
        prim_type_tx            <= prim_type_tx_next;
903 
        FIS_word_count          <= FIS_word_count_next;
904 
        tx_sector_count         <= tx_sector_count_next;
905 
      end if;
906 
    end if;
907 
  end process TX_FRAME_STATE_PROC;
908 
 
909 
  -----------------------------------------------------------------------------
910 
  -- PROCESS: TX_FRAME_LOGIC_PROC
911 
  -- PURPOSE: Next State and Output Logic
912 
  -----------------------------------------------------------------------------
913 
  TX_FRAME_LOGIC_PROC : process (tx_frame_curr, FIS_word_count, sector_count,
914 
                            tx_sector_count,
915 
                            R_RDY_det, R_OK_det, sync_count_tx, start_tx,
916 
                            LINKUP, frame_err
917 
                                ) is
918 
  begin
919 
    -- Register _next to current signals
920 
    tx_frame_next            <= tx_frame_curr;
921 
    sync_count_tx_next       <= sync_count_tx;
922 
    rx_tx_state_sel_next     <= rx_tx_state_sel;
923 
    tx_fifo_re_next          <= tx_fifo_re;
924 
    tx_done_next             <= tx_done;
925 
    frame_err_next           <= frame_err;
926 
    tx_err_next              <= tx_err;
927 
    replay_buffer_clear_next <= replay_buffer_clear;
928 
    prim_type_tx_next        <= prim_type_tx;
929 
    FIS_word_count_next      <= FIS_word_count;
930 
    tx_sector_count_next     <= tx_sector_count;
931 
    tx_charisk_TX_FRAME      <= '1';
932 
    ---------------------------------------------------------------------------
933 
    -- Finite State Machine
934 
    ---------------------------------------------------------------------------
935 
    case (tx_frame_curr) is
936 
 
937 
     -- x0
938 
     when idle =>
939 
        tx_done_next              <= '0';
940 
        tx_err_next               <= '0';
941 
        replay_buffer_clear_next  <= '0';
942 
        prim_type_tx_next         <= SYNC;
943 
        FIS_word_count_next       <= (others => '0');
944 
 
945 
        if (start_tx = '1') then
946 
           rx_tx_state_sel_next    <= '1';
947 
           tx_frame_next           <= send_X_RDY;
948 
        end if;
949 
 
950 
     -- x1
951 
     when send_X_RDY =>
952 
         -- Send X_RDY to indicate host ready to transmit
953 
        prim_type_tx_next <= X_RDY;
954 
        if (R_RDY_det = '1') then
955 
            tx_frame_next  <= send_SOF;
956 
        end if;
957 
 
958 
     -- x2
959 
     when send_SOF =>
960 
     --Send SOF to indicate start of new FRAME
961 
         prim_type_tx_next <= SOF;
962 
         if (align_en_out = '0') then
963 
            tx_frame_next  <= send_FIS;
964 
         end if;
965 
 
966 
     -- x3
967 
     when send_FIS =>
968 
         tx_charisk_TX_FRAME      <= '0';
969 
     --Send FIS data
970 
         prim_type_tx_next <= FIS;
971 
         -- ALIGN primitives after 256 DWORDS
972 
         if (align_en_out = '1' or tx_fifo_almost_empty = '1') then
973 
           FIS_word_count_next  <= FIS_word_count;
974 
           tx_fifo_re_next   <= '0';
975 
         else
976 
           FIS_word_count_next  <= FIS_word_count + '1';
977 
           tx_fifo_re_next   <= '1';
978 
         end if;
979 
         -- Receive buffer empty condition
980 
         if (HOLD_start_det = '1') then
981 
            tx_frame_next  <= send_HOLD_ACK;
982 
         end if;
983 
         -- Transmit buffer empty condition
984 
         if (tx_fifo_almost_empty = '1') then
985 
            if (align_en_out = '0') then
986 
               tx_charisk_TX_FRAME  <= '1';
987 
               prim_type_tx_next <= HOLD;
988 
               tx_frame_next  <= send_HOLD;
989 
            end if;
990 
         end if;
991 
         -- Transmitted sector count
992 
         if(((conv_integer(FIS_word_count) mod SECTOR_NDWORDS)=0) and (conv_integer(FIS_word_count)>0) and (align_en_out='0') and (tx_fifo_almost_empty='0')) then
993 
            tx_sector_count_next <= tx_sector_count + 1;
994 
         else
995 
            tx_sector_count_next <= tx_sector_count;
996 
         end if;
997 
         if ((tx_sector_count >= conv_std_logic_vector(sector_count, 16)) or (FIS_word_count >= FIS_count_value)) then
998 
            if (align_en_out = '0') then
999 
               tx_charisk_TX_FRAME      <= '0';
1000 
               FIS_word_count_next <= (others => '0');
1001 
               tx_fifo_re_next   <= '1';
1002 
               prim_type_tx_next <= FIS;
1003 
               tx_frame_next  <= send_EOF;
1004 
            end if;
1005 
         end if;
1006 
 
1007 
     -- x7
1008 
     when send_HOLD_ACK =>
1009 
     -- Send HOLD ACK to Acknowledge FIS pause
1010 
         prim_type_tx_next <= HOLD_ACK;
1011 
         tx_fifo_re_next <= '0';
1012 
         --if (HOLD_stop_det = '1') then
1013 
         if (R_IP_det = '1') then
1014 
            tx_frame_next  <= send_FIS;
1015 
         end if;
1016 
 
1017 
     -- x8
1018 
     when send_HOLD =>
1019 
     -- Send HOLD to indicate transmit buffer empty
1020 
         prim_type_tx_next <= HOLD;
1021 
         tx_fifo_re_next <= '0';
1022 
         if (tx_fifo_empty = '0') then
1023 
            tx_frame_next  <= send_FIS;
1024 
         end if;
1025 
 
1026 
     -- x4
1027 
     when send_EOF =>
1028 
     --Send EOF to indicate end of FRAME
1029 
         tx_fifo_re_next <= '0';
1030 
         prim_type_tx_next <= EOF;
1031 
         if (align_en_out = '0') then
1032 
            tx_frame_next  <= send_WTRM;
1033 
         end if;
1034 
 
1035 
     -- x5
1036 
     when send_WTRM =>
1037 
         -- Send WTRM to indicate Waiting for Frame Termination
1038 
         prim_type_tx_next <= WTRM;
1039 
 
1040 
         if (R_OK_det = '1' or R_ERR_det = '1' or SYNC_det = '1') then
1041 
            if (R_ERR_det = '1' or SYNC_det = '1') then
1042 
                if (master_fsm_curr = H2D_REG_FIS) then
1043 
                   frame_err_next <= '1';
1044 
                else
1045 
                   frame_err_next <= '0';
1046 
                end if;
1047 
            end if;
1048 
            if (R_OK_det = '1') then
1049 
                replay_buffer_clear_next <= '1';
1050 
                frame_err_next <= '0';
1051 
            end if;
1052 
            tx_frame_next  <= send_SYNC;
1053 
         end if;
1054 
 
1055 
     -- x6
1056 
     when send_SYNC =>
1057 
         -- Send SYNC to indicate host idle
1058 
         prim_type_tx_next <= SYNC;
1059 
 
1060 
         if (sync_count_tx = SYNC_COUNT_VALUE) then
1061 
            sync_count_tx_next <= (others => '0');
1062 
            if (frame_err = '1') then
1063 
               tx_err_next   <= '1';
1064 
            else
1065 
               tx_done_next  <= '1';
1066 
            end if;
1067 
            rx_tx_state_sel_next  <= '0';
1068 
            tx_frame_next   <=  idle;
1069 
         else
1070 
            sync_count_tx_next <= sync_count_tx + 1;
1071 
         end if;
1072 
 
1073 
     -- x8
1074 
     when dead =>
1075 
         tx_frame_next  <= dead;
1076 
 
1077 
     -- x9
1078 
     when others =>
1079 
         tx_frame_next  <= dead;
1080 
 
1081 
   end case;
1082 
 end process TX_FRAME_LOGIC_PROC;
1083 
 
1084 
-- ASYNCHRONOUS MUXES
1085 
 tx_charisk_RX_FRAME <= '1';
1086 
 --tx_charisk_TX_FRAME <= '0' when (((tx_frame_curr = send_FIS) and (tx_fifo_almost_empty = '0')) or ((tx_frame_curr=send_FIS) and
1087 
        --              (tx_fifo_almost_empty = '1') and (master_fsm_curr = H2D_REG_FIS))) else '1';
1088 
 --tx_charisk_out      <= '0' when ((tx_frame_curr = send_FIS) or (prim_type_tx = PRIM_SCRM)) else tx_charisk_RX_FRAME when (rx_tx_state_sel = '0') else tx_charisk_TX_FRAME;
1089 
 tx_charisk_out      <= tx_charisk_RX_FRAME when (rx_tx_state_sel = '0') else tx_charisk_TX_FRAME;
1090 
 prim_type           <= prim_type_rx when (rx_tx_state_sel = '0') else prim_type_tx;
1091 
-- ASYNCHRONOUS MUXES
1092 
 
1093 
-- Primitive detection
1094 
ALIGN_det      <= '1' when (rx_datain = x"7B4A4ABC") else '0';
1095 
SYNC_det       <= '1' when (rx_datain = x"B5B5957C") else '0';
1096 
R_RDY_det      <= '1' when (rx_datain = x"4A4A957C") else '0';
1097 
R_IP_det       <= '1' when (rx_datain = x"5555B57C") else '0';
1098 
R_OK_det       <= '1' when (rx_datain = x"3535B57C") else '0';
1099 
R_ERR_det      <= '1' when (rx_datain = x"5656B57C") else '0';
1100 
SOF_det        <= '1' when (rx_datain = x"3737B57C") else '0';
1101 
EOF_det        <= '1' when (rx_datain = x"D5D5B57C") else '0';
1102 
X_RDY_det      <= '1' when (rx_datain = x"5757B57C") else '0';
1103 
WTRM_det       <= '1' when (rx_datain = x"5858B57C") else '0';
1104 
CONT_det       <= '1' when (rx_datain = x"9999AA7C") else '0';
1105 
HOLD_det       <= '1' when (rx_datain = x"D5D5AA7C") else '0';
1106 
HOLD_start_det <= '1' when (((TWO_HOLD_det_r = '1') and (CONT_det = '1'))  or (CORNER_CASE_HOLD = '1')) else '0';
1107 
TWO_HOLD_det   <= '1' when ((rx_datain = x"D5D5AA7C") and (HOLD_det_r = '1')) else '0';
1108 
HOLD_stop_det  <= '1' when ((rx_datain = x"D5D5AA7C") and (ALIGN_det_r = '0') and (TWO_HOLD_det = '0')) else '0';
1109 
HOLD_stop_after_ALIGN_det  <= '1' when ((HOLD_det_r = '1') and (ALIGN_det_r2 = '1') and (ALIGN_det_r = '0') and (TWO_HOLD_det = '0')) or ((TWO_HOLD_det_r = '1') and (CONT_det = '0'))  else '0';
1110 
-- Corner Case
1111 
-- ALIGN primitives are received between two HOLD primitives or between 2 HOLD and a CONT primitive
1112 
CORNER_CASE_HOLD <= '1' when ((CONT_det = '1') and (HOLD_det_r4 = '1')) else '0';
1113 
 
1114 
 
1115 
-- SATA Primitives
1116 
-- SYNC
1117 
tx_sync  <= x"B5B5957C";
1118 
 
1119 
 -- R_RDY
1120 
tx_r_rdy <= x"4A4A957C";
1121 
 
1122 
-- R_OK
1123 
tx_r_ok  <= x"3535B57C";
1124 
 
1125 
-- R_ERR
1126 
tx_r_err <= x"5656B57C";
1127 
 
1128 
-- R_IP
1129 
tx_r_ip  <= x"5555B57C";
1130 
 
1131 
-- X_RDY
1132 
tx_x_rdy <= x"5757B57C";
1133 
 
1134 
-- CONT
1135 
tx_cont  <= x"9999AA7C";
1136 
 
1137 
-- WTRM
1138 
tx_wtrm  <= x"5858B57C";
1139 
 
1140 
-- SOF
1141 
tx_sof   <= x"3737B57C";
1142 
 
1143 
-- EOF
1144 
tx_eof   <= x"D5D5B57C";
1145 
 
1146 
-- HOLD
1147 
tx_hold  <= x"D5D5AA7C";
1148 
 
1149 
-- HOLD_ACK
1150 
tx_hold_ack  <= x"9595AA7C";
1151 
 
1152 
-- Output Mux
1153 
OUTPUT_MUX_i: entity work.mux_161
1154 
generic map
1155 
    (
1156 
      DATA_WIDTH => 32
1157 
    )
1158 
port map
1159 
  (
1160 
    a  => tx_sync,
1161 
    b  => tx_r_rdy,
1162 
    c  => tx_r_ip,
1163 
    d  => tx_r_ok,
1164 
    e  => tx_r_err,
1165 
    f  => tx_x_rdy,
1166 
    g  => tx_wtrm,
1167 
    h  => tx_hold,
1168 
    i  => tx_hold_ack,
1169 
    j  => tx_cont,
1170 
    k  => tx_sof,
1171 
    l  => tx_eof,
1172 
    m  => tx_fifo_dout,
1173 
    --n  => tx_prim_scrm,
1174 
    n  => (others => '0'),
1175 
    o  => (others => '0'),
1176 
    p  => (others => '0'),
1177 
    sel=> output_mux_sel,
1178 
    output=> tx_dataout
1179 
  );
1180 
 
1181 
  output_mux_sel <= prim_type;
1182 
 
1183 
-------------------------------------------------------------------------------
1184 
-- LINK LAYER
1185 
-------------------------------------------------------------------------------
1186 
---------------------------------------------------------------------------
1187 
-- Pre-DeScramble RX FIFO from PHY Layer
1188 
---------------------------------------------------------------------------
1189 
    rx_fifo_din <= rx_datain;
1190 
    rx_fifo_re  <= descrambler_din_re_r;
1191 13 ashwin_men 
    rx_fifo_reset <= sw_reset or descrambler_reset;
1192 11 ashwin_men 
 
1193 
    RX_FIFO : rx_tx_fifo
1194 
        port map (
1195 
           clk    => sata_user_clk,
1196 13 ashwin_men 
           rst    => rx_fifo_reset,
1197 11 ashwin_men 
           rd_en  => rx_fifo_re,
1198 
           din    => rx_fifo_din,
1199 
           wr_en  => rx_fifo_we_next,
1200 
           dout   => rx_fifo_dout,
1201 
           almost_empty  => rx_fifo_almost_empty,
1202 
           empty  => rx_fifo_empty,
1203 
           full   => rx_fifo_full,
1204 
           prog_full   => rx_fifo_prog_full,
1205 
           data_count => rx_fifo_data_count
1206 
        );
1207 
 
1208 
---------------------------------------------------------------------------
1209 
-- DESCRAMBLER
1210 
---------------------------------------------------------------------------
1211 
    --descrambler_din(0 to 15)  <= rx_fifo_dout(16 to 31);
1212 
    --descrambler_din(16 to 31) <= rx_fifo_dout(0 to 15);
1213 
    descrambler_din     <= rx_fifo_dout;
1214 
    descrambler_en      <= not(rx_fifo_almost_empty);
1215 
    descrambler_reset   <= '1' when ((start_rx='1') or ((rx_frame_curr = send_R_OK) and (SYNC_det = '1'))) else '0';
1216 
 
1217 
    DESCRAMBLER_i: entity work.scrambler
1218 
        generic map(
1219 
           CHIPSCOPE    => FALSE
1220 
        )
1221 
        port map(
1222 
        -- Clock and Reset Signals
1223 
           clk          => sata_user_clk,
1224 
           reset        => descrambler_reset,
1225 
        -- ChipScope ILA / Trigger Signals
1226 
           scrambler_ila_control => descrambler_ila_control,
1227 
        ---------------------------------------
1228 
        -- Signals from/to Sata Link Layer FIFOs
1229 
           prim_scrambler => '0',
1230 
           scrambler_en   => descrambler_en,
1231 
           din_re         => descrambler_din_re,
1232 
           data_in        => descrambler_din,
1233 
           data_out       => descrambler_dout,
1234 
           dout_we        => descrambler_dout_we
1235 
       );
1236 
 
1237 
---------------------------------------------------------------------------
1238 
-- Post-DeScramble Read FIFO to Command Layer
1239 
---------------------------------------------------------------------------
1240 
    read_fifo_din <= descrambler_dout;
1241 
    read_fifo_we  <= descrambler_dout_we when ((master_fsm_curr = D2H_DATA_FIS) and (DATA_FIS_dword_count > 0) and (DATA_FIS_dword_count < dword_count_value)) else '0';
1242 
 
1243 
    READ_FIFO_i : read_write_fifo
1244 
        port map (
1245 
           clk    => sata_user_clk,
1246 
           rst    => sw_reset,
1247 
           rd_en  => read_fifo_re,
1248 
           din    => read_fifo_din,
1249 
           wr_en  => read_fifo_we,
1250 
           dout   => read_fifo_dout,
1251 
           almost_empty  => read_fifo_almost_empty,
1252 
           empty  => read_fifo_empty_i,
1253 
           full   => read_fifo_full,
1254 
           prog_full  => read_fifo_prog_full
1255 
        );
1256 
    -- Data Output to Command Layer
1257 
    sata_dout     <= read_fifo_dout;
1258 
    -- Input from Command Layer
1259 
    read_fifo_re  <= sata_dout_re;
1260 
 
1261 
    read_fifo_empty <= read_fifo_empty_i;
1262 
---------------------------------------------------------------------------
1263 
-- Pre-Scramble Write FIFO from Command Layer
1264 
---------------------------------------------------------------------------
1265 
    write_fifo_we   <= sata_din_we;
1266 
    write_fifo_din  <= sata_din;
1267 
    write_fifo_full <= write_fifo_prog_full;
1268 
    --write_fifo_re   <= scrambler_din_re_r when (scrambler_en = '1') else '0';
1269 
    write_fifo_re   <= scrambler_din_re_r when ((scrambler_en='1') and (scrambler_count_en_reg_fis='1')) or ((scrambler_count < scrambler_count_value) and (scrambler_count_en_data_fis = '1') and (write_fifo_empty = '0')) else '0';
1270 
 
1271 
    WRITE_FIFO_i : read_write_fifo
1272 
        port map (
1273 
           clk    => sata_user_clk,
1274 
           rst    => sw_reset,
1275 
           din    => write_fifo_din,
1276 
           wr_en  => write_fifo_we,
1277 
           dout   => write_fifo_dout,
1278 
           rd_en  => write_fifo_re,
1279 
           almost_empty  => write_fifo_almost_empty,
1280 
           empty  => write_fifo_empty,
1281 
           full   => write_fifo_full_i,
1282 
           prog_full   => write_fifo_prog_full
1283 
        );
1284 
 
1285 
---------------------------------------------------------------------------
1286 
-- CRC
1287 
---------------------------------------------------------------------------
1288 
    crc_reset   <=  scrambler_reset;
1289 
    crc_en      <=  scrambler_dout_we;
1290 
    crc_din     <=  write_fifo_dout;
1291 
 
1292 
    CRC_i : entity work.crc
1293 
      generic map (
1294 
         CHIPSCOPE => FALSE
1295 
      )
1296 
      port map (
1297 
        clk        => sata_user_clk,
1298 
        reset      => crc_reset,
1299 
        --crc_ila_control => crc_ila_control,
1300 
        crc_en     => crc_en,
1301 
        data_in    => crc_din,
1302 
        data_out   => crc_dout
1303 
      );
1304 
 
1305 
---------------------------------------------------------------------------
1306 
-- SCRAMBLER
1307 
---------------------------------------------------------------------------
1308 
    REGISTER_PROCESS : process(sata_user_clk) is
1309 
      begin
1310 
        if sata_user_clk'event and sata_user_clk = '1' then
1311 
          if sw_reset = '1' then
1312 
             scrambler_din_re_r     <= '0';
1313 
             descrambler_din_re_r   <= '0';
1314 
             crc_dout_r             <= (others => '0');
1315 
          else
1316 
             scrambler_din_re_r     <= scrambler_din_re;
1317 
             descrambler_din_re_r   <= descrambler_din_re;
1318 
             crc_dout_r             <= crc_dout;
1319 
          end if;
1320 
        end if;
1321 
      end process REGISTER_PROCESS;
1322 
 
1323 
 
1324 
    scrambler_count_en_reg_fis   <= '1' when (master_fsm_curr = H2D_REG_FIS) else '0';
1325 
    scrambler_count_en_data_fis  <= '1' when ((master_fsm_curr = H2D_DATA_FIS) or ((master_fsm_curr = D2H_DMA_ACT_FIS) and (tx_sector_count > 0)))  else '0';
1326 
 
1327 
    -- To disable scrambler after the REG FIS
1328 
    SCRAMBLER_CNT: process(sata_user_clk) is
1329 
     begin
1330 
       if ((sata_user_clk'event) and (sata_user_clk = '1')) then
1331 
          if (sw_reset = '1') then
1332 
              scrambler_count <= (others => '0');
1333 
              scrambler_count_init_value <= (others => '0');
1334 
              scrambler_count_value <= (others => '0');
1335 
              scrambler_reset_after_FIS <= '0';
1336 
          elsif ((scrambler_count < (REG_FIS_NDWORDS)) and (scrambler_count_en_reg_fis = '1')) then
1337 
              scrambler_count <= scrambler_count + 1;
1338 
          elsif ((scrambler_count < scrambler_count_value) and (scrambler_count_en_data_fis = '1') and (tx_fifo_we = '1') and (write_fifo_empty = '0')) then
1339 
              scrambler_count <= scrambler_count + 1;
1340 
              if (scrambler_count = NDWORDS_PER_DATA_FIS) then
1341 
                 scrambler_reset_after_FIS <= '1';
1342 
              end if;
1343 
          elsif (( scrambler_count = (NDWORDS_PER_DATA_FIS+1)) and (scrambler_count_en_data_fis = '1')) then
1344 
              scrambler_count_init_value <= (scrambler_count_init_value - NDWORDS_PER_DATA_FIS_32);
1345 
              scrambler_count <= (others => '0');
1346 
              scrambler_reset_after_FIS <= '0';
1347 
          else
1348 
              scrambler_count <= scrambler_count;
1349 
          end if;
1350 
 
1351 
          if (scrambler_reset = '1') then
1352 
              scrambler_count <= (others => '0');
1353 
              scrambler_reset_after_FIS <= '0';
1354 
          end if;
1355 
 
1356 
          if(new_cmd = '1') then
1357 
             scrambler_count_init_value <= conv_std_logic_vector((SECTOR_NDWORDS * sector_count), 32);
1358 
             scrambler_count_value <= (others => '0');
1359 
          elsif(scrambler_count_init_value < NDWORDS_PER_DATA_FIS_32) then
1360 
             scrambler_count_value <= scrambler_count_init_value(16 to 31) + conv_std_logic_vector(1,16);
1361 
          elsif(scrambler_count_init_value >= NDWORDS_PER_DATA_FIS_32) then
1362 
             scrambler_count_value <= NDWORDS_PER_DATA_FIS + 1;
1363 
          end if;
1364 
       end if;
1365 
    end process SCRAMBLER_CNT;
1366 
 
1367 
 
1368 
    scrambler_reset <= (sw_reset or new_cmd or scrambler_reset_after_FIS or (tx_done and scrambler_count_en_reg_fis)) ;
1369 
    scrambler_din   <=  crc_dout_r when ((scrambler_count = REG_FIS_NDWORDS) and (scrambler_count_en_reg_fis = '1')) or ((scrambler_count = scrambler_count_value) and (scrambler_count_en_data_fis = '1')) else write_fifo_dout;
1370 
    scrambler_en    <= not(write_fifo_empty) when (((scrambler_count_en_reg_fis = '1') and (scrambler_count < REG_FIS_NDWORDS))
1371 
--or ((scrambler_count_en_data_fis = '1') and (scrambler_count = NDWORDS_PER_DATA_FIS) and (tx_fifo_prog_full = '1'))
1372 
or ((scrambler_count_en_data_fis = '1') and (scrambler_count = (scrambler_count_value - '1'))))
1373 
else not(write_fifo_almost_empty) when ((scrambler_count_en_data_fis = '1') and (scrambler_count < scrambler_count_value) and (tx_fifo_prog_full = '0'))
1374 
else '0';
1375 
   -- Corner Case: tx_fifo_almost_full goes high when (scrambler_count = NDWORDS_PER_DATA_FIS)
1376 
 
1377 
    SCRAMBLER_i: entity work.scrambler
1378 
        generic map(
1379 
           CHIPSCOPE    => FALSE
1380 
        )
1381 
        port map(
1382 
        -- Clock and Reset Signals
1383 
           clk          => sata_user_clk,
1384 
           reset        => scrambler_reset,
1385 
        -- ChipScope ILA / Trigger Signals
1386 
           scrambler_ila_control => scrambler_ila_control,
1387 
        ---------------------------------------
1388 
        -- Signals from/to Sata Link Layer FIFOs
1389 
           prim_scrambler => '0',
1390 
           scrambler_en   => scrambler_en,
1391 
           din_re         => scrambler_din_re,
1392 
           data_in        => scrambler_din,
1393 
           data_out       => scrambler_dout,
1394 
           dout_we        => scrambler_dout_we
1395 
       );
1396 
 
1397 
   ---------------------------------------------------------------------------
1398 
   -- Post-Scramble TX FIFO to PHY Layer
1399 
   ---------------------------------------------------------------------------
1400 
    -- Input Signals from User Logic
1401 
    tx_fifo_din            <= scrambler_dout;
1402 
    tx_fifo_we             <= scrambler_dout_we;
1403 
 
1404 
    TX_FIFO: rx_tx_fifo
1405 
        port map (
1406 
           clk    => sata_user_clk,
1407 
           rst    => sw_reset,
1408 
           rd_en  => tx_fifo_re,
1409 
           din    => tx_fifo_din,
1410 
           wr_en  => tx_fifo_we,
1411 
           dout   => tx_fifo_dout,
1412 
           almost_empty  => tx_fifo_almost_empty,
1413 
           empty  => tx_fifo_empty,
1414 
           full   => tx_fifo_full,
1415 
           prog_full  => tx_fifo_prog_full,
1416 
           data_count => tx_fifo_data_count
1417 
        );
1418 
 
1419 
  ---------------------------------------------------------------------------
1420 
  --  Sata Phy Instantiation
1421 
  ---------------------------------------------------------------------------
1422 
    SATA_PHY_i : sata_phy
1423 
     port map (
1424 
        oob_control_ila_control=>  oob_control_ila_control,
1425 
        sata_phy_ila_control   =>  sata_phy_ila_control,
1426 
        REFCLK_PAD_P_IN        =>  REFCLK_PAD_P_IN  ,
1427 
        REFCLK_PAD_N_IN        =>  REFCLK_PAD_N_IN  ,
1428 
        GTXRESET_IN            =>  GTX_RESET_IN         ,
1429 
        PLLLKDET_OUT_N         =>  PLLLKDET_OUT_N ,
1430 
        TXP0_OUT               =>  TXP0_OUT,
1431 
        TXN0_OUT               =>  TXN0_OUT,
1432 
        RXP0_IN                =>  RXP0_IN ,
1433 
        RXN0_IN                =>  RXN0_IN ,
1434 
        DCMLOCKED_OUT          =>  DCMLOCKED_OUT,
1435 
        LINKUP                 =>  LINKUP   ,
1436 
        LINKUP_led             =>  LINKUP_led ,
1437 
        sata_user_clk          =>  sata_user_clk ,
1438 
        GEN2_led               =>  GEN2_led_i ,
1439 
        align_en_out           =>  align_en_out,
1440 
        tx_datain              =>  tx_dataout,
1441 
        tx_charisk_in          =>  tx_charisk_out,
1442 
        rx_dataout             =>  rx_datain,
1443 
        rx_charisk_out         =>  rx_charisk_in,
1444 
        CurrentState_out       =>  OOB_state,
1445 
        rxelecidle_out         =>  rxelecidle,
1446 
        CLKIN_150              =>  CLKIN_150
1447 
     );
1448 
 
1449 
     sata_user_clk_out         <= sata_user_clk;
1450 
 
1451 
 -----------------------------------------------------------------------------
1452 
 -- ILA Instantiations
1453 
 -----------------------------------------------------------------------------
1454 
 chipscope_gen_ila : if (CHIPSCOPE) generate
1455 
   SATA_RX_FRAME_ILA_i : sata_rx_frame_ila
1456 
    port map (
1457 
      control  => sata_rx_frame_ila_control,
1458 
      clk      => sata_user_clk,
1459 
      trig0    => rx_frame_value,
1460 
      trig1    => tx_dataout,
1461 
      trig2    => sync_count_rx,
1462 
      trig3    => master_fsm_value,
1463 
      trig4    => rx_charisk_in,
1464 
      trig5    => OOB_state,
1465 
      trig6    => rx_datain,
1466 
      trig7    => rx_fifo_dout,
1467 
      trig8    => read_fifo_din,
1468 
      trig9    => read_fifo_dout,
1469 
      trig10(0) => SOF_det,
1470 
      trig10(1) => EOF_det,
1471 
      trig10(2) => X_RDY_det,
1472 
      trig10(3) => WTRM_det,
1473 
      trig10(4) => HOLD_start_det,
1474 
      trig10(5) => HOLD_stop_det,
1475 
      trig10(6) => SYNC_det,
1476 
      trig10(7) => CONT_det,
1477 
      trig10(8) => ALIGN_det,
1478 
      trig10(9) => new_cmd,
1479 
      trig10(10) => start_rx,
1480 
      trig10(11) => rx_done,
1481 
      trig10(12) => descrambler_dout_we,
1482 
      trig10(13) => tx_charisk_out,
1483 
      trig10(14) => sw_reset,
1484 
      trig10(15) => LINKUP,
1485 
      trig10(16) => rx_fifo_we_next,
1486 
      trig10(17) => rx_fifo_re,
1487 
      trig10(18) => rx_fifo_empty,
1488 
      trig10(19) => descrambler_reset,
1489 
      trig10(20) => descrambler_en,
1490 
      trig10(21) => read_fifo_we,
1491 
      trig10(22) => read_fifo_re,
1492 
      trig10(23) => rx_fifo_almost_empty,
1493 
      trig10(24) => HOLD_det_r,
1494 
      trig10(25) => ALIGN_det_r,
1495 
      trig10(26) => TWO_HOLD_det,
1496 
      trig10(27) => read_fifo_empty_i,
1497 
      trig10(28) => TWO_HOLD_det_r,
1498 
      trig10(29) => HOLD_det,
1499 
      trig10(30) => HOLD_stop_after_ALIGN_det,
1500 
      trig10(31) => ALIGN_det_r2,
1501 
      trig11     => dword_count,
1502 
      trig12     => rx_sector_count,
1503 
      trig13     => DATA_FIS_dword_count,
1504 
      trig14     => dword_count_value,
1505 
      trig15     => dword_count_init_value
1506 
         );
1507 
 
1508 
 
1509 
   SATA_TX_FRAME_ILA_i : sata_tx_frame_ila
1510 
    port map (
1511 
      control  => sata_tx_frame_ila_control,
1512 
      clk      => sata_user_clk,
1513 
      trig0    => tx_frame_value,
1514 
      trig1    => tx_dataout,
1515 
      trig2    => rx_datain,
1516 
      trig3    => tx_fifo_dout,
1517 
      trig4    => master_fsm_value,
1518 
      trig5    => tx_fifo_din,
1519 
      trig6    => write_fifo_din,
1520 
      trig7    => write_fifo_dout,
1521 
      trig8    => FIS_word_count,
1522 
      trig9    => scrambler_count,
1523 
      trig10(0) => tx_fifo_we,
1524 
      trig10(1) => tx_fifo_re,
1525 
      trig10(2) => tx_fifo_full,
1526 
      trig10(3) => align_en_out,
1527 
      trig10(4) => SYNC_det,
1528 
      trig10(5) => R_RDY_det,
1529 
      trig10(6) => R_IP_det,
1530 
      trig10(7) => R_OK_det,
1531 
      trig10(8) => R_ERR_det,
1532 
      trig10(9) => start_tx,
1533 
      trig10(10) => tx_done,
1534 
      trig10(11) => tx_fifo_almost_empty,
1535 
      trig10(12) => tx_charisk_out,
1536 
      trig10(13) => tx_fifo_empty,
1537 
      trig10(14) => scrambler_din_re,
1538 
      trig10(15) => ALIGN_det,
1539 
      trig10(16) => HOLD_start_det,
1540 
      trig10(17) => HOLD_stop_det,
1541 
      trig10(18) => CONT_det,
1542 
      trig10(19) => write_fifo_prog_full,
1543 
      trig10(20) => tx_err,
1544 
      trig10(21) => write_fifo_almost_empty,
1545 
      trig10(22) => new_cmd,
1546 
      trig10(23) => scrambler_reset_after_FIS,
1547 
      trig10(24) => write_fifo_we,
1548 
      trig10(25) => write_fifo_re,
1549 
      trig10(26) => write_fifo_empty,
1550 
      trig10(27) => scrambler_en,
1551 
      trig10(28) => tx_fifo_prog_full,
1552 
      trig10(29) => scrambler_count_en_data_fis,
1553 
      trig10(30) => scrambler_reset,
1554 
      trig10(31) => crc_en,
1555 
      trig11     => scrambler_din,
1556 
      trig12     => crc_dout,
1557 
      trig13     => tx_sector_count,
1558 
      trig14     => scrambler_count_value,
1559 
      trig15     => tx_fifo_data_count
1560 
        );
1561 
 
1562 
      --trig14     => scrambler_count_init_value,
1563 
   end generate chipscope_gen_ila;
1564 
 
1565 
end BEHAV;

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