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Subversion Repositories sata_controller_core

[/] [sata_controller_core/] [trunk/] [sata2_bus_v1_00_a/] [base_system/] [system.mhs] - Blame information for rev 11

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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 12.2 Build EDK_MS2.63c
# Fri Aug  5 09:18:57 2011
# Target Board:  Xilinx Virtex 6 ML605 Evaluation Platform Rev D
# Family:    virtex6
# Device:    xc6vlx240t
# Package:   ff1156
# Speed Grade:  -1
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 100.0
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
 PARAMETER VERSION = 2.1.0
 
 
 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_Clk_pin = fpga_0_DDR3_SDRAM_DDR3_Clk_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin = fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_CE_pin = fpga_0_DDR3_SDRAM_DDR3_CE_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_CS_n_pin = fpga_0_DDR3_SDRAM_DDR3_CS_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_ODT_pin = fpga_0_DDR3_SDRAM_DDR3_ODT_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin = fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin = fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_WE_n_pin = fpga_0_DDR3_SDRAM_DDR3_WE_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin = fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin, DIR = O, VEC = [2:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_Addr_pin = fpga_0_DDR3_SDRAM_DDR3_Addr_pin, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_DQ_pin = fpga_0_DDR3_SDRAM_DDR3_DQ_pin, DIR = IO, VEC = [31:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_DM_pin = fpga_0_DDR3_SDRAM_DDR3_DM_pin, DIR = O, VEC = [3:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin = fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_DQS_pin = fpga_0_DDR3_SDRAM_DDR3_DQS_pin, DIR = IO, VEC = [3:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin = fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin, DIR = IO, VEC = [3:0]
 PORT fpga_0_clk_1_sys_clk_p_pin = dcm_clk_s, DIR = I, SIGIS = CLK, DIFFERENTIAL_POLARITY = P, CLK_FREQ = 200000000
 PORT fpga_0_clk_1_sys_clk_n_pin = dcm_clk_s, DIR = I, SIGIS = CLK, DIFFERENTIAL_POLARITY = N, CLK_FREQ = 200000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
# # SATA Push Button Reset and New Command
# PORT GTX_RESET_IN = GTX_RESET_IN, DIR = IO
# PORT NEW_CMD = NEW_CMD, DIR = I
# # SATA LEDs
 PORT TILE0_PLLLKDET_OUT_N = TILE0_PLLLKDET_OUT_N, DIR = O
 PORT DCMLOCKED_OUT = DCMLOCKED_OUT, DIR = O
 PORT LINKUP_led = LINKUP_led, DIR = O
 PORT GEN2_led = GEN2_led, DIR = O
# # SATA GTX
 PORT FMC_HPC_DP2_C2M_N = TXN0_OUT, DIR = O
 PORT FMC_HPC_DP2_C2M_P = TXP0_OUT, DIR = O
 PORT FMC_HPC_DP2_M2C_N = RXN0_IN, DIR = I
 PORT FMC_HPC_DP2_M2C_P = RXP0_IN, DIR = I
 
 
# PORT TILE0_REFCLK_PAD_P_IN_pin = TILE0_REFCLK_PAD_P_IN, DIR = I
# PORT TILE0_REFCLK_PAD_N_IN_pin = TILE0_REFCLK_PAD_N_IN, DIR = I
BEGIN npi_core
 PARAMETER INSTANCE = npi_core_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER CHIPSCOPE = true
 PARAMETER RAM_OFFSET = 0xd0
 PARAMETER BLOCK_SIZE = 512
 BUS_INTERFACE XIL_NPI = npi_complete_0_XIL_NPI
 PORT npi_if_ila_control = npi_if_ila_control
 PORT npi_if_tx_ila_control = npi_if_tx_ila_control
 PORT npi_ila_control = npi_ila_control
 PORT MPMC_Clk = clk_200_0000MHzMMCM0
 PORT user_clk = SATA_CORE_CLK_OUT
 PORT reset = sys_rst_s
 PORT NPI_CORE_DIN = SATA_CORE_DOUT
 PORT NPI_CORE_WE = SATA_CORE_DOUT_WE
 PORT NPI_CORE_DOUT = SATA_CORE_DIN
 PORT NPI_CORE_DOUT_WE = SATA_CORE_DIN_WE
 PORT SATA_CORE_FULL = SATA_CORE_FULL
 PORT req_type = NPI_CORE_REQ_TYPE
 PORT new_cmd = NPI_CORE_NEW_CMD
 PORT num_read_bytes_in = NPI_CORE_NUM_RD_BYTES
 PORT num_write_bytes_in = NPI_CORE_NUM_WR_BYTES
 PORT NPI_init_wr_addr_in = NPI_CORE_INIT_WR_ADDR
 PORT NPI_init_rd_addr_in = NPI_CORE_INIT_RD_ADDR
 PORT NPI_ready_for_cmd = NPI_CORE_READY_FOR_CMD
END
 
BEGIN sata_core
 PARAMETER INSTANCE = sata_core_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER CHIPSCOPE = true
 PARAMETER DATA_WIDTH = 32
 PARAMETER C_BASEADDR = 0x70000000
 PARAMETER C_HIGHADDR = 0x7000FFFF
 BUS_INTERFACE SPLB = mb_plb
 PORT cmd_layer_ila_control = cmd_layer_ila_control
 PORT sata_rx_frame_ila_control = sata_rx_frame_ila_control
 PORT sata_tx_frame_ila_control = sata_tx_frame_ila_control
 PORT sata_phy_ila_control = sata_phy_ila_control
 PORT oob_control_ila_control = oob_control_ila_control
# PORT scrambler_ila_control = scrambler_ila_control
# PORT descrambler_ila_control = descrambler_ila_control
 PORT user_logic_ila_control = user_logic_ila_control
# PORT TILE0_REFCLK_PAD_P_IN = TILE0_REFCLK_PAD_P_IN
# PORT TILE0_REFCLK_PAD_N_IN = TILE0_REFCLK_PAD_N_IN
 PORT TILE0_PLLLKDET_OUT_N = TILE0_PLLLKDET_OUT_N
 PORT DCMLOCKED_OUT = DCMLOCKED_OUT
 PORT LINKUP_led = LINKUP_led
 PORT GEN2_led = GEN2_led
 PORT TXP0_OUT = TXP0_OUT
 PORT TXN0_OUT = TXN0_OUT
 PORT RXP0_IN = RXP0_IN
 PORT RXN0_IN = RXN0_IN
 PORT RESET = sys_bus_reset
 PORT CLKIN_150 = clk_150_0000MHz
# SATA-NPI Interface
 PORT SATA_CORE_DOUT = SATA_CORE_DOUT
 PORT SATA_CORE_DOUT_WE = SATA_CORE_DOUT_WE
 PORT SATA_CORE_CLK_OUT = SATA_CORE_CLK_OUT
 PORT SATA_CORE_DIN = SATA_CORE_DIN
 PORT SATA_CORE_DIN_WE = SATA_CORE_DIN_WE
 PORT SATA_CORE_FULL = SATA_CORE_FULL
 PORT NPI_CORE_REQ_TYPE = NPI_CORE_REQ_TYPE
 PORT NPI_CORE_NEW_CMD = NPI_CORE_NEW_CMD
 PORT NPI_CORE_NUM_RD_BYTES = NPI_CORE_NUM_RD_BYTES
 PORT NPI_CORE_NUM_WR_BYTES = NPI_CORE_NUM_WR_BYTES
 PORT NPI_CORE_INIT_WR_ADDR = NPI_CORE_INIT_WR_ADDR
 PORT NPI_CORE_INIT_RD_ADDR = NPI_CORE_INIT_RD_ADDR
 PORT NPI_CORE_READY_FOR_CMD = NPI_CORE_READY_FOR_CMD
END
 
BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER HW_VER = 7.30.b
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
 PORT MB_RESET = mb_reset
END
 
BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.04.a
 PORT PLB_Clk = clk_100_0000MHzMMCM0
 PORT SYS_Rst = sys_bus_reset
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_100_0000MHzMMCM0
 PORT SYS_Rst = sys_bus_reset
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_100_0000MHzMMCM0
 PORT SYS_Rst = sys_bus_reset
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0003FFFF
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0003FFFF
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END
 
BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END
 
BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_Uart_1_RX_pin
 PORT TX = fpga_0_RS232_Uart_1_TX_pin
END
 
BEGIN mpmc
 PARAMETER INSTANCE = DDR3_SDRAM
 PARAMETER C_NUM_PORTS = 2
 PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y9
 PARAMETER C_MEM_TYPE = DDR3
 PARAMETER C_MEM_PARTNO = MT4JSF6464HY-1G1
 PARAMETER C_MEM_ODT_TYPE = 1
 PARAMETER C_MEM_REG_DIMM = 0
 PARAMETER C_MEM_CLK_WIDTH = 1
 PARAMETER C_MEM_ODT_WIDTH = 1
 PARAMETER C_MEM_CE_WIDTH = 1
 PARAMETER C_MEM_CS_N_WIDTH = 1
 PARAMETER C_MEM_DATA_WIDTH = 32
 PARAMETER C_MEM_NDQS_COL0 = 3
 PARAMETER C_MEM_NDQS_COL1 = 1
 PARAMETER C_MEM_DQS_LOC_COL0 = 0x000000000000000000000000000000020100
 PARAMETER C_MEM_DQS_LOC_COL1 = 0x000000000000000000000000000000000003
 PARAMETER C_PIM0_BASETYPE = 2
 PARAMETER HW_VER = 6.01.a
 PARAMETER C_MPMC_BASEADDR = 0x90000000
 PARAMETER C_MPMC_HIGHADDR = 0x9fffffff
 PARAMETER C_PIM1_BASETYPE = 4
 BUS_INTERFACE SPLB0 = mb_plb
 BUS_INTERFACE MPMC_PIM1 = npi_complete_0_XIL_NPI
 PORT MPMC_Clk0 = clk_200_0000MHzMMCM0
 PORT MPMC_Clk_200MHz = clk_200_0000MHzMMCM0
 PORT MPMC_Rst = sys_periph_reset
 PORT MPMC_Clk_Mem = clk_400_0000MHzMMCM0
 PORT MPMC_Clk_Rd_Base = clk_400_0000MHzMMCM0_nobuf_varphase
 PORT MPMC_DCM_PSEN = MPMC_DCM_PSEN
 PORT MPMC_DCM_PSINCDEC = MPMC_DCM_PSINCDEC
 PORT MPMC_DCM_PSDONE = MPMC_DCM_PSDONE
 PORT DDR3_Clk = fpga_0_DDR3_SDRAM_DDR3_Clk_pin
 PORT DDR3_Clk_n = fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin
 PORT DDR3_CE = fpga_0_DDR3_SDRAM_DDR3_CE_pin
 PORT DDR3_CS_n = fpga_0_DDR3_SDRAM_DDR3_CS_n_pin
 PORT DDR3_ODT = fpga_0_DDR3_SDRAM_DDR3_ODT_pin
 PORT DDR3_RAS_n = fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin
 PORT DDR3_CAS_n = fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin
 PORT DDR3_WE_n = fpga_0_DDR3_SDRAM_DDR3_WE_n_pin
 PORT DDR3_BankAddr = fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin
 PORT DDR3_Addr = fpga_0_DDR3_SDRAM_DDR3_Addr_pin
 PORT DDR3_DQ = fpga_0_DDR3_SDRAM_DDR3_DQ_pin
 PORT DDR3_DM = fpga_0_DDR3_SDRAM_DDR3_DM_pin
 PORT DDR3_Reset_n = fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin
 PORT DDR3_DQS = fpga_0_DDR3_SDRAM_DDR3_DQS_pin
 PORT DDR3_DQS_n = fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin
END
 
BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_CLKIN_FREQ = 200000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = MMCM0
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 200000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = MMCM0
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 400000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = MMCM0
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT3_FREQ = 400000000
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = MMCM0
 PARAMETER C_CLKOUT3_BUF = FALSE
 PARAMETER C_CLKOUT3_VARIABLE_PHASE = TRUE
 PARAMETER C_PSDONE_GROUP = MMCM0
 PARAMETER C_CLKOUT4_FREQ = 150000000
 PARAMETER C_CLKOUT4_PHASE = 0
 PARAMETER C_CLKOUT4_GROUP = NONE
 PARAMETER C_CLKOUT4_BUF = TRUE
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 4.00.a
 PORT CLKIN = dcm_clk_s
 PORT CLKOUT0 = clk_100_0000MHzMMCM0
 PORT CLKOUT1 = clk_200_0000MHzMMCM0
 PORT CLKOUT2 = clk_400_0000MHzMMCM0
 PORT CLKOUT3 = clk_400_0000MHzMMCM0_nobuf_varphase
 PORT CLKOUT4 = clk_150_0000MHz
 PORT PSCLK = clk_200_0000MHzMMCM0
 PORT PSEN = MPMC_DCM_PSEN
 PORT PSINCDEC = MPMC_DCM_PSINCDEC
 PORT PSDONE = MPMC_DCM_PSDONE
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
END
 
BEGIN mdm
 PARAMETER INSTANCE = mdm_0
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER HW_VER = 1.00.g
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END
 
BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 2.00.a
 PORT Slowest_sync_clk = clk_100_0000MHzMMCM0
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Dcm_locked = Dcm_all_locked
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END
 
BEGIN chipscope_icon
 PARAMETER INSTANCE = chipscope_icon_0
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_NUM_CONTROL_PORTS = 9
 PORT control0 = oob_control_ila_control
 PORT control1 = sata_phy_ila_control
 PORT control2 = sata_rx_frame_ila_control
 PORT control3 = sata_tx_frame_ila_control
 PORT control4 = cmd_layer_ila_control
 PORT control5 = user_logic_ila_control
 PORT control6 = npi_ila_control
 PORT control7 = npi_if_ila_control
 PORT control8 = npi_if_tx_ila_control
END
 

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Subversion Repositories sata_controller_core

[/] [sata_controller_core/] [trunk/] [sata2_bus_v1_00_a/] [base_system/] [system.mhs] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	ashwin_men
2			`# ##############################################################################`
3			`# Created by Base System Builder Wizard for Xilinx EDK 12.2 Build EDK_MS2.63c`
4			`# Fri Aug 5 09:18:57 2011`
5			`# Target Board: Xilinx Virtex 6 ML605 Evaluation Platform Rev D`
6			`# Family: virtex6`
7			`# Device: xc6vlx240t`
8			`# Package: ff1156`
9			`# Speed Grade: -1`
10			`# Processor number: 1`
11			`# Processor 1: microblaze_0`
12			`# System clock frequency: 100.0`
13			`# Debug Interface: On-Chip HW Debug Module`
14			`# ##############################################################################`
15			`PARAMETER VERSION = 2.1.0`
16
17
18			`PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I`
19			`PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O`
20			`PORT fpga_0_DDR3_SDRAM_DDR3_Clk_pin = fpga_0_DDR3_SDRAM_DDR3_Clk_pin, DIR = O`
21			`PORT fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin = fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin, DIR = O`
22			`PORT fpga_0_DDR3_SDRAM_DDR3_CE_pin = fpga_0_DDR3_SDRAM_DDR3_CE_pin, DIR = O`
23			`PORT fpga_0_DDR3_SDRAM_DDR3_CS_n_pin = fpga_0_DDR3_SDRAM_DDR3_CS_n_pin, DIR = O`
24			`PORT fpga_0_DDR3_SDRAM_DDR3_ODT_pin = fpga_0_DDR3_SDRAM_DDR3_ODT_pin, DIR = O`
25			`PORT fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin = fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin, DIR = O`
26			`PORT fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin = fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin, DIR = O`
27			`PORT fpga_0_DDR3_SDRAM_DDR3_WE_n_pin = fpga_0_DDR3_SDRAM_DDR3_WE_n_pin, DIR = O`
28			`PORT fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin = fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin, DIR = O, VEC = [2:0]`
29			`PORT fpga_0_DDR3_SDRAM_DDR3_Addr_pin = fpga_0_DDR3_SDRAM_DDR3_Addr_pin, DIR = O, VEC = [12:0]`
30			`PORT fpga_0_DDR3_SDRAM_DDR3_DQ_pin = fpga_0_DDR3_SDRAM_DDR3_DQ_pin, DIR = IO, VEC = [31:0]`
31			`PORT fpga_0_DDR3_SDRAM_DDR3_DM_pin = fpga_0_DDR3_SDRAM_DDR3_DM_pin, DIR = O, VEC = [3:0]`
32			`PORT fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin = fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin, DIR = O`
33			`PORT fpga_0_DDR3_SDRAM_DDR3_DQS_pin = fpga_0_DDR3_SDRAM_DDR3_DQS_pin, DIR = IO, VEC = [3:0]`
34			`PORT fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin = fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin, DIR = IO, VEC = [3:0]`
35			`PORT fpga_0_clk_1_sys_clk_p_pin = dcm_clk_s, DIR = I, SIGIS = CLK, DIFFERENTIAL_POLARITY = P, CLK_FREQ = 200000000`
36			`PORT fpga_0_clk_1_sys_clk_n_pin = dcm_clk_s, DIR = I, SIGIS = CLK, DIFFERENTIAL_POLARITY = N, CLK_FREQ = 200000000`
37			`PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1`
38			`# # SATA Push Button Reset and New Command`
39			`# PORT GTX_RESET_IN = GTX_RESET_IN, DIR = IO`
40			`# PORT NEW_CMD = NEW_CMD, DIR = I`
41			`# # SATA LEDs`
42			`PORT TILE0_PLLLKDET_OUT_N = TILE0_PLLLKDET_OUT_N, DIR = O`
43			`PORT DCMLOCKED_OUT = DCMLOCKED_OUT, DIR = O`
44			`PORT LINKUP_led = LINKUP_led, DIR = O`
45			`PORT GEN2_led = GEN2_led, DIR = O`
46			`# # SATA GTX`
47			`PORT FMC_HPC_DP2_C2M_N = TXN0_OUT, DIR = O`
48			`PORT FMC_HPC_DP2_C2M_P = TXP0_OUT, DIR = O`
49			`PORT FMC_HPC_DP2_M2C_N = RXN0_IN, DIR = I`
50			`PORT FMC_HPC_DP2_M2C_P = RXP0_IN, DIR = I`
51
52
53			`# PORT TILE0_REFCLK_PAD_P_IN_pin = TILE0_REFCLK_PAD_P_IN, DIR = I`
54			`# PORT TILE0_REFCLK_PAD_N_IN_pin = TILE0_REFCLK_PAD_N_IN, DIR = I`
55			`BEGIN npi_core`
56			`PARAMETER INSTANCE = npi_core_0`
57			`PARAMETER HW_VER = 1.00.a`
58			`PARAMETER CHIPSCOPE = true`
59			`PARAMETER RAM_OFFSET = 0xd0`
60			`PARAMETER BLOCK_SIZE = 512`
61			`BUS_INTERFACE XIL_NPI = npi_complete_0_XIL_NPI`
62			`PORT npi_if_ila_control = npi_if_ila_control`
63			`PORT npi_if_tx_ila_control = npi_if_tx_ila_control`
64			`PORT npi_ila_control = npi_ila_control`
65			`PORT MPMC_Clk = clk_200_0000MHzMMCM0`
66			`PORT user_clk = SATA_CORE_CLK_OUT`
67			`PORT reset = sys_rst_s`
68			`PORT NPI_CORE_DIN = SATA_CORE_DOUT`
69			`PORT NPI_CORE_WE = SATA_CORE_DOUT_WE`
70			`PORT NPI_CORE_DOUT = SATA_CORE_DIN`
71			`PORT NPI_CORE_DOUT_WE = SATA_CORE_DIN_WE`
72			`PORT SATA_CORE_FULL = SATA_CORE_FULL`
73			`PORT req_type = NPI_CORE_REQ_TYPE`
74			`PORT new_cmd = NPI_CORE_NEW_CMD`
75			`PORT num_read_bytes_in = NPI_CORE_NUM_RD_BYTES`
76			`PORT num_write_bytes_in = NPI_CORE_NUM_WR_BYTES`
77			`PORT NPI_init_wr_addr_in = NPI_CORE_INIT_WR_ADDR`
78			`PORT NPI_init_rd_addr_in = NPI_CORE_INIT_RD_ADDR`
79			`PORT NPI_ready_for_cmd = NPI_CORE_READY_FOR_CMD`
80			`END`
81
82			`BEGIN sata_core`
83			`PARAMETER INSTANCE = sata_core_0`
84			`PARAMETER HW_VER = 1.00.a`
85			`PARAMETER CHIPSCOPE = true`
86			`PARAMETER DATA_WIDTH = 32`
87			`PARAMETER C_BASEADDR = 0x70000000`
88			`PARAMETER C_HIGHADDR = 0x7000FFFF`
89			`BUS_INTERFACE SPLB = mb_plb`
90			`PORT cmd_layer_ila_control = cmd_layer_ila_control`
91			`PORT sata_rx_frame_ila_control = sata_rx_frame_ila_control`
92			`PORT sata_tx_frame_ila_control = sata_tx_frame_ila_control`
93			`PORT sata_phy_ila_control = sata_phy_ila_control`
94			`PORT oob_control_ila_control = oob_control_ila_control`
95			`# PORT scrambler_ila_control = scrambler_ila_control`
96			`# PORT descrambler_ila_control = descrambler_ila_control`
97			`PORT user_logic_ila_control = user_logic_ila_control`
98			`# PORT TILE0_REFCLK_PAD_P_IN = TILE0_REFCLK_PAD_P_IN`
99			`# PORT TILE0_REFCLK_PAD_N_IN = TILE0_REFCLK_PAD_N_IN`
100			`PORT TILE0_PLLLKDET_OUT_N = TILE0_PLLLKDET_OUT_N`
101			`PORT DCMLOCKED_OUT = DCMLOCKED_OUT`
102			`PORT LINKUP_led = LINKUP_led`
103			`PORT GEN2_led = GEN2_led`
104			`PORT TXP0_OUT = TXP0_OUT`
105			`PORT TXN0_OUT = TXN0_OUT`
106			`PORT RXP0_IN = RXP0_IN`
107			`PORT RXN0_IN = RXN0_IN`
108			`PORT RESET = sys_bus_reset`
109			`PORT CLKIN_150 = clk_150_0000MHz`
110			`# SATA-NPI Interface`
111			`PORT SATA_CORE_DOUT = SATA_CORE_DOUT`
112			`PORT SATA_CORE_DOUT_WE = SATA_CORE_DOUT_WE`
113			`PORT SATA_CORE_CLK_OUT = SATA_CORE_CLK_OUT`
114			`PORT SATA_CORE_DIN = SATA_CORE_DIN`
115			`PORT SATA_CORE_DIN_WE = SATA_CORE_DIN_WE`
116			`PORT SATA_CORE_FULL = SATA_CORE_FULL`
117			`PORT NPI_CORE_REQ_TYPE = NPI_CORE_REQ_TYPE`
118			`PORT NPI_CORE_NEW_CMD = NPI_CORE_NEW_CMD`
119			`PORT NPI_CORE_NUM_RD_BYTES = NPI_CORE_NUM_RD_BYTES`
120			`PORT NPI_CORE_NUM_WR_BYTES = NPI_CORE_NUM_WR_BYTES`
121			`PORT NPI_CORE_INIT_WR_ADDR = NPI_CORE_INIT_WR_ADDR`
122			`PORT NPI_CORE_INIT_RD_ADDR = NPI_CORE_INIT_RD_ADDR`
123			`PORT NPI_CORE_READY_FOR_CMD = NPI_CORE_READY_FOR_CMD`
124			`END`
125
126			`BEGIN microblaze`
127			`PARAMETER INSTANCE = microblaze_0`
128			`PARAMETER C_DEBUG_ENABLED = 1`
129			`PARAMETER HW_VER = 7.30.b`
130			`BUS_INTERFACE DLMB = dlmb`
131			`BUS_INTERFACE ILMB = ilmb`
132			`BUS_INTERFACE DPLB = mb_plb`
133			`BUS_INTERFACE IPLB = mb_plb`
134			`BUS_INTERFACE DEBUG = microblaze_0_mdm_bus`
135			`PORT MB_RESET = mb_reset`
136			`END`
137
138			`BEGIN plb_v46`
139			`PARAMETER INSTANCE = mb_plb`
140			`PARAMETER HW_VER = 1.04.a`
141			`PORT PLB_Clk = clk_100_0000MHzMMCM0`
142			`PORT SYS_Rst = sys_bus_reset`
143			`END`
144
145			`BEGIN lmb_v10`
146			`PARAMETER INSTANCE = ilmb`
147			`PARAMETER HW_VER = 1.00.a`
148			`PORT LMB_Clk = clk_100_0000MHzMMCM0`
149			`PORT SYS_Rst = sys_bus_reset`
150			`END`
151
152			`BEGIN lmb_v10`
153			`PARAMETER INSTANCE = dlmb`
154			`PARAMETER HW_VER = 1.00.a`
155			`PORT LMB_Clk = clk_100_0000MHzMMCM0`
156			`PORT SYS_Rst = sys_bus_reset`
157			`END`
158
159			`BEGIN lmb_bram_if_cntlr`
160			`PARAMETER INSTANCE = dlmb_cntlr`
161			`PARAMETER HW_VER = 2.10.b`
162			`PARAMETER C_BASEADDR = 0x00000000`
163			`PARAMETER C_HIGHADDR = 0x0003FFFF`
164			`BUS_INTERFACE SLMB = dlmb`
165			`BUS_INTERFACE BRAM_PORT = dlmb_port`
166			`END`
167
168			`BEGIN lmb_bram_if_cntlr`
169			`PARAMETER INSTANCE = ilmb_cntlr`
170			`PARAMETER HW_VER = 2.10.b`
171			`PARAMETER C_BASEADDR = 0x00000000`
172			`PARAMETER C_HIGHADDR = 0x0003FFFF`
173			`BUS_INTERFACE SLMB = ilmb`
174			`BUS_INTERFACE BRAM_PORT = ilmb_port`
175			`END`
176
177			`BEGIN bram_block`
178			`PARAMETER INSTANCE = lmb_bram`
179			`PARAMETER HW_VER = 1.00.a`
180			`BUS_INTERFACE PORTA = ilmb_port`
181			`BUS_INTERFACE PORTB = dlmb_port`
182			`END`
183
184			`BEGIN xps_uartlite`
185			`PARAMETER INSTANCE = RS232_Uart_1`
186			`PARAMETER C_BAUDRATE = 115200`
187			`PARAMETER C_DATA_BITS = 8`
188			`PARAMETER C_USE_PARITY = 0`
189			`PARAMETER C_ODD_PARITY = 0`
190			`PARAMETER HW_VER = 1.01.a`
191			`PARAMETER C_BASEADDR = 0x84000000`
192			`PARAMETER C_HIGHADDR = 0x8400ffff`
193			`BUS_INTERFACE SPLB = mb_plb`
194			`PORT RX = fpga_0_RS232_Uart_1_RX_pin`
195			`PORT TX = fpga_0_RS232_Uart_1_TX_pin`
196			`END`
197
198			`BEGIN mpmc`
199			`PARAMETER INSTANCE = DDR3_SDRAM`
200			`PARAMETER C_NUM_PORTS = 2`
201			`PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y9`
202			`PARAMETER C_MEM_TYPE = DDR3`
203			`PARAMETER C_MEM_PARTNO = MT4JSF6464HY-1G1`
204			`PARAMETER C_MEM_ODT_TYPE = 1`
205			`PARAMETER C_MEM_REG_DIMM = 0`
206			`PARAMETER C_MEM_CLK_WIDTH = 1`
207			`PARAMETER C_MEM_ODT_WIDTH = 1`
208			`PARAMETER C_MEM_CE_WIDTH = 1`
209			`PARAMETER C_MEM_CS_N_WIDTH = 1`
210			`PARAMETER C_MEM_DATA_WIDTH = 32`
211			`PARAMETER C_MEM_NDQS_COL0 = 3`
212			`PARAMETER C_MEM_NDQS_COL1 = 1`
213			`PARAMETER C_MEM_DQS_LOC_COL0 = 0x000000000000000000000000000000020100`
214			`PARAMETER C_MEM_DQS_LOC_COL1 = 0x000000000000000000000000000000000003`
215			`PARAMETER C_PIM0_BASETYPE = 2`
216			`PARAMETER HW_VER = 6.01.a`
217			`PARAMETER C_MPMC_BASEADDR = 0x90000000`
218			`PARAMETER C_MPMC_HIGHADDR = 0x9fffffff`
219			`PARAMETER C_PIM1_BASETYPE = 4`
220			`BUS_INTERFACE SPLB0 = mb_plb`
221			`BUS_INTERFACE MPMC_PIM1 = npi_complete_0_XIL_NPI`
222			`PORT MPMC_Clk0 = clk_200_0000MHzMMCM0`
223			`PORT MPMC_Clk_200MHz = clk_200_0000MHzMMCM0`
224			`PORT MPMC_Rst = sys_periph_reset`
225			`PORT MPMC_Clk_Mem = clk_400_0000MHzMMCM0`
226			`PORT MPMC_Clk_Rd_Base = clk_400_0000MHzMMCM0_nobuf_varphase`
227			`PORT MPMC_DCM_PSEN = MPMC_DCM_PSEN`
228			`PORT MPMC_DCM_PSINCDEC = MPMC_DCM_PSINCDEC`
229			`PORT MPMC_DCM_PSDONE = MPMC_DCM_PSDONE`
230			`PORT DDR3_Clk = fpga_0_DDR3_SDRAM_DDR3_Clk_pin`
231			`PORT DDR3_Clk_n = fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin`
232			`PORT DDR3_CE = fpga_0_DDR3_SDRAM_DDR3_CE_pin`
233			`PORT DDR3_CS_n = fpga_0_DDR3_SDRAM_DDR3_CS_n_pin`
234			`PORT DDR3_ODT = fpga_0_DDR3_SDRAM_DDR3_ODT_pin`
235			`PORT DDR3_RAS_n = fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin`
236			`PORT DDR3_CAS_n = fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin`
237			`PORT DDR3_WE_n = fpga_0_DDR3_SDRAM_DDR3_WE_n_pin`
238			`PORT DDR3_BankAddr = fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin`
239			`PORT DDR3_Addr = fpga_0_DDR3_SDRAM_DDR3_Addr_pin`
240			`PORT DDR3_DQ = fpga_0_DDR3_SDRAM_DDR3_DQ_pin`
241			`PORT DDR3_DM = fpga_0_DDR3_SDRAM_DDR3_DM_pin`
242			`PORT DDR3_Reset_n = fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin`
243			`PORT DDR3_DQS = fpga_0_DDR3_SDRAM_DDR3_DQS_pin`
244			`PORT DDR3_DQS_n = fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin`
245			`END`
246
247			`BEGIN clock_generator`
248			`PARAMETER INSTANCE = clock_generator_0`
249			`PARAMETER C_CLKIN_FREQ = 200000000`
250			`PARAMETER C_CLKOUT0_FREQ = 100000000`
251			`PARAMETER C_CLKOUT0_PHASE = 0`
252			`PARAMETER C_CLKOUT0_GROUP = MMCM0`
253			`PARAMETER C_CLKOUT0_BUF = TRUE`
254			`PARAMETER C_CLKOUT1_FREQ = 200000000`
255			`PARAMETER C_CLKOUT1_PHASE = 0`
256			`PARAMETER C_CLKOUT1_GROUP = MMCM0`
257			`PARAMETER C_CLKOUT1_BUF = TRUE`
258			`PARAMETER C_CLKOUT2_FREQ = 400000000`
259			`PARAMETER C_CLKOUT2_PHASE = 0`
260			`PARAMETER C_CLKOUT2_GROUP = MMCM0`
261			`PARAMETER C_CLKOUT2_BUF = TRUE`
262			`PARAMETER C_CLKOUT3_FREQ = 400000000`
263			`PARAMETER C_CLKOUT3_PHASE = 0`
264			`PARAMETER C_CLKOUT3_GROUP = MMCM0`
265			`PARAMETER C_CLKOUT3_BUF = FALSE`
266			`PARAMETER C_CLKOUT3_VARIABLE_PHASE = TRUE`
267			`PARAMETER C_PSDONE_GROUP = MMCM0`
268			`PARAMETER C_CLKOUT4_FREQ = 150000000`
269			`PARAMETER C_CLKOUT4_PHASE = 0`
270			`PARAMETER C_CLKOUT4_GROUP = NONE`
271			`PARAMETER C_CLKOUT4_BUF = TRUE`
272			`PARAMETER C_EXT_RESET_HIGH = 1`
273			`PARAMETER HW_VER = 4.00.a`
274			`PORT CLKIN = dcm_clk_s`
275			`PORT CLKOUT0 = clk_100_0000MHzMMCM0`
276			`PORT CLKOUT1 = clk_200_0000MHzMMCM0`
277			`PORT CLKOUT2 = clk_400_0000MHzMMCM0`
278			`PORT CLKOUT3 = clk_400_0000MHzMMCM0_nobuf_varphase`
279			`PORT CLKOUT4 = clk_150_0000MHz`
280			`PORT PSCLK = clk_200_0000MHzMMCM0`
281			`PORT PSEN = MPMC_DCM_PSEN`
282			`PORT PSINCDEC = MPMC_DCM_PSINCDEC`
283			`PORT PSDONE = MPMC_DCM_PSDONE`
284			`PORT RST = sys_rst_s`
285			`PORT LOCKED = Dcm_all_locked`
286			`END`
287
288			`BEGIN mdm`
289			`PARAMETER INSTANCE = mdm_0`
290			`PARAMETER C_MB_DBG_PORTS = 1`
291			`PARAMETER C_USE_UART = 1`
292			`PARAMETER C_UART_WIDTH = 8`
293			`PARAMETER HW_VER = 1.00.g`
294			`PARAMETER C_BASEADDR = 0x84400000`
295			`PARAMETER C_HIGHADDR = 0x8440ffff`
296			`BUS_INTERFACE SPLB = mb_plb`
297			`BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus`
298			`PORT Debug_SYS_Rst = Debug_SYS_Rst`
299			`END`
300
301			`BEGIN proc_sys_reset`
302			`PARAMETER INSTANCE = proc_sys_reset_0`
303			`PARAMETER C_EXT_RESET_HIGH = 1`
304			`PARAMETER HW_VER = 2.00.a`
305			`PORT Slowest_sync_clk = clk_100_0000MHzMMCM0`
306			`PORT Ext_Reset_In = sys_rst_s`
307			`PORT MB_Debug_Sys_Rst = Debug_SYS_Rst`
308			`PORT Dcm_locked = Dcm_all_locked`
309			`PORT MB_Reset = mb_reset`
310			`PORT Bus_Struct_Reset = sys_bus_reset`
311			`PORT Peripheral_Reset = sys_periph_reset`
312			`END`
313
314			`BEGIN chipscope_icon`
315			`PARAMETER INSTANCE = chipscope_icon_0`
316			`PARAMETER HW_VER = 1.04.a`
317			`PARAMETER C_NUM_CONTROL_PORTS = 9`
318			`PORT control0 = oob_control_ila_control`
319			`PORT control1 = sata_phy_ila_control`
320			`PORT control2 = sata_rx_frame_ila_control`
321			`PORT control3 = sata_tx_frame_ila_control`
322			`PORT control4 = cmd_layer_ila_control`
323			`PORT control5 = user_logic_ila_control`
324			`PORT control6 = npi_ila_control`
325			`PORT control7 = npi_if_ila_control`
326			`PORT control8 = npi_if_tx_ila_control`
327			`END`
328