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ashwin_men |
-- Copyright (C) 2012
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-- Ashwin A. Mendon
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--
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-- This file is part of SATA2 core.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------------
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-- ENTITY: sata_core
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-- Version: 1.0
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-- Author: Ashwin Mendon
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-- Description: The SATA core implements the Command, Transport and Link Layers of
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-- the SATA protocol and provides a Physical Layer Wrapper for the GTX
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-- transceivers. The Physical Layer Wrapper also includes an Out of Band
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-- Signaling (OOB) controller state machine which deals with initialization
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-- and synchronization of the SATA link. It can interface with SATA 2
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-- Winchester style Hard Disks as well as Flash-based Solid State Drives
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-- The core provides a simple interface to issue READ/WRITE sector commands.
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-- The DATA interface is 32-bit FIFO like.
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-- A 150 MHz input reference clock is needed for the GTX transceivers.
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-- The output data is delivered 4 bytes @ 75 MHz (user output clock)
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-- for a theoretical peak bandwidth of 300 MB/s (SATA 2).
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--
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--
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-- PORTS:
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-- Command, Control and Status --
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-- ready_for_cmd : When asserted, SATA core is ready to execute new command.
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-- This signal goes low after new_cmd is asserted.
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-- It also serves as the command done signal
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-- new_cmd : Asserted for one clock cycle to start a request
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-- cmd_type : "01" for READ request and "10" for WRITE request
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-- sector_count : Number of sectors requested by user
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-- sector_addr : Starting address of request
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-- Data and User Clock --
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-- sata_din : Data from user to Write to Disk
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-- sata_din_we : Write Enable to SATA Core when FULL is low
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-- sata_core_full : SATA Core Full- de-assert WE
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-- sata_dout : Data output from SATA Core
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-- sata_dout_re : Read Enable from SATA asserted when EMPTY is low
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-- sata_core_empty : SATA Core Empty- de-assert RE
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-- SATA_USER_DATA_CLK_IN : SATA Core Write Clock
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-- SATA_USER_DATA_CLK_OUT : SATA Core Read Clock
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-- sata_timer : SATA core timer output to check performance
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--PHY Signals--
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-- CLKIN_150 : 150 Mhz input reference clock for the GTX transceivers
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-- reset : Resets GTX and SATA core; can be tied to a software reset
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-- LINKUP : Indicates Link Initialization done (OOB) and SATA link is up
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--GTX transmit/receive pins: Connected to the FMC_HPC pins on a ML605 board
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-- TXP0_OUT, TXN0_OUT, RXP0_IN, RXN0_IN
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-----------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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entity sata_core is
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generic(
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CHIPSCOPE : boolean := false;
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DATA_WIDTH : natural := 32
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);
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port(
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-- ChipScope ILA / Trigger Signals
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sata_rx_frame_ila_control : in std_logic_vector(35 downto 0);
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sata_tx_frame_ila_control : in std_logic_vector(35 downto 0);
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sata_phy_ila_control : in std_logic_vector(35 downto 0);
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oob_control_ila_control : in std_logic_vector(35 downto 0);
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cmd_layer_ila_control : in std_logic_vector(35 downto 0);
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scrambler_ila_control : in std_logic_vector(35 downto 0);
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descrambler_ila_control : in std_logic_vector(35 downto 0);
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---------------------------------------
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-- SATA Interface -----
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-- Command, Control and Status --
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ready_for_cmd : out std_logic;
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new_cmd : in std_logic;
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cmd_type : in std_logic_vector(1 downto 0);
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sector_count : in std_logic_vector(31 downto 0);
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sector_addr : in std_logic_vector(31 downto 0);
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-- Data and User Clock --
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sata_din : in std_logic_vector(31 downto 0);
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sata_din_we : in std_logic;
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sata_core_full : out std_logic;
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sata_dout : out std_logic_vector(31 downto 0);
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sata_dout_re : in std_logic;
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sata_core_empty : out std_logic;
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SATA_USER_DATA_CLK_IN : in std_logic;
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SATA_USER_DATA_CLK_OUT : out std_logic;
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-- Timer --
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sata_timer : out std_logic_vector(31 downto 0);
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-- PHY Signals
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-- Clock and Reset Signals
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CLKIN_150 : in std_logic;
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reset : in std_logic;
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LINKUP : out std_logic;
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TXP0_OUT : out std_logic;
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TXN0_OUT : out std_logic;
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RXP0_IN : in std_logic;
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RXN0_IN : in std_logic;
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PLLLKDET_OUT_N : out std_logic;
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DCMLOCKED_OUT : out std_logic
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);
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end sata_core;
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-------------------------------------------------------------------------------
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-- ARCHITECTURE
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-------------------------------------------------------------------------------
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architecture BEHAV of sata_core is
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-- Sata Phy
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signal sata_user_clk : std_logic;
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--signal GTXRESET : std_logic;
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signal LINKUP_i : std_logic;
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-- Sata Phy
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signal REFCLK_PAD_P_IN_i : std_logic;
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signal REFCLK_PAD_N_IN_i : std_logic;
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-- COMMAND LAYER / LINK LAYER SIGNALS
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signal ll_ready_for_cmd_i : std_logic;
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signal sata_ready_for_cmd_i : std_logic;
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signal ll_cmd_start : std_logic;
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signal ll_cmd_type : std_logic_vector(1 downto 0);
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signal ll_dout : std_logic_vector(31 downto 0);
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signal ll_dout_we : std_logic;
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signal ll_din : std_logic_vector(31 downto 0);
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signal ll_din_re : std_logic;
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signal sector_count_int : integer;
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-- User FIFO signals
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signal user_din_re : std_logic;
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signal user_fifo_dout : std_logic_vector(31 downto 0);
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signal user_fifo_full : std_logic;
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signal user_fifo_prog_full : std_logic;
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signal user_fifo_empty : std_logic;
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signal write_fifo_full_i : std_logic;
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signal read_fifo_empty : std_logic;
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-- USER FIFO DECLARATION
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component user_fifo
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port (
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rst: IN std_logic;
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wr_clk: IN std_logic;
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din: IN std_logic_VECTOR(31 downto 0);
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wr_en: IN std_logic;
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rd_clk: IN std_logic;
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rd_en: IN std_logic;
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dout: OUT std_logic_VECTOR(31 downto 0);
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full: OUT std_logic;
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prog_full: OUT std_logic;
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empty: OUT std_logic);
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end component;
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-------------------------------------------------------------------------------
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-- BEGIN
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-------------------------------------------------------------------------------
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begin
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--- User Logic Fifo for writing data ---
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USER_FIFO_i : user_fifo
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port map (
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rst => reset,
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wr_clk => SATA_USER_DATA_CLK_IN,
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din => sata_din,
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wr_en => sata_din_we,
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rd_clk => sata_user_clk,
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dout => user_fifo_dout,
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rd_en => user_din_re,
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full => user_fifo_full,
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prog_full => user_fifo_prog_full,
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empty => user_fifo_empty);
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-- SATA Core Output Signals
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ready_for_cmd <= sata_ready_for_cmd_i;
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--sata_core_full <= write_fifo_full_i;
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sata_core_full <= user_fifo_prog_full;
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sata_core_empty <= read_fifo_empty;
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SATA_USER_DATA_CLK_OUT <= sata_user_clk;
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LINKUP <= LINKUP_i;
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-----------------------------------------------------------------------------
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-- Command Layer Instance
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-----------------------------------------------------------------------------
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COMMAND_LAYER_i : entity work.command_layer
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generic map
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(
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CHIPSCOPE => CHIPSCOPE
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)
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port map
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(
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-- ChipScope Signal
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cmd_layer_ila_control => cmd_layer_ila_control,
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-- Clock and Reset Signals
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sw_reset => reset,
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clk => sata_user_clk,
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new_cmd => new_cmd,
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cmd_done => sata_ready_for_cmd_i,
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cmd_type => cmd_type,
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sector_count => sector_count,
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sector_addr => sector_addr,
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user_din => user_fifo_dout,
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user_din_re_out => user_din_re,
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user_dout => sata_dout,
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user_dout_re => sata_dout_re,
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write_fifo_full => write_fifo_full_i,
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user_fifo_empty => user_fifo_empty,
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user_fifo_full => user_fifo_prog_full,
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sector_timer_out => sata_timer,
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-- Signals from/to Link Layer
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ll_ready_for_cmd => ll_ready_for_cmd_i,
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ll_cmd_start => ll_cmd_start,
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ll_cmd_type => ll_cmd_type,
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ll_dout => ll_dout,
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ll_dout_we => ll_dout_we,
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ll_din => ll_din,
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ll_din_re => ll_din_re
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);
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------------------------------------------
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-- Sata Link Layer Module Instance
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------------------------------------------
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sector_count_int <= conv_integer(sector_count);
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SATA_LINK_LAYER_i: entity work.sata_link_layer
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generic map(
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CHIPSCOPE => CHIPSCOPE,
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DATA_WIDTH => DATA_WIDTH
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)
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port map(
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-- Clock and Reset Signals
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CLKIN_150 => CLKIN_150,
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sw_reset => reset,
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-- ChipScope ILA / Trigger Signals
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sata_rx_frame_ila_control => sata_rx_frame_ila_control ,
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sata_tx_frame_ila_control => sata_tx_frame_ila_control ,
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oob_control_ila_control => oob_control_ila_control,
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sata_phy_ila_control => sata_phy_ila_control,
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scrambler_ila_control => scrambler_ila_control,
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descrambler_ila_control => descrambler_ila_control,
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---------------------------------------
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-- Ports from/to User Logic
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read_fifo_empty => read_fifo_empty,
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write_fifo_full => write_fifo_full_i,
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GTX_RESET_IN => reset,
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sector_count => sector_count_int,
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sata_user_clk_out => sata_user_clk,
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-- Ports from/to Command Layer
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ready_for_cmd_out => ll_ready_for_cmd_i,
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new_cmd_in => ll_cmd_start,
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cmd_type => ll_cmd_type,
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sata_din => ll_dout,
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sata_din_we => ll_dout_we,
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sata_dout => ll_din,
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sata_dout_re => ll_din_re,
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---------------------------------------
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-- Ports to SATA PHY
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REFCLK_PAD_P_IN => REFCLK_PAD_P_IN_i,
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REFCLK_PAD_N_IN => REFCLK_PAD_N_IN_i,
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TXP0_OUT => TXP0_OUT,
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TXN0_OUT => TXN0_OUT,
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RXP0_IN => RXP0_IN,
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RXN0_IN => RXN0_IN,
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PLLLKDET_OUT_N => PLLLKDET_OUT_N,
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DCMLOCKED_OUT => DCMLOCKED_OUT,
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LINKUP_led => LINKUP_i
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);
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end BEHAV;
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