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//////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version : 1.11
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// \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
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// / / Filename : sata_s6_sata1_gtp_tile.v
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// /___/ /\
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// \ \ / \
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// \___\/\___\
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//
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//
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// Module sata_s6_sata1_gtp_tile (a GTPA1_DUAL Tile Wrapper)
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// Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
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//
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//
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// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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`timescale 1ns / 1ps
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//***************************** Entity Declaration ****************************
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module sata_s6_sata1_gtp_tile #
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(
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// Simulation attributes
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parameter TILE_SIM_GTPRESET_SPEEDUP = 0, // Set to 1 to speed up sim reset
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parameter TILE_CLK25_DIVIDER_0 = 6,
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parameter TILE_CLK25_DIVIDER_1 = 6,
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parameter TILE_PLL_DIVSEL_FB_0 = 2,
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parameter TILE_PLL_DIVSEL_FB_1 = 2,
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parameter TILE_PLL_DIVSEL_REF_0 = 1,
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parameter TILE_PLL_DIVSEL_REF_1 = 1,
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//
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parameter TILE_PLL_SOURCE_0 = "PLL0",
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parameter TILE_PLL_SOURCE_1 = "PLL1"
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)
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(
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//---------------------- Loopback and Powerdown Ports ----------------------
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input [2:0] LOOPBACK0_IN,
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input [2:0] LOOPBACK1_IN,
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//------------------------------- PLL Ports --------------------------------
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input CLK00_IN,
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input CLK01_IN,
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input GTPRESET0_IN,
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input GTPRESET1_IN,
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output PLLLKDET0_OUT,
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output PLLLKDET1_OUT,
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output RESETDONE0_OUT,
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output RESETDONE1_OUT,
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//--------------------- Receive Ports - 8b10b Decoder ----------------------
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output [1:0] RXCHARISCOMMA0_OUT,
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output [1:0] RXCHARISCOMMA1_OUT,
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output [1:0] RXCHARISK0_OUT,
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output [1:0] RXCHARISK1_OUT,
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output [1:0] RXDISPERR0_OUT,
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output [1:0] RXDISPERR1_OUT,
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output [1:0] RXNOTINTABLE0_OUT,
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output [1:0] RXNOTINTABLE1_OUT,
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//-------------------- Receive Ports - Clock Correction --------------------
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output [2:0] RXCLKCORCNT0_OUT,
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output [2:0] RXCLKCORCNT1_OUT,
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//------------- Receive Ports - Comma Detection and Alignment --------------
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output RXBYTEISALIGNED0_OUT,
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output RXBYTEISALIGNED1_OUT,
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input RXENMCOMMAALIGN0_IN,
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input RXENMCOMMAALIGN1_IN,
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input RXENPCOMMAALIGN0_IN,
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input RXENPCOMMAALIGN1_IN,
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//----------------- Receive Ports - RX Data Path interface -----------------
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output [15:0] RXDATA0_OUT,
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output [15:0] RXDATA1_OUT,
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output RXRECCLK0_OUT,
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output RXRECCLK1_OUT,
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input RXRESET0_IN,
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input RXRESET1_IN,
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input RXUSRCLK0_IN,
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input RXUSRCLK1_IN,
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input RXUSRCLK20_IN,
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input RXUSRCLK21_IN,
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//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
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input GATERXELECIDLE0_IN,
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input GATERXELECIDLE1_IN,
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input IGNORESIGDET0_IN,
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input IGNORESIGDET1_IN,
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output RXELECIDLE0_OUT,
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output RXELECIDLE1_OUT,
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input [1:0] RXEQMIX0_IN,
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input [1:0] RXEQMIX1_IN,
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input RXN0_IN,
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input RXN1_IN,
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input RXP0_IN,
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input RXP1_IN,
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//--------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
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output [2:0] RXSTATUS0_OUT,
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output [2:0] RXSTATUS1_OUT,
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//-------------------------- TX/RX Datapath Ports --------------------------
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output [1:0] GTPCLKOUT0_OUT,
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output [1:0] GTPCLKOUT1_OUT,
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//----------------- Transmit Ports - 8b10b Encoder Control -----------------
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input [1:0] TXCHARISK0_IN,
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input [1:0] TXCHARISK1_IN,
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//---------------- Transmit Ports - TX Data Path interface -----------------
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input [15:0] TXDATA0_IN,
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input [15:0] TXDATA1_IN,
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output TXOUTCLK0_OUT,
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output TXOUTCLK1_OUT,
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input TXRESET0_IN,
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input TXRESET1_IN,
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input TXUSRCLK0_IN,
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input TXUSRCLK1_IN,
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input TXUSRCLK20_IN,
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input TXUSRCLK21_IN,
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//------------- Transmit Ports - TX Driver and OOB signalling --------------
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input [3:0] TXDIFFCTRL0_IN,
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input [3:0] TXDIFFCTRL1_IN,
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output TXN0_OUT,
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output TXN1_OUT,
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output TXP0_OUT,
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output TXP1_OUT,
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input [2:0] TXPREEMPHASIS0_IN,
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input [2:0] TXPREEMPHASIS1_IN,
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//--------------- Transmit Ports - TX Ports for PCI Express ----------------
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input TXELECIDLE0_IN,
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input TXELECIDLE1_IN,
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//------------------- Transmit Ports - TX Ports for SATA -------------------
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input TXCOMSTART0_IN,
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input TXCOMSTART1_IN,
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input TXCOMTYPE0_IN,
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input TXCOMTYPE1_IN
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);
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//***************************** Wire Declarations *****************************
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// ground and vcc signals
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wire tied_to_ground_i;
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wire [63:0] tied_to_ground_vec_i;
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wire tied_to_vcc_i;
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wire [63:0] tied_to_vcc_vec_i;
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//RX Datapath signals
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wire [31:0] rxdata0_i;
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wire [1:0] rxchariscomma0_float_i;
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wire [1:0] rxcharisk0_float_i;
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wire [1:0] rxdisperr0_float_i;
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wire [1:0] rxnotintable0_float_i;
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wire [1:0] rxrundisp0_float_i;
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//TX Datapath signals
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wire [31:0] txdata0_i;
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wire [1:0] txkerr0_float_i;
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wire [1:0] txrundisp0_float_i;
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//RX Datapath signals
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wire [31:0] rxdata1_i;
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wire [1:0] rxchariscomma1_float_i;
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wire [1:0] rxcharisk1_float_i;
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wire [1:0] rxdisperr1_float_i;
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wire [1:0] rxnotintable1_float_i;
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wire [1:0] rxrundisp1_float_i;
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//TX Datapath signals
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wire [31:0] txdata1_i;
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wire [1:0] txkerr1_float_i;
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wire [1:0] txrundisp1_float_i;
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//
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//********************************* Main Body of Code**************************
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//------------------------- Static signal Assigments ---------------------
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assign tied_to_ground_i = 1'b0;
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assign tied_to_ground_vec_i = 64'h0000000000000000;
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assign tied_to_vcc_i = 1'b1;
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assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
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//------------------- GTP Datapath byte mapping -----------------
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assign RXDATA0_OUT = rxdata0_i[15:0];
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// The GTP transmits little endian data (TXDATA[7:0] transmitted first)
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assign txdata0_i = {tied_to_ground_vec_i[15:0],TXDATA0_IN};
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assign RXDATA1_OUT = rxdata1_i[15:0];
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// The GTP transmits little endian data (TXDATA[7:0] transmitted first)
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assign txdata1_i = {tied_to_ground_vec_i[15:0],TXDATA1_IN};
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//------------------------ GTPA1_DUAL Instantiations -------------------------
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GTPA1_DUAL #
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(
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//_______________________ Simulation-Only Attributes __________________
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.SIM_TX_ELEC_IDLE_LEVEL ("Z"),
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.SIM_RECEIVER_DETECT_PASS ("TRUE"),
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.SIM_VERSION ("2.0"),
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.SIM_REFCLK0_SOURCE (3'b000),
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.SIM_REFCLK1_SOURCE (3'b000),
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.SIM_GTPRESET_SPEEDUP (TILE_SIM_GTPRESET_SPEEDUP),
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.CLK25_DIVIDER_0 (TILE_CLK25_DIVIDER_0),
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.CLK25_DIVIDER_1 (TILE_CLK25_DIVIDER_1),
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.PLL_DIVSEL_FB_0 (TILE_PLL_DIVSEL_FB_0),
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.PLL_DIVSEL_FB_1 (TILE_PLL_DIVSEL_FB_1),
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.PLL_DIVSEL_REF_0 (TILE_PLL_DIVSEL_REF_0),
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.PLL_DIVSEL_REF_1 (TILE_PLL_DIVSEL_REF_1),
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//PLL Attributes
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.CLKINDC_B_0 ("TRUE"),
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.CLKRCV_TRST_0 ("TRUE"),
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.OOB_CLK_DIVIDER_0 (6),
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.PLL_COM_CFG_0 (24'h21680a),
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.PLL_CP_CFG_0 (8'h00),
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.PLL_RXDIVSEL_OUT_0 (2),
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.PLL_SATA_0 ("FALSE"),
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.PLL_SOURCE_0 (TILE_PLL_SOURCE_0),
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.PLL_TXDIVSEL_OUT_0 (2),
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.PLLLKDET_CFG_0 (3'b111),
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//
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.CLKINDC_B_1 ("TRUE"),
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.CLKRCV_TRST_1 ("TRUE"),
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.OOB_CLK_DIVIDER_1 (6),
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.PLL_COM_CFG_1 (24'h21680a),
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.PLL_CP_CFG_1 (8'h00),
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.PLL_RXDIVSEL_OUT_1 (2),
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.PLL_SATA_1 ("FALSE"),
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.PLL_SOURCE_1 (TILE_PLL_SOURCE_1),
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.PLL_TXDIVSEL_OUT_1 (2),
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.PLLLKDET_CFG_1 (3'b111),
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.PMA_COM_CFG_EAST (36'h000008000),
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.PMA_COM_CFG_WEST (36'h00000a000),
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.TST_ATTR_0 (32'h00000000),
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.TST_ATTR_1 (32'h00000000),
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//TX Interface Attributes
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.CLK_OUT_GTP_SEL_0 ("TXOUTCLK0"),
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.TX_TDCC_CFG_0 (2'b00),
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.CLK_OUT_GTP_SEL_1 ("TXOUTCLK1"),
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.TX_TDCC_CFG_1 (2'b00),
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//TX Buffer and Phase Alignment Attributes
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.PMA_TX_CFG_0 (20'h00082),
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.TX_BUFFER_USE_0 ("TRUE"),
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.TX_XCLK_SEL_0 ("TXOUT"),
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.TXRX_INVERT_0 (3'b011),
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.PMA_TX_CFG_1 (20'h00082),
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.TX_BUFFER_USE_1 ("TRUE"),
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|
|
.TX_XCLK_SEL_1 ("TXOUT"),
|
| 323 |
|
|
.TXRX_INVERT_1 (3'b011),
|
| 324 |
|
|
|
| 325 |
|
|
//TX Driver and OOB signalling Attributes
|
| 326 |
|
|
.CM_TRIM_0 (2'b00),
|
| 327 |
|
|
.TX_IDLE_DELAY_0 (3'b011),
|
| 328 |
|
|
.CM_TRIM_1 (2'b00),
|
| 329 |
|
|
.TX_IDLE_DELAY_1 (3'b011),
|
| 330 |
|
|
|
| 331 |
|
|
//TX PIPE/SATA Attributes
|
| 332 |
|
|
.COM_BURST_VAL_0 (4'b1111),
|
| 333 |
|
|
.COM_BURST_VAL_1 (4'b1111),
|
| 334 |
|
|
|
| 335 |
|
|
//RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
|
| 336 |
|
|
.AC_CAP_DIS_0 ("TRUE"),
|
| 337 |
|
|
.OOBDETECT_THRESHOLD_0 (3'b110),
|
| 338 |
|
|
.PMA_CDR_SCAN_0 (27'h6404040),
|
| 339 |
|
|
.PMA_RX_CFG_0 (25'h05ce049),
|
| 340 |
|
|
.PMA_RXSYNC_CFG_0 (7'h00),
|
| 341 |
|
|
.RCV_TERM_GND_0 ("FALSE"),
|
| 342 |
|
|
.RCV_TERM_VTTRX_0 ("FALSE"),
|
| 343 |
|
|
.RXEQ_CFG_0 (8'b01111011),
|
| 344 |
|
|
.TERMINATION_CTRL_0 (5'b10100),
|
| 345 |
|
|
.TERMINATION_OVRD_0 ("FALSE"),
|
| 346 |
|
|
.TX_DETECT_RX_CFG_0 (14'h1832),
|
| 347 |
|
|
.AC_CAP_DIS_1 ("TRUE"),
|
| 348 |
|
|
.OOBDETECT_THRESHOLD_1 (3'b110),
|
| 349 |
|
|
.PMA_CDR_SCAN_1 (27'h6404040),
|
| 350 |
|
|
.PMA_RX_CFG_1 (25'h05ce049),
|
| 351 |
|
|
.PMA_RXSYNC_CFG_1 (7'h00),
|
| 352 |
|
|
.RCV_TERM_GND_1 ("FALSE"),
|
| 353 |
|
|
.RCV_TERM_VTTRX_1 ("FALSE"),
|
| 354 |
|
|
.RXEQ_CFG_1 (8'b01111011),
|
| 355 |
|
|
.TERMINATION_CTRL_1 (5'b10100),
|
| 356 |
|
|
.TERMINATION_OVRD_1 ("FALSE"),
|
| 357 |
|
|
.TX_DETECT_RX_CFG_1 (14'h1832),
|
| 358 |
|
|
|
| 359 |
|
|
//PRBS Detection Attributes
|
| 360 |
|
|
.RXPRBSERR_LOOPBACK_0 (1'b0),
|
| 361 |
|
|
.RXPRBSERR_LOOPBACK_1 (1'b0),
|
| 362 |
|
|
|
| 363 |
|
|
//Comma Detection and Alignment Attributes
|
| 364 |
|
|
.ALIGN_COMMA_WORD_0 (2),
|
| 365 |
|
|
.COMMA_10B_ENABLE_0 (10'b1111111111),
|
| 366 |
|
|
.DEC_MCOMMA_DETECT_0 ("TRUE"),
|
| 367 |
|
|
.DEC_PCOMMA_DETECT_0 ("TRUE"),
|
| 368 |
|
|
.DEC_VALID_COMMA_ONLY_0 ("FALSE"),
|
| 369 |
|
|
.MCOMMA_10B_VALUE_0 (10'b1010000011),
|
| 370 |
|
|
.MCOMMA_DETECT_0 ("TRUE"),
|
| 371 |
|
|
.PCOMMA_10B_VALUE_0 (10'b0101111100),
|
| 372 |
|
|
.PCOMMA_DETECT_0 ("TRUE"),
|
| 373 |
|
|
.RX_SLIDE_MODE_0 ("PCS"),
|
| 374 |
|
|
.ALIGN_COMMA_WORD_1 (2),
|
| 375 |
|
|
.COMMA_10B_ENABLE_1 (10'b1111111111),
|
| 376 |
|
|
.DEC_MCOMMA_DETECT_1 ("TRUE"),
|
| 377 |
|
|
.DEC_PCOMMA_DETECT_1 ("TRUE"),
|
| 378 |
|
|
.DEC_VALID_COMMA_ONLY_1 ("FALSE"),
|
| 379 |
|
|
.MCOMMA_10B_VALUE_1 (10'b1010000011),
|
| 380 |
|
|
.MCOMMA_DETECT_1 ("TRUE"),
|
| 381 |
|
|
.PCOMMA_10B_VALUE_1 (10'b0101111100),
|
| 382 |
|
|
.PCOMMA_DETECT_1 ("TRUE"),
|
| 383 |
|
|
.RX_SLIDE_MODE_1 ("PCS"),
|
| 384 |
|
|
|
| 385 |
|
|
//RX Loss-of-sync State Machine Attributes
|
| 386 |
|
|
.RX_LOS_INVALID_INCR_0 (8),
|
| 387 |
|
|
.RX_LOS_THRESHOLD_0 (128),
|
| 388 |
|
|
.RX_LOSS_OF_SYNC_FSM_0 ("FALSE"),
|
| 389 |
|
|
.RX_LOS_INVALID_INCR_1 (8),
|
| 390 |
|
|
.RX_LOS_THRESHOLD_1 (128),
|
| 391 |
|
|
.RX_LOSS_OF_SYNC_FSM_1 ("FALSE"),
|
| 392 |
|
|
|
| 393 |
|
|
//RX Elastic Buffer and Phase alignment Attributes
|
| 394 |
|
|
.RX_BUFFER_USE_0 ("TRUE"),
|
| 395 |
|
|
.RX_EN_IDLE_RESET_BUF_0 ("TRUE"),
|
| 396 |
|
|
.RX_IDLE_HI_CNT_0 (4'b1000),
|
| 397 |
|
|
.RX_IDLE_LO_CNT_0 (4'b0000),
|
| 398 |
|
|
.RX_XCLK_SEL_0 ("RXREC"),
|
| 399 |
|
|
.RX_BUFFER_USE_1 ("TRUE"),
|
| 400 |
|
|
.RX_EN_IDLE_RESET_BUF_1 ("TRUE"),
|
| 401 |
|
|
.RX_IDLE_HI_CNT_1 (4'b1000),
|
| 402 |
|
|
.RX_IDLE_LO_CNT_1 (4'b0000),
|
| 403 |
|
|
.RX_XCLK_SEL_1 ("RXREC"),
|
| 404 |
|
|
|
| 405 |
|
|
//Clock Correction Attributes
|
| 406 |
|
|
.CLK_COR_ADJ_LEN_0 (4),
|
| 407 |
|
|
.CLK_COR_DET_LEN_0 (4),
|
| 408 |
|
|
.CLK_COR_INSERT_IDLE_FLAG_0 ("FALSE"),
|
| 409 |
|
|
.CLK_COR_KEEP_IDLE_0 ("FALSE"),
|
| 410 |
|
|
.CLK_COR_MAX_LAT_0 (18),
|
| 411 |
|
|
.CLK_COR_MIN_LAT_0 (16),
|
| 412 |
|
|
.CLK_COR_PRECEDENCE_0 ("TRUE"),
|
| 413 |
|
|
.CLK_COR_REPEAT_WAIT_0 (0),
|
| 414 |
|
|
.CLK_COR_SEQ_1_1_0 (10'b0110111100),
|
| 415 |
|
|
.CLK_COR_SEQ_1_2_0 (10'b0001001010),
|
| 416 |
|
|
.CLK_COR_SEQ_1_3_0 (10'b0001001010),
|
| 417 |
|
|
.CLK_COR_SEQ_1_4_0 (10'b0001111011),
|
| 418 |
|
|
.CLK_COR_SEQ_1_ENABLE_0 (4'b1111),
|
| 419 |
|
|
.CLK_COR_SEQ_2_1_0 (10'b0100000000),
|
| 420 |
|
|
.CLK_COR_SEQ_2_2_0 (10'b0000000000),
|
| 421 |
|
|
.CLK_COR_SEQ_2_3_0 (10'b0000000000),
|
| 422 |
|
|
.CLK_COR_SEQ_2_4_0 (10'b0000000000),
|
| 423 |
|
|
.CLK_COR_SEQ_2_ENABLE_0 (4'b0000),
|
| 424 |
|
|
.CLK_COR_SEQ_2_USE_0 ("FALSE"),
|
| 425 |
|
|
.CLK_CORRECT_USE_0 ("TRUE"),
|
| 426 |
|
|
.RX_DECODE_SEQ_MATCH_0 ("TRUE"),
|
| 427 |
|
|
.CLK_COR_ADJ_LEN_1 (4),
|
| 428 |
|
|
.CLK_COR_DET_LEN_1 (4),
|
| 429 |
|
|
.CLK_COR_INSERT_IDLE_FLAG_1 ("FALSE"),
|
| 430 |
|
|
.CLK_COR_KEEP_IDLE_1 ("FALSE"),
|
| 431 |
|
|
.CLK_COR_MAX_LAT_1 (18),
|
| 432 |
|
|
.CLK_COR_MIN_LAT_1 (16),
|
| 433 |
|
|
.CLK_COR_PRECEDENCE_1 ("TRUE"),
|
| 434 |
|
|
.CLK_COR_REPEAT_WAIT_1 (0),
|
| 435 |
|
|
.CLK_COR_SEQ_1_1_1 (10'b0110111100),
|
| 436 |
|
|
.CLK_COR_SEQ_1_2_1 (10'b0001001010),
|
| 437 |
|
|
.CLK_COR_SEQ_1_3_1 (10'b0001001010),
|
| 438 |
|
|
.CLK_COR_SEQ_1_4_1 (10'b0001111011),
|
| 439 |
|
|
.CLK_COR_SEQ_1_ENABLE_1 (4'b1111),
|
| 440 |
|
|
.CLK_COR_SEQ_2_1_1 (10'b0100000000),
|
| 441 |
|
|
.CLK_COR_SEQ_2_2_1 (10'b0000000000),
|
| 442 |
|
|
.CLK_COR_SEQ_2_3_1 (10'b0000000000),
|
| 443 |
|
|
.CLK_COR_SEQ_2_4_1 (10'b0000000000),
|
| 444 |
|
|
.CLK_COR_SEQ_2_ENABLE_1 (4'b0000),
|
| 445 |
|
|
.CLK_COR_SEQ_2_USE_1 ("FALSE"),
|
| 446 |
|
|
.CLK_CORRECT_USE_1 ("TRUE"),
|
| 447 |
|
|
.RX_DECODE_SEQ_MATCH_1 ("TRUE"),
|
| 448 |
|
|
|
| 449 |
|
|
//Channel Bonding Attributes
|
| 450 |
|
|
.CHAN_BOND_1_MAX_SKEW_0 (1),
|
| 451 |
|
|
.CHAN_BOND_2_MAX_SKEW_0 (1),
|
| 452 |
|
|
.CHAN_BOND_KEEP_ALIGN_0 ("FALSE"),
|
| 453 |
|
|
.CHAN_BOND_SEQ_1_1_0 (10'b0000000000),
|
| 454 |
|
|
.CHAN_BOND_SEQ_1_2_0 (10'b0000000000),
|
| 455 |
|
|
.CHAN_BOND_SEQ_1_3_0 (10'b0000000000),
|
| 456 |
|
|
.CHAN_BOND_SEQ_1_4_0 (10'b0000000000),
|
| 457 |
|
|
.CHAN_BOND_SEQ_1_ENABLE_0 (4'b0000),
|
| 458 |
|
|
.CHAN_BOND_SEQ_2_1_0 (10'b0000000000),
|
| 459 |
|
|
.CHAN_BOND_SEQ_2_2_0 (10'b0000000000),
|
| 460 |
|
|
.CHAN_BOND_SEQ_2_3_0 (10'b0000000000),
|
| 461 |
|
|
.CHAN_BOND_SEQ_2_4_0 (10'b0000000000),
|
| 462 |
|
|
.CHAN_BOND_SEQ_2_ENABLE_0 (4'b0000),
|
| 463 |
|
|
.CHAN_BOND_SEQ_2_USE_0 ("FALSE"),
|
| 464 |
|
|
.CHAN_BOND_SEQ_LEN_0 (1),
|
| 465 |
|
|
.RX_EN_MODE_RESET_BUF_0 ("TRUE"),
|
| 466 |
|
|
.CHAN_BOND_1_MAX_SKEW_1 (1),
|
| 467 |
|
|
.CHAN_BOND_2_MAX_SKEW_1 (1),
|
| 468 |
|
|
.CHAN_BOND_KEEP_ALIGN_1 ("FALSE"),
|
| 469 |
|
|
.CHAN_BOND_SEQ_1_1_1 (10'b0000000000),
|
| 470 |
|
|
.CHAN_BOND_SEQ_1_2_1 (10'b0000000000),
|
| 471 |
|
|
.CHAN_BOND_SEQ_1_3_1 (10'b0000000000),
|
| 472 |
|
|
.CHAN_BOND_SEQ_1_4_1 (10'b0000000000),
|
| 473 |
|
|
.CHAN_BOND_SEQ_1_ENABLE_1 (4'b0000),
|
| 474 |
|
|
.CHAN_BOND_SEQ_2_1_1 (10'b0000000000),
|
| 475 |
|
|
.CHAN_BOND_SEQ_2_2_1 (10'b0000000000),
|
| 476 |
|
|
.CHAN_BOND_SEQ_2_3_1 (10'b0000000000),
|
| 477 |
|
|
.CHAN_BOND_SEQ_2_4_1 (10'b0000000000),
|
| 478 |
|
|
.CHAN_BOND_SEQ_2_ENABLE_1 (4'b0000),
|
| 479 |
|
|
.CHAN_BOND_SEQ_2_USE_1 ("FALSE"),
|
| 480 |
|
|
.CHAN_BOND_SEQ_LEN_1 (1),
|
| 481 |
|
|
.RX_EN_MODE_RESET_BUF_1 ("TRUE"),
|
| 482 |
|
|
|
| 483 |
|
|
//RX PCI Express Attributes
|
| 484 |
|
|
.CB2_INH_CC_PERIOD_0 (8),
|
| 485 |
|
|
.CDR_PH_ADJ_TIME_0 (5'b01010),
|
| 486 |
|
|
.PCI_EXPRESS_MODE_0 ("FALSE"),
|
| 487 |
|
|
.RX_EN_IDLE_HOLD_CDR_0 ("FALSE"),
|
| 488 |
|
|
.RX_EN_IDLE_RESET_FR_0 ("TRUE"),
|
| 489 |
|
|
.RX_EN_IDLE_RESET_PH_0 ("TRUE"),
|
| 490 |
|
|
.RX_STATUS_FMT_0 ("SATA"),
|
| 491 |
|
|
.TRANS_TIME_FROM_P2_0 (12'h03c),
|
| 492 |
|
|
.TRANS_TIME_NON_P2_0 (8'h19),
|
| 493 |
|
|
.TRANS_TIME_TO_P2_0 (10'h064),
|
| 494 |
|
|
.CB2_INH_CC_PERIOD_1 (8),
|
| 495 |
|
|
.CDR_PH_ADJ_TIME_1 (5'b01010),
|
| 496 |
|
|
.PCI_EXPRESS_MODE_1 ("FALSE"),
|
| 497 |
|
|
.RX_EN_IDLE_HOLD_CDR_1 ("FALSE"),
|
| 498 |
|
|
.RX_EN_IDLE_RESET_FR_1 ("TRUE"),
|
| 499 |
|
|
.RX_EN_IDLE_RESET_PH_1 ("TRUE"),
|
| 500 |
|
|
.RX_STATUS_FMT_1 ("SATA"),
|
| 501 |
|
|
.TRANS_TIME_FROM_P2_1 (12'h03c),
|
| 502 |
|
|
.TRANS_TIME_NON_P2_1 (8'h19),
|
| 503 |
|
|
.TRANS_TIME_TO_P2_1 (10'h064),
|
| 504 |
|
|
|
| 505 |
|
|
//RX SATA Attributes
|
| 506 |
|
|
.SATA_BURST_VAL_0 (3'b100),
|
| 507 |
|
|
.SATA_IDLE_VAL_0 (3'b100),
|
| 508 |
|
|
.SATA_MAX_BURST_0 (7),
|
| 509 |
|
|
.SATA_MAX_INIT_0 (22),
|
| 510 |
|
|
.SATA_MAX_WAKE_0 (7),
|
| 511 |
|
|
.SATA_MIN_BURST_0 (4),
|
| 512 |
|
|
.SATA_MIN_INIT_0 (12),
|
| 513 |
|
|
.SATA_MIN_WAKE_0 (4),
|
| 514 |
|
|
.SATA_BURST_VAL_1 (3'b100),
|
| 515 |
|
|
.SATA_IDLE_VAL_1 (3'b100),
|
| 516 |
|
|
.SATA_MAX_BURST_1 (7),
|
| 517 |
|
|
.SATA_MAX_INIT_1 (22),
|
| 518 |
|
|
.SATA_MAX_WAKE_1 (7),
|
| 519 |
|
|
.SATA_MIN_BURST_1 (4),
|
| 520 |
|
|
.SATA_MIN_INIT_1 (12),
|
| 521 |
|
|
.SATA_MIN_WAKE_1 (4)
|
| 522 |
|
|
|
| 523 |
|
|
|
| 524 |
|
|
)
|
| 525 |
|
|
gtpa1_dual_i
|
| 526 |
|
|
(
|
| 527 |
|
|
|
| 528 |
|
|
|
| 529 |
|
|
|
| 530 |
|
|
//---------------------- Loopback and Powerdown Ports ----------------------
|
| 531 |
|
|
.LOOPBACK0 (LOOPBACK0_IN),
|
| 532 |
|
|
.LOOPBACK1 (LOOPBACK1_IN),
|
| 533 |
|
|
.RXPOWERDOWN0 (tied_to_ground_vec_i[1:0]),
|
| 534 |
|
|
.RXPOWERDOWN1 (tied_to_ground_vec_i[1:0]),
|
| 535 |
|
|
.TXPOWERDOWN0 (tied_to_ground_vec_i[1:0]),
|
| 536 |
|
|
.TXPOWERDOWN1 (tied_to_ground_vec_i[1:0]),
|
| 537 |
|
|
//------------------------------- PLL Ports --------------------------------
|
| 538 |
|
|
.CLK00 (CLK00_IN),
|
| 539 |
|
|
.CLK01 (CLK01_IN),
|
| 540 |
|
|
.CLK10 (tied_to_ground_i),
|
| 541 |
|
|
.CLK11 (tied_to_ground_i),
|
| 542 |
|
|
.CLKINEAST0 (tied_to_ground_i),
|
| 543 |
|
|
.CLKINEAST1 (tied_to_ground_i),
|
| 544 |
|
|
.CLKINWEST0 (tied_to_ground_i),
|
| 545 |
|
|
.CLKINWEST1 (tied_to_ground_i),
|
| 546 |
|
|
.GCLK00 (tied_to_ground_i),
|
| 547 |
|
|
.GCLK01 (tied_to_ground_i),
|
| 548 |
|
|
.GCLK10 (tied_to_ground_i),
|
| 549 |
|
|
.GCLK11 (tied_to_ground_i),
|
| 550 |
|
|
.GTPRESET0 (GTPRESET0_IN),
|
| 551 |
|
|
.GTPRESET1 (GTPRESET1_IN),
|
| 552 |
|
|
.GTPTEST0 (8'b00010000),
|
| 553 |
|
|
.GTPTEST1 (8'b00010000),
|
| 554 |
|
|
.INTDATAWIDTH0 (tied_to_vcc_i),
|
| 555 |
|
|
.INTDATAWIDTH1 (tied_to_vcc_i),
|
| 556 |
|
|
.PLLCLK00 (tied_to_ground_i),
|
| 557 |
|
|
.PLLCLK01 (tied_to_ground_i),
|
| 558 |
|
|
.PLLCLK10 (tied_to_ground_i),
|
| 559 |
|
|
.PLLCLK11 (tied_to_ground_i),
|
| 560 |
|
|
.PLLLKDET0 (PLLLKDET0_OUT),
|
| 561 |
|
|
.PLLLKDET1 (PLLLKDET1_OUT),
|
| 562 |
|
|
.PLLLKDETEN0 (tied_to_vcc_i),
|
| 563 |
|
|
.PLLLKDETEN1 (tied_to_vcc_i),
|
| 564 |
|
|
.PLLPOWERDOWN0 (tied_to_ground_i),
|
| 565 |
|
|
.PLLPOWERDOWN1 (tied_to_ground_i),
|
| 566 |
|
|
.REFCLKOUT0 (),
|
| 567 |
|
|
.REFCLKOUT1 (),
|
| 568 |
|
|
.REFCLKPLL0 (),
|
| 569 |
|
|
.REFCLKPLL1 (),
|
| 570 |
|
|
.REFCLKPWRDNB0 (tied_to_vcc_i),
|
| 571 |
|
|
.REFCLKPWRDNB1 (tied_to_vcc_i),
|
| 572 |
|
|
.REFSELDYPLL0 (tied_to_ground_vec_i[2:0]),
|
| 573 |
|
|
.REFSELDYPLL1 (tied_to_ground_vec_i[2:0]),
|
| 574 |
|
|
.RESETDONE0 (RESETDONE0_OUT),
|
| 575 |
|
|
.RESETDONE1 (RESETDONE1_OUT),
|
| 576 |
|
|
.TSTCLK0 (tied_to_ground_i),
|
| 577 |
|
|
.TSTCLK1 (tied_to_ground_i),
|
| 578 |
|
|
.TSTIN0 (tied_to_ground_vec_i[11:0]),
|
| 579 |
|
|
.TSTIN1 (tied_to_ground_vec_i[11:0]),
|
| 580 |
|
|
.TSTOUT0 (),
|
| 581 |
|
|
.TSTOUT1 (),
|
| 582 |
|
|
//--------------------- Receive Ports - 8b10b Decoder ----------------------
|
| 583 |
|
|
.RXCHARISCOMMA0 ({rxchariscomma0_float_i,RXCHARISCOMMA0_OUT}),
|
| 584 |
|
|
.RXCHARISCOMMA1 ({rxchariscomma1_float_i,RXCHARISCOMMA1_OUT}),
|
| 585 |
|
|
.RXCHARISK0 ({rxcharisk0_float_i,RXCHARISK0_OUT}),
|
| 586 |
|
|
.RXCHARISK1 ({rxcharisk1_float_i,RXCHARISK1_OUT}),
|
| 587 |
|
|
.RXDEC8B10BUSE0 (tied_to_vcc_i),
|
| 588 |
|
|
.RXDEC8B10BUSE1 (tied_to_vcc_i),
|
| 589 |
|
|
.RXDISPERR0 ({rxdisperr0_float_i,RXDISPERR0_OUT}),
|
| 590 |
|
|
.RXDISPERR1 ({rxdisperr1_float_i,RXDISPERR1_OUT}),
|
| 591 |
|
|
.RXNOTINTABLE0 ({rxnotintable0_float_i,RXNOTINTABLE0_OUT}),
|
| 592 |
|
|
.RXNOTINTABLE1 ({rxnotintable1_float_i,RXNOTINTABLE1_OUT}),
|
| 593 |
|
|
.RXRUNDISP0 (),
|
| 594 |
|
|
.RXRUNDISP1 (),
|
| 595 |
|
|
.USRCODEERR0 (tied_to_ground_i),
|
| 596 |
|
|
.USRCODEERR1 (tied_to_ground_i),
|
| 597 |
|
|
//-------------------- Receive Ports - Channel Bonding ---------------------
|
| 598 |
|
|
.RXCHANBONDSEQ0 (),
|
| 599 |
|
|
.RXCHANBONDSEQ1 (),
|
| 600 |
|
|
.RXCHANISALIGNED0 (),
|
| 601 |
|
|
.RXCHANISALIGNED1 (),
|
| 602 |
|
|
.RXCHANREALIGN0 (),
|
| 603 |
|
|
.RXCHANREALIGN1 (),
|
| 604 |
|
|
.RXCHBONDI (tied_to_ground_vec_i[2:0]),
|
| 605 |
|
|
.RXCHBONDMASTER0 (tied_to_ground_i),
|
| 606 |
|
|
.RXCHBONDMASTER1 (tied_to_ground_i),
|
| 607 |
|
|
.RXCHBONDO (),
|
| 608 |
|
|
.RXCHBONDSLAVE0 (tied_to_ground_i),
|
| 609 |
|
|
.RXCHBONDSLAVE1 (tied_to_ground_i),
|
| 610 |
|
|
.RXENCHANSYNC0 (tied_to_ground_i),
|
| 611 |
|
|
.RXENCHANSYNC1 (tied_to_ground_i),
|
| 612 |
|
|
//-------------------- Receive Ports - Clock Correction --------------------
|
| 613 |
|
|
.RXCLKCORCNT0 (RXCLKCORCNT0_OUT),
|
| 614 |
|
|
.RXCLKCORCNT1 (RXCLKCORCNT1_OUT),
|
| 615 |
|
|
//------------- Receive Ports - Comma Detection and Alignment --------------
|
| 616 |
|
|
.RXBYTEISALIGNED0 (RXBYTEISALIGNED0_OUT),
|
| 617 |
|
|
.RXBYTEISALIGNED1 (RXBYTEISALIGNED1_OUT),
|
| 618 |
|
|
.RXBYTEREALIGN0 (),
|
| 619 |
|
|
.RXBYTEREALIGN1 (),
|
| 620 |
|
|
.RXCOMMADET0 (),
|
| 621 |
|
|
.RXCOMMADET1 (),
|
| 622 |
|
|
.RXCOMMADETUSE0 (tied_to_vcc_i),
|
| 623 |
|
|
.RXCOMMADETUSE1 (tied_to_vcc_i),
|
| 624 |
|
|
.RXENMCOMMAALIGN0 (RXENMCOMMAALIGN0_IN),
|
| 625 |
|
|
.RXENMCOMMAALIGN1 (RXENMCOMMAALIGN1_IN),
|
| 626 |
|
|
.RXENPCOMMAALIGN0 (RXENPCOMMAALIGN0_IN),
|
| 627 |
|
|
.RXENPCOMMAALIGN1 (RXENPCOMMAALIGN1_IN),
|
| 628 |
|
|
.RXSLIDE0 (tied_to_ground_i),
|
| 629 |
|
|
.RXSLIDE1 (tied_to_ground_i),
|
| 630 |
|
|
//--------------------- Receive Ports - PRBS Detection ---------------------
|
| 631 |
|
|
.PRBSCNTRESET0 (tied_to_ground_i),
|
| 632 |
|
|
.PRBSCNTRESET1 (tied_to_ground_i),
|
| 633 |
|
|
.RXENPRBSTST0 (tied_to_ground_vec_i[2:0]),
|
| 634 |
|
|
.RXENPRBSTST1 (tied_to_ground_vec_i[2:0]),
|
| 635 |
|
|
.RXPRBSERR0 (),
|
| 636 |
|
|
.RXPRBSERR1 (),
|
| 637 |
|
|
//----------------- Receive Ports - RX Data Path interface -----------------
|
| 638 |
|
|
.RXDATA0 (rxdata0_i),
|
| 639 |
|
|
.RXDATA1 (rxdata1_i),
|
| 640 |
|
|
.RXDATAWIDTH0 (2'b01),
|
| 641 |
|
|
.RXDATAWIDTH1 (2'b01),
|
| 642 |
|
|
.RXRECCLK0 (RXRECCLK0_OUT),
|
| 643 |
|
|
.RXRECCLK1 (RXRECCLK1_OUT),
|
| 644 |
|
|
.RXRESET0 (RXRESET0_IN),
|
| 645 |
|
|
.RXRESET1 (RXRESET1_IN),
|
| 646 |
|
|
.RXUSRCLK0 (RXUSRCLK0_IN),
|
| 647 |
|
|
.RXUSRCLK1 (RXUSRCLK1_IN),
|
| 648 |
|
|
.RXUSRCLK20 (RXUSRCLK20_IN),
|
| 649 |
|
|
.RXUSRCLK21 (RXUSRCLK21_IN),
|
| 650 |
|
|
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
| 651 |
|
|
.GATERXELECIDLE0 (GATERXELECIDLE0_IN),
|
| 652 |
|
|
.GATERXELECIDLE1 (GATERXELECIDLE1_IN),
|
| 653 |
|
|
.IGNORESIGDET0 (IGNORESIGDET0_IN),
|
| 654 |
|
|
.IGNORESIGDET1 (IGNORESIGDET1_IN),
|
| 655 |
|
|
.RCALINEAST (tied_to_ground_vec_i[4:0]),
|
| 656 |
|
|
.RCALINWEST (tied_to_ground_vec_i[4:0]),
|
| 657 |
|
|
.RCALOUTEAST (),
|
| 658 |
|
|
.RCALOUTWEST (),
|
| 659 |
|
|
.RXCDRRESET0 (tied_to_ground_i),
|
| 660 |
|
|
.RXCDRRESET1 (tied_to_ground_i),
|
| 661 |
|
|
.RXELECIDLE0 (RXELECIDLE0_OUT),
|
| 662 |
|
|
.RXELECIDLE1 (RXELECIDLE1_OUT),
|
| 663 |
|
|
.RXEQMIX0 (RXEQMIX0_IN),
|
| 664 |
|
|
.RXEQMIX1 (RXEQMIX1_IN),
|
| 665 |
|
|
.RXN0 (RXN0_IN),
|
| 666 |
|
|
.RXN1 (RXN1_IN),
|
| 667 |
|
|
.RXP0 (RXP0_IN),
|
| 668 |
|
|
.RXP1 (RXP1_IN),
|
| 669 |
|
|
//--------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
|
| 670 |
|
|
.RXBUFRESET0 (tied_to_ground_i),
|
| 671 |
|
|
.RXBUFRESET1 (tied_to_ground_i),
|
| 672 |
|
|
.RXBUFSTATUS0 (),
|
| 673 |
|
|
.RXBUFSTATUS1 (),
|
| 674 |
|
|
.RXENPMAPHASEALIGN0 (tied_to_ground_i),
|
| 675 |
|
|
.RXENPMAPHASEALIGN1 (tied_to_ground_i),
|
| 676 |
|
|
.RXPMASETPHASE0 (tied_to_ground_i),
|
| 677 |
|
|
.RXPMASETPHASE1 (tied_to_ground_i),
|
| 678 |
|
|
.RXSTATUS0 (RXSTATUS0_OUT),
|
| 679 |
|
|
.RXSTATUS1 (RXSTATUS1_OUT),
|
| 680 |
|
|
//------------- Receive Ports - RX Loss-of-sync State Machine --------------
|
| 681 |
|
|
.RXLOSSOFSYNC0 (),
|
| 682 |
|
|
.RXLOSSOFSYNC1 (),
|
| 683 |
|
|
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
|
| 684 |
|
|
.PHYSTATUS0 (),
|
| 685 |
|
|
.PHYSTATUS1 (),
|
| 686 |
|
|
.RXVALID0 (),
|
| 687 |
|
|
.RXVALID1 (),
|
| 688 |
|
|
//------------------ Receive Ports - RX Polarity Control -------------------
|
| 689 |
|
|
.RXPOLARITY0 (tied_to_ground_i),
|
| 690 |
|
|
.RXPOLARITY1 (tied_to_ground_i),
|
| 691 |
|
|
//----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
|
| 692 |
|
|
.DADDR (tied_to_ground_vec_i[7:0]),
|
| 693 |
|
|
.DCLK (tied_to_ground_i),
|
| 694 |
|
|
.DEN (tied_to_ground_i),
|
| 695 |
|
|
.DI (tied_to_ground_vec_i[15:0]),
|
| 696 |
|
|
.DRDY (),
|
| 697 |
|
|
.DRPDO (),
|
| 698 |
|
|
.DWE (tied_to_ground_i),
|
| 699 |
|
|
//-------------------------- TX/RX Datapath Ports --------------------------
|
| 700 |
|
|
.GTPCLKFBEAST (),
|
| 701 |
|
|
.GTPCLKFBSEL0EAST (2'b10),
|
| 702 |
|
|
.GTPCLKFBSEL0WEST (2'b00),
|
| 703 |
|
|
.GTPCLKFBSEL1EAST (2'b11),
|
| 704 |
|
|
.GTPCLKFBSEL1WEST (2'b01),
|
| 705 |
|
|
.GTPCLKFBWEST (),
|
| 706 |
|
|
.GTPCLKOUT0 (GTPCLKOUT0_OUT),
|
| 707 |
|
|
.GTPCLKOUT1 (GTPCLKOUT1_OUT),
|
| 708 |
|
|
//----------------- Transmit Ports - 8b10b Encoder Control -----------------
|
| 709 |
|
|
.TXBYPASS8B10B0 (tied_to_ground_vec_i[3:0]),
|
| 710 |
|
|
.TXBYPASS8B10B1 (tied_to_ground_vec_i[3:0]),
|
| 711 |
|
|
.TXCHARDISPMODE0 (tied_to_ground_vec_i[3:0]),
|
| 712 |
|
|
.TXCHARDISPMODE1 (tied_to_ground_vec_i[3:0]),
|
| 713 |
|
|
.TXCHARDISPVAL0 (tied_to_ground_vec_i[3:0]),
|
| 714 |
|
|
.TXCHARDISPVAL1 (tied_to_ground_vec_i[3:0]),
|
| 715 |
|
|
.TXCHARISK0 ({tied_to_ground_vec_i[1:0],TXCHARISK0_IN}),
|
| 716 |
|
|
.TXCHARISK1 ({tied_to_ground_vec_i[1:0],TXCHARISK1_IN}),
|
| 717 |
|
|
.TXENC8B10BUSE0 (tied_to_vcc_i),
|
| 718 |
|
|
.TXENC8B10BUSE1 (tied_to_vcc_i),
|
| 719 |
|
|
.TXKERR0 (),
|
| 720 |
|
|
.TXKERR1 (),
|
| 721 |
|
|
.TXRUNDISP0 (),
|
| 722 |
|
|
.TXRUNDISP1 (),
|
| 723 |
|
|
//------------- Transmit Ports - TX Buffer and Phase Alignment -------------
|
| 724 |
|
|
.TXBUFSTATUS0 (),
|
| 725 |
|
|
.TXBUFSTATUS1 (),
|
| 726 |
|
|
.TXENPMAPHASEALIGN0 (tied_to_ground_i),
|
| 727 |
|
|
.TXENPMAPHASEALIGN1 (tied_to_ground_i),
|
| 728 |
|
|
.TXPMASETPHASE0 (tied_to_ground_i),
|
| 729 |
|
|
.TXPMASETPHASE1 (tied_to_ground_i),
|
| 730 |
|
|
//---------------- Transmit Ports - TX Data Path interface -----------------
|
| 731 |
|
|
.TXDATA0 (txdata0_i),
|
| 732 |
|
|
.TXDATA1 (txdata1_i),
|
| 733 |
|
|
.TXDATAWIDTH0 (2'b01),
|
| 734 |
|
|
.TXDATAWIDTH1 (2'b01),
|
| 735 |
|
|
.TXOUTCLK0 (TXOUTCLK0_OUT),
|
| 736 |
|
|
.TXOUTCLK1 (TXOUTCLK1_OUT),
|
| 737 |
|
|
.TXRESET0 (TXRESET0_IN),
|
| 738 |
|
|
.TXRESET1 (TXRESET1_IN),
|
| 739 |
|
|
.TXUSRCLK0 (TXUSRCLK0_IN),
|
| 740 |
|
|
.TXUSRCLK1 (TXUSRCLK1_IN),
|
| 741 |
|
|
.TXUSRCLK20 (TXUSRCLK20_IN),
|
| 742 |
|
|
.TXUSRCLK21 (TXUSRCLK21_IN),
|
| 743 |
|
|
//------------- Transmit Ports - TX Driver and OOB signalling --------------
|
| 744 |
|
|
.TXBUFDIFFCTRL0 (3'b101),
|
| 745 |
|
|
.TXBUFDIFFCTRL1 (3'b101),
|
| 746 |
|
|
.TXDIFFCTRL0 (TXDIFFCTRL0_IN),
|
| 747 |
|
|
.TXDIFFCTRL1 (TXDIFFCTRL1_IN),
|
| 748 |
|
|
.TXINHIBIT0 (tied_to_ground_i),
|
| 749 |
|
|
.TXINHIBIT1 (tied_to_ground_i),
|
| 750 |
|
|
.TXN0 (TXN0_OUT),
|
| 751 |
|
|
.TXN1 (TXN1_OUT),
|
| 752 |
|
|
.TXP0 (TXP0_OUT),
|
| 753 |
|
|
.TXP1 (TXP1_OUT),
|
| 754 |
|
|
.TXPREEMPHASIS0 (TXPREEMPHASIS0_IN),
|
| 755 |
|
|
.TXPREEMPHASIS1 (TXPREEMPHASIS1_IN),
|
| 756 |
|
|
//------------------- Transmit Ports - TX PRBS Generator -------------------
|
| 757 |
|
|
.TXENPRBSTST0 (tied_to_ground_vec_i[2:0]),
|
| 758 |
|
|
.TXENPRBSTST1 (tied_to_ground_vec_i[2:0]),
|
| 759 |
|
|
.TXPRBSFORCEERR0 (tied_to_ground_i),
|
| 760 |
|
|
.TXPRBSFORCEERR1 (tied_to_ground_i),
|
| 761 |
|
|
//------------------ Transmit Ports - TX Polarity Control ------------------
|
| 762 |
|
|
.TXPOLARITY0 (tied_to_ground_i),
|
| 763 |
|
|
.TXPOLARITY1 (tied_to_ground_i),
|
| 764 |
|
|
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
|
| 765 |
|
|
.TXDETECTRX0 (tied_to_ground_i),
|
| 766 |
|
|
.TXDETECTRX1 (tied_to_ground_i),
|
| 767 |
|
|
.TXELECIDLE0 (TXELECIDLE0_IN),
|
| 768 |
|
|
.TXELECIDLE1 (TXELECIDLE1_IN),
|
| 769 |
|
|
.TXPDOWNASYNCH0 (tied_to_ground_i),
|
| 770 |
|
|
.TXPDOWNASYNCH1 (tied_to_ground_i),
|
| 771 |
|
|
//------------------- Transmit Ports - TX Ports for SATA -------------------
|
| 772 |
|
|
.TXCOMSTART0 (TXCOMSTART0_IN),
|
| 773 |
|
|
.TXCOMSTART1 (TXCOMSTART1_IN),
|
| 774 |
|
|
.TXCOMTYPE0 (TXCOMTYPE0_IN),
|
| 775 |
|
|
.TXCOMTYPE1 (TXCOMTYPE1_IN)
|
| 776 |
|
|
|
| 777 |
|
|
);
|
| 778 |
|
|
|
| 779 |
|
|
endmodule
|
| 780 |
|
|
|
